TW202516832A - Quasi-resonant flyback converter operating with a constant switching frequency and valley-switching controller therefor - Google Patents

Abstract

A quasi-resonant flyback converter is capable of operating with a constant switching frequency over a wide range of input voltage variation and load current variation. The valley switching controller of said quasi-resonant flyback converter includes a m-multiple clock generator which issues m pulses per switching cycle corresponding to said constant switching frequency. Said valley switching controller turns on the power switch of said quasi-resonant flyback converter at the first drain-source voltage valley following the first instance of said m pulses, but no later than the second instance of said m pulses. Said valley switching controller turns off said power switch when the input current sense signal rises above a regulation error voltage level, but no later than the third instance of said m pulses.

Description

Translated fromChinese

操作在單一恆定頻率的準諧振式返馳變換器及其波谷切換控制器Quasi-resonant flyback converter operating at a single constant frequency and its valley switching controller

本發明一般涉及脈寬調變（PWM）開關式電源供應器領域，尤其涉及用於在準諧振模式或波谷切換模式下工作的脈寬調變開關式電源供應器的控制電路和方法。The present invention generally relates to the field of pulse width modulation (PWM) switching power supplies, and more particularly to a control circuit and method for a pulse width modulation switching power supply operating in a quasi-resonant mode or a valley switching mode.

返馳轉換器通常被採納於離線或交流至直流電源供應器應用。返馳轉換器使用之功率變壓器，可同時實現三項功能：功率傳輸，電壓升降，和絕緣隔離。當功率開關接通 (turn on) 時，流經一次側繞組的一次側電流開始上升，從而在功率變壓器的磁芯中形成更高的磁通密度。當功率開關關閉時，一次側電流換向 (commutate) 至二次側繞組，二次側電流則流過輸出二極體並進入輸出電容器和負載電路。然後，以磁通密度形式存儲的能量被釋放到負載電路。通常，返馳轉換器的控制器會改變功率開關的導通佔空比，在一個輸入電壓或負載電流較大變化範圍內將輸出電壓調節到一個恆定水準。Flyback converters are usually used in offline or AC to DC power supply applications. The power transformer used in flyback converters can simultaneously achieve three functions: power transmission, voltage step-up and step-down, and insulation isolation. When the power switch is turned on, the primary current flowing through the primary winding When the power switch is turned off, the primary current commutates to the secondary winding, and the secondary current The current flows through the output diode and into the output capacitor and load circuit. The energy stored in the form of magnetic flux density is then released to the load circuit. Typically, the controller of a flyback converter varies the on-time duty cycle of the power switch to regulate the output voltage to a constant level over a wide range of input voltage or load current.

返馳轉換器可以設計為在連續導通模式 (CCM)，或在非連續導通模式 (DCM)下工作。在 CCM 操作模式中，其功率開關會在二次側電流尚未降到零時接通。請注意，在 CCM 操作模式，開關週期等於與之和。其中，通常被稱為「導通時間」 (on time)。則通常被稱為「退磁時間」 (demagnetizing time)。請又注意，在功率開關接通瞬間之前，其汲極-源極電壓差額，是處於。其中，是為功率變壓器一次側繞組匝數 ;是為功率變壓器二次側繞組匝數。A flyback converter can be designed to operate in either continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In CCM operation, the power switch conducts current on the secondary side. Please note that in CCM operation mode, the switching cycle Equal to and The sum of. Often referred to as "on time". This is usually called the "demagnetizing time". Please also note that before the power switch is turned on, the drain-source voltage difference , is in .in, is the number of turns of the primary winding of the power transformer; is the number of turns of the secondary winding of the power transformer.

相較之下，在 DCM 操作模式中，其功率開關會在二次側電流已經降到零之後才接通。請注意，在 DCM 操作模式，開關週期，等於，與三者之和。其中，通常被稱為「停滯時間」(dead time)。而在期間，功率開關的汲源極電壓會在一個波峰值，以及一個波谷值之間往復振盪。因此，功率開關接通瞬間之前的實際汲源極電壓會落在上述波峰值與波谷值之間。In contrast, in DCM operation, the power switch will switch the secondary current Note that in DCM operation, the switching cycle , which is equal to ,and The sum of the three. Among them, Often referred to as "dead time". During this period, the drain-source voltage of the power switch Will be in one The peak value, and a Therefore, the actual drain-source voltage before the power switch is turned on is It will fall between the peak and trough values mentioned above.

請注意，在期間，汲源極電壓振盪的諧振週期時間，，是由與組合成的諧振迴路來決定。其中，為功率變壓器一次側繞組的激磁電感值。則為功率開關的汲源極之間的寄生電容值。亦即，。而功率開關的切換損耗，，由下列公式決定:---公式 (1)。其中，為返馳轉換器的操作(開關)頻率，而且。而另一方面，準諧振式返馳轉換器，通常也稱為波谷切換返馳轉換器，實際上是屬於常規 DCM 返馳轉換器的一個類別，但使用一種波谷檢測方法來確保功率開關始終在汲源極電壓振盪到一個波谷時才接通，因而可以將其切換損耗降到最低程度。但是，目前所有已知準諧振式返馳轉換器都採用某種波谷鎖定或波谷追蹤機制，藉以達到波谷切換的特性。可是這些波谷鎖定機制都會造成其操作頻率隨著輸入電壓變化或負載電流變化而起較大的變化。通常典型的操作頻率變化範圍大約在 2:1，但也有高達 3:1 的實例。但是，操作頻率變化範圍如此巨大的準諧振式返馳轉換器可能存在幾個缺點：(a) 設計一個堅韌可靠的波谷鎖定機制是相當複雜的任務。設計者必須耗費更長的開發和驗證時間。(b) 操作頻率變動太大時，造成轉換器的電磁干擾防治更難處理。Please note that During this period, the drain-source voltage The harmonic period of the oscillation, , is and The combined resonant loop determines the is the magnetizing inductance of the primary winding of the power transformer. is the parasitic capacitance between the drain and source of the power switch. That is, . The switching loss of the power switch is , determined by the following formula: ---Formula (1). Where, is the operating (switching) frequency of the foldback converter, and On the other hand, a quasi-resonant flyback converter, also commonly called a valley-switching flyback converter, is actually a type of conventional DCM flyback converter, but uses a valley detection method to ensure that the power switch is always switched at the drain-source voltage. The oscillation is turned on only when it reaches a trough, so that the switching loss can be reduced. However, all known quasi-resonant flyback converters use some kind of valley locking or valley tracking mechanism to achieve the valley switching characteristics. However, these valley locking mechanisms will cause their operating frequency to vary greatly with changes in input voltage or load current. The typical operating frequency variation range is usually about 2:1, but there are also examples as high as 3:1. However, quasi-resonant flyback converters with such a large operating frequency variation range may have several disadvantages: (a) Designing a robust and reliable valley locking mechanism is a very complex task. Designers must spend more time on development and verification. (b) When the operating frequency changes too much, it becomes more difficult to prevent and control electromagnetic interference of the converter.

因此在開關式電源領域，本發明提出一種改良的準諧振式返馳轉換器，該轉換器能夠在輸入電壓和輸出負載電流變化的全範圍內以一個恆定的開關頻率工作。Therefore, in the field of switching power supply, the present invention proposes an improved quasi-resonant flyback converter, which can operate at a constant switching frequency within the full range of input voltage and output load current changes.

傳統的脈寬調變（PWM）返馳轉換器通常操作在電流控制模式和一恆定開關頻率。它可以設計為在連續導通模式（CCM）或在非連續導通模式（DCM）下工作。因為它具有簡單的電源電路拓撲結構，使用最少數量的功率元件，所以返馳轉換器被普遍應用於手機電池充電器等低功耗電源產品。如圖 1 所示，一典型的常規PWM 返馳轉換器 100 耦合到輸入電壓 110，並將輸入電壓 110 轉換為輸出電壓 120。返馳轉換器 100 的一次側電路主要包括輸入濾波電容器 111，功率變壓器 113，功率開關 117，電流偵測電阻 118，可選的緩衝電路 112 和 脈寬調變控制器 130。返馳轉換器 100 的二次側電路主要包括輸出二極體 121，輸出濾波電容器 125，並聯調節器 150，及光耦合器 160。A conventional pulse width modulation (PWM) flyback converter usually operates in current control mode and a constant switching frequency. It can be designed to operate in continuous conduction mode (CCM) or in discontinuous conduction mode (DCM). Because it has a simple power circuit topology and uses a minimum number of power components, flyback converters are widely used in low-power power products such as mobile phone battery chargers. As shown in FIG1 , a typical conventionalPWM flyback converter 100 is coupled to aninput voltage 110 and converts theinput voltage 110 into anoutput voltage 120. The primary circuit of theflyback converter 100 mainly includes aninput filter capacitor 111, apower transformer 113, apower switch 117, acurrent detection resistor 118, anoptional buffer circuit 112 and a pulsewidth modulation controller 130. The secondary circuit of theflyback converter 100 mainly includes anoutput diode 121, anoutput filter capacitor 125, ashunt regulator 150, and anoptical coupler 160.

前述功率變壓器 113 的鐵氧體磁芯安裝有三個繞組：一次側繞組; 二次側繞組; 偏置電壓繞組(114)。 一次側繞組的第一端耦合到輸入電壓 110。一次側繞組的第二端則耦合到功率開關 117 的汲極。二次側繞組的第一端耦合到二次側的共同接地點 ; 二次側繞組的第二端則耦合到輸出二極體 121 的陽極。偏置電壓繞組則產生電壓予於脈寬調變控制器 130。The ferrite core of thepower transformer 113 is equipped with three windings: a primary winding ; Secondary winding ; Bias voltage winding (114). Primary winding assembly The first end of the primary winding is coupled to theinput voltage 110. The second end of the secondary winding is coupled to the drain of thepower switch 117. The first end is coupled to the common ground point of the secondary side; the secondary side winding The second end of is coupled to the anode of theoutput diode 121. Then it will produce The voltage is given to thePWM controller 130.

前述脈寬調變控制器 130 主要包括 PWM 時鐘產生器 131，SR正反器 133，閘極驅動放大器 134，電流斜坡比較器 135，和誤差電壓分壓器 140。前述並聯穩壓器 150 包括誤差放大器 151。並聯穩壓器 150 通過使用由電阻 123 和電阻 124 組成的電阻分壓器來檢測輸出電壓 120 的電位，並將該電阻分壓器的輸出電壓 126 耦合到誤差放大器 151 的反相輸入端。誤差放大器 151 的正相輸入端則耦合到一個精密參考電壓 152，例如 2.50V。電容器 153 是一可選的反饋補償元件。基本上，誤差放大器 151 的功能是根據分壓電位 126 與參考電壓 152 的時間加權電位偏差量以產生誤差電壓信號 154。例如，如果分壓電位 126 在一段時間內低於參考電壓 152，則誤差電壓信號 154 將往 5.0V方向上升。另一方面，如果分壓電位 126 在一段時間內高於參考電壓 152，則誤差電壓信號 154 將往 0.0V 方向下降。而誤差電壓信號 154 則耦合到光耦合器 160 的輸入端。光耦合器 160 的功能基本上是將二次側的誤差電壓信號 154 耦合至一次側，並複製產生幅度大致相同的一次側誤差電壓 139，並將其連結到誤差電壓分壓器 140 的輸入端。The pulsewidth modulation controller 130 mainly includes aPWM clock generator 131, an SR flip-flop 133, agate drive amplifier 134, acurrent slope comparator 135, and anerror voltage divider 140. Theparallel voltage regulator 150 includes anerror amplifier 151. Theparallel voltage regulator 150 detects the potential of theoutput voltage 120 by using a resistor divider composed of aresistor 123 and aresistor 124, and couples theoutput voltage 126 of the resistor divider to the inverting input terminal of theerror amplifier 151. The non-inverting input of theerror amplifier 151 is coupled to aprecision reference voltage 152, such as 2.50V. Capacitor 153 is an optional feedback compensation element. Basically, the function of theerror amplifier 151 is to generate anerror voltage signal 154 according to the time-weighted potential deviation between the dividedvoltage 126 and thereference voltage 152. For example, if the dividedvoltage 126 is lower than thereference voltage 152 for a period of time, theerror voltage signal 154 will rise towards 5.0V. On the other hand, if the dividedvoltage 126 is higher than thereference voltage 152 for a period of time, theerror voltage signal 154 will decrease towards 0.0V. Theerror voltage signal 154 is coupled to the input of theoptocoupler 160. The function of theoptocoupler 160 is basically to couple the secondaryerror voltage signal 154 to the primary side and replicate theprimary error voltage 139 of approximately the same amplitude and connect it to the input of theerror voltage divider 140.

請注意，一般做法是將誤差電壓信號 154 和一次側誤差電壓 139 都設計為操作在 0.0V 至 5.0V 的電壓區間。誤差電壓分壓器 140 的功用則是將一次側誤差電壓 139 縮減成一個調節用誤差信號 136，其工作電壓區間下調到 0.0V 至大約 1.2V。另一方面，在脈寬調變控制器 130 之中，PWM 時鐘產生器 131 產生一個恆定頻率的 PWM 時鐘信號 132。於圖 1 返馳轉換器的範例中，PWM 時鐘信號 132 的恆定頻率是設定在 100 kHz，如圖 2(a) 所示。而且圖 1 返馳轉換器的範例中，輸入電壓110 是設定在 300V ; 輸出電壓120 則是設定在 20V; 全載電流設定在 3.0 A。圖 2 所示為圖 1 返馳轉換器工作在連續導通模式 (CCM) 時的關鍵信號波形。Please note that the general practice is to design theerror voltage signal 154 and theprimary error voltage 139 to operate in the voltage range of 0.0V to 5.0V. The function of theerror voltage divider 140 is to reduce theprimary error voltage 139 to a regulatingerror signal 136, whose operating voltage range is adjusted down to 0.0V to about 1.2V. On the other hand, in the pulsewidth modulation controller 130, thePWM clock generator 131 generates a constant frequencyPWM clock signal 132. In the example of the flyback converter of FIG1 , the constant frequency of thePWM clock signal 132 is set at 100 kHz, as shown in FIG2(a). Also, in the example of the flyback converter of FIG1 , theinput voltage 110 is set at 300V;output voltage 120 is set at 20V; full load current is set at 3.0 A. Figure 2 shows the key signal waveforms when the flyback converter in Figure 1 operates in continuous conduction mode (CCM).

當工作在一個穩定的 CCM 狀態下，每個 PWM 時鐘信號 132 的脈衝將觸動 SR正反器 133，其輸出信號轉正並耦合至閘極驅動放大器 134。而後者的輸出信號 137 轉成高位，而將功率開關 117 立即接通。功率開關 117 接通之後，一次側電流 115 (開始流經一次側繞組，功率開關 117，以及電流偵測電阻118，並且穩定上升。一次側電流 115 自一個初始谷值，，按照一個的斜率上升。其中，是為一次側繞組的激磁電感，則為時間變數。上升中的一次側電流 115，其波形如圖 2(c) 所示，會在電流偵測電阻 118 感應出一個電流偵測信號 138， 如圖 2(d) 所示。然後，當此電流偵測信號 138 上升到超越調節用誤差信號 136 的準位時，電流斜坡比較器 135 的輸出信號立即自低位轉成高位。此動作導致 SR 正反器 133 的重置。而 SR 正反器的重置直接導致閘極驅動放大器 134 和功率開關 117 依序關斷，如圖 2(b) 至圖 2(e) 所示。請注意，功率開關 117 導通一次側電流 115 的時間，通常被稱為「導通時間」(。When operating in a stable CCM state, each pulse of thePWM clock signal 132 will trigger the SR flip-flop 133, whose output signal turns positive and is coupled to thegate driver amplifier 134. The latter'soutput signal 137 turns high and immediately turns on thepower switch 117. After thepower switch 117 is turned on, the primary current 115 ( Starts to flow through the primary winding ,power switch 117, andcurrent detection resistor 118, and rises steadily. Theprimary current 115 rises from an initial valley value, , according to a The slope of is increasing. This is a side winding group The magnetizing inductance is is a time variable. The risingprimary current 115, whose waveform is shown in FIG2(c), will induce acurrent detection signal 138 in thecurrent detection resistor 118, as shown in FIG2(d). Then, when thecurrent detection signal 138 rises to a level exceeding theerror signal 136 for regulation, the output signal of thecurrent slope comparator 135 immediately changes from a low level to a high level. This action causes the SR flip-flop 133 to be reset. The reset of the SR flip-flop directly causes thegate driver amplifier 134 and thepower switch 117 to be turned off in sequence, as shown in FIG2(b) to FIG2(e). Note that the time that thepower switch 117 conducts theprimary current 115 is usually referred to as the "on time" ( .

而在功率開關 117 關斷瞬間，一次側電流 115 立即停止在一次側導通，並且切換至二次側，形成二次側電流(122)。此電流自二次繞組經由輸出二極體 121 流向輸出濾波電容器 125 和負載電路。請注意，自功率開關 117 關斷一次側電流 115 直到下一週期之初功率開關 117 再度被接通的時間，，通常又被稱為「退磁時間」。而在期間，二次側電流 122 按照一個的斜率下降。其中，是為二次側繞組的激磁電感值，則為時間變數。請注意，在CCM 操作模式中，開關週期時間是等於與相加之和，易言之，。另請注意，在功率開關 117 關斷瞬間，其汲源極電壓會自幾近於零跳升至的高準位。而且，在 CCM 操作模式中，一次側電流 115 和二次側電流 122 不會在任何時間點同時為零。在期間，一次側電流115 自一個起始谷值上升。在時間結束時，一次側電流 115 會上升至一個的峰值。而在期間，二次側電流 122 自一個起始峰值下降。在時間結束時，二次側電流 122 會下降至一個的谷值，如圖 2(c) 所示。請注意，根據前述之公式 (1)，在CCM操作模式中，返馳轉換器會承受較多的切換損耗。這是因為功率開關 117 一直在其汲源極電壓116 停留在一個最高準位，的狀況下瞬間導通。例如，假設功率開關 117 的汲源極之間寄生電容等於 100pF，為 300V，為 150V，亦即= 450V。再如前設定，等於 100kHz。將上述各值代入公式 (1)，則可以算出功率開關 117 操作在 CCM 模式的切換損耗為 1.01W。When thepower switch 117 is turned off, the primary current 115 stops conducting on the primary side and switches to the secondary side, forming a secondary current (122). This current flows from the secondary winding Flows through theoutput diode 121 to theoutput filter capacitor 125 and the load circuit. Note that the time from when thepower switch 117 turns off theprimary current 115 until thepower switch 117 is turned on again at the beginning of the next cycle is , often referred to as "demagnetization time" . And in During this period, the secondary current 122 follows a The slope of is decreasing. It is the secondary winding group The magnetizing inductance value is is the time variable. Note that in CCM operation, the switching cycle time is equal to and The sum of the additions, in other words, . Also note that at the moment thepower switch 117 is turned off, its drain-source voltage It will jump from almost zero to Furthermore, in the CCM operation mode, the primary current 115 and the secondary current 122 are not zero at any point in time. During this period, the primary current 115 from a The initial valley value rises. At the end of the time, the primary current 115 will rise to a peak value. During this period, the secondary current 122 from a The initial peak value decreases. At the end of the time, the secondary current 122 will drop to a As shown in FIG2(c), please note that according to the above formula (1), in CCM operation mode, the flyback converter will suffer more switching loss. This is because thepower switch 117 is always at its drain-source voltage 116 Stay at the highest level, For example, assuming that the parasitic capacitance between the drain and source of thepower switch 117 is Equivalent to 100pF, 300V, is 150V, that is = 450V. As before, Substituting the above values into formula (1), it can be calculated that the switching loss of thepower switch 117 operating in CCM mode is 1.01W.

事實上，圖 1 返馳轉換器可以很容易被修改成為 DCM 模式下工作，這修改只需將功率變壓器的激磁電感值大幅調降，而其他電路設計參數基本上維持不變。DCM 模式與 CCM 模式主要相異處，就在於前者的開關週期時間，是等於，與三者之和。亦即在期間，一次側電流 115 自零值上升。在時間結束時，一次側電流 115 會上升至一個的峰值。而在期間，二次側電流 122 自一個起始值下降。在時間結束時，二次側電流 122 會下降至零。而在期間，二次側電流 122 和一次側電流 115 都同時停留在零的準位。所以通常又被稱為停滯時間，如圖 3(c) 所示。請注意，在期間，功率開關 117 的汲源極電壓 116，會在一個波峰值，以及一個波谷值之間往復振盪。如前述，汲源極電壓振盪的諧振週期時間，，等於。In fact, the flyback converter in Figure 1 can be easily modified to operate in DCM mode. This modification only requires a significant reduction in the magnetizing inductance of the power transformer, while other circuit design parameters remain essentially unchanged. The main difference between DCM mode and CCM mode is the switching cycle time of the former. is equal to ,and The sum of the three. exist During this period, the primary current 115 rises from zero. At the end of the time, the primary current 115 will rise to a The peak value of During this period, the secondary current 122 from a The starting value decreases. At the end of the time, the secondary current 122 will drop to zero. During this period, the secondary current 122 and the primary current 115 both stay at zero level at the same time. Often referred to as dwell time , as shown in Figure 3(c). Note that During this period, the drain-source voltage 116 of thepower switch 117 will be The peak value, and a As mentioned above, the drain-source voltage The harmonic period of the oscillation, , which is equal to .

請注意，功率開關 117 接通瞬間前的實際汲源極電壓，，會落在上述波峰值與波谷值之間，如圖 3(e) 所示。一般而言，的數值會受到數項因素影響，包括和的各別長度，輸入電壓 110，以及負載電流的大小。事實上，DCM 返馳轉換器的汲源極電壓會於期間在一波峰值與一波谷值之間進行諧振式振盪的特性，乃是準諧振式返馳轉換器，通常也稱為波谷切換返馳轉換器的原始概念形成的起源。此原始概念之所以形成，其原因也並不複雜。根據公式 (1)，功率開關 117 的切換損耗是正比於的平方值。所以，如果我們可以設計出一個控制方法，確保功率開關 117 固定在其汲源極電壓 116 振盪到某一個波谷時才接通，就可以將切換損耗減少到一個最低的程度。Note that the actual drain-source voltage immediately before thepower switch 117 is turned on is , will fall between the peak and trough values mentioned above, as shown in Figure 3(e). Generally speaking, The value of is affected by several factors, including and The respective lengths of theinput voltage 110, and the magnitude of the load current. In fact, the drain-source voltage of the DCM flyback converter will be The characteristic of resonant oscillation between a peak value and a valley value during the period is the origin of the original concept of the quasi-resonant flyback converter, which is also commonly called the valley switching flyback converter. The reason why this original concept was formed is not complicated. According to formula (1), the switching loss of thepower switch 117 is proportional to Therefore, if we can design a control method to ensure that thepower switch 117 is fixed when its drain-source voltage 116 oscillates to a certain valley before turning on, the switching loss can be reduced to a minimum.

總言之， 準諧振式或者波谷切換返馳轉換器可被視為 DCM 返馳轉換器的一個子類別。圖 4 示出了現今準諧振式返馳轉換器的一個典型實施例，例如: On-Semi 的 NCP1345; 德州儀器的 UCC28600 ; 英飛淩的 ICE5QSAG。一般而言，現今準諧振式返馳轉換器不同於常規 DCM 返馳轉換器主要在於其三個獨特的子電路：(a) 零交越檢測子電路; (b) 第N波谷鎖定控制子電路; (c) 開關頻率上下限子電路，如圖 4 中準諧振式返馳轉換器 400 所用之波谷切換控制器 450 所示。 請注意如圖 1 所示，功率變壓器 113 的偏置電壓繞組(114) 原本的功能是為脈寬調變控制器 130 提供一個操作電壓 ()。然而，在準諧振式返馳轉換器 400 之中，偏置電壓繞組 114 尚可耦合到零交越檢測子電路 410，該子電路包括電阻分壓器 411 和 412 以及電壓比較器 451，如圖 4 所示。電阻分壓器 411 和 412 輸出一個波谷檢測信號 413。此波谷檢測信號 413 基本上是汲源極電壓波形的壓縮版本，但是去除其直流成分，如圖 5 所示。In summary, a quasi-resonant or valley-switching flyback converter can be considered a subcategory of a DCM flyback converter. FIG4 shows a typical implementation of a current quasi-resonant flyback converter, such as: NCP1345 from On-Semi; UCC28600 from Texas Instruments; ICE5QSAG from Infineon. Generally speaking, current quasi-resonant flyback converters differ from conventional DCM flyback converters primarily in their three unique subcircuits: (a) a zero-crossing detection subcircuit; (b) an Nth valley lock control subcircuit; and (c) a switching frequency upper and lower limit subcircuit, as shown in thevalley switching controller 450 used in thequasi-resonant flyback converter 400 in FIG4. Please note that as shown in FIG1, the bias voltage winding of the power transformer 113 (114) The original function is to provide an operating voltage for the pulse width modulation controller 130 ( ). However, in thequasi-resonant flyback converter 400, the bias voltage winding 114 can also be coupled to a zero-crossing detection subcircuit 410, which includesresistor dividers 411 and 412 and avoltage comparator 451, as shown in FIG4. Theresistor dividers 411 and 412 output avalley detection signal 413. Thevalley detection signal 413 is basically the drain-source voltage. A compressed version of the waveform, but with its DC component removed, is shown in Figure 5.

然後，波谷檢測信號 413 被耦合到電壓比較器 451 的反相輸入端，其正相輸入端連結到幾近於零的參考電位。電壓比較器 451 的輸出稱為零交越信號 452。然後零交越信號 452 耦合到第N個波谷鎖定控制子電路 453 的第一個輸入端。請注意如圖 5(d) 和圖 5(e) 所示，在每個開關週期的期間，零交越信號 452 的第一個上升緣預告即將到來的第一個波谷。零交越信號 452 的第二個上升緣預告即將到來的第二個波谷，如此類推。請再注意，開關頻率上下限子電路 455 的輸入端是耦合到 SR 正反器 133 的輸出端，以檢測準諧振式返馳轉換器 400 目前的開關頻率是否漂移到所設定的上限以上，或者漂移到所設定的下限以下。開關頻率上下限子電路 455 的輸出信號 456 耦合到第N個波谷鎖定控制子電路 453 的第二個輸入端，如圖 4 所示。Then, thevalley detection signal 413 is coupled to the inverting input of thevoltage comparator 451, whose non-inverting input is connected to a reference potential close to zero. The output of thevoltage comparator 451 is called the zero-crossing signal 452. The zero-crossing signal 452 is then coupled to the first input terminal of the Nth valleylock control subcircuit 453. Please note that as shown in Figure 5(d) and Figure 5(e), in each switching cycle During this period, the first rising edge of the zero-crossing signal 452 indicates the first The second rising edge of the zero-crossing signal 452 indicates the coming second trough, and so on. Please note that the input end of the switching frequency upper andlower limit sub-circuit 455 is coupled to the output end of the SR flip-flop 133 to detect whether the current switching frequency of thequasi-resonant flyback converter 400 drifts to Above the upper limit, or drifting to Theoutput signal 456 of the switching frequency upper andlower limit sub-circuit 455 is coupled to the second input terminal of the Nth valleylock control sub-circuit 453, as shown in FIG4.

圖 6 顯示先前準諧振式返馳轉換器的一個典型波谷鎖定機制及其操作流程圖 600。以圖 4 的準諧振式返馳轉換器為例，波谷切換控制器 450 在步驟 601 開始其操作，N 的初始值被設定為 1。在完成步驟 602 的一個週期轉換器開關動作之後，波谷切換控制器 450 於步驟 603 檢查前一個開關週期的開關頻率是否超過預設上限。如果步驟 603 的結果是肯定的，則波谷切換控制器 450 繼續執行步驟 604，其中 N 的數值增加 1。然後波谷切換控制器 450 的操作返回到步驟 602。另一方面，如果步驟 603 的結果是否定的，則波谷切換控制器 450 繼續執行步驟 605，在此它檢查前一個開關週期的開關頻率是否已降至預設下限以下。如果步驟 605 的結果是肯定的，並且 N 的原先數值大於 1，則波谷切換控制器 450 繼續執行步驟 606，其中 N 的數值減去 1。然後波谷切換控制器 450 的操作返回到步驟 602。但是，如果步驟 605 的結果是否定的，那麼我們知道前一個開關週期的開關頻率是保持在上限和下限之間。因此，無需更改 N 的數值。然後波谷切換控制器 450 的操作返回到步驟 602。請注意，在實際設計中，和不必然是兩個固定值。大多數現今波谷切換控制器都會根據 N 的現值來調整和的設定值。FIG6 shows a typical valley locking mechanism of a prior art quasi-resonant flyback converter and itsoperation flow chart 600. Taking the quasi-resonant flyback converter of FIG4 as an example, thevalley switching controller 450 starts its operation atstep 601, and the initial value of N is set to 1. After completing a cycle of converter switching action atstep 602, thevalley switching controller 450 checks the switching frequency of the previous switching cycle atstep 603. Whether it exceeds the default limit If the result ofstep 603 is positive, thevalley switching controller 450 proceeds to step 604, where the value of N is increased by 1. The operation of thevalley switching controller 450 then returns to step 602. On the other hand, if the result ofstep 603 is negative, thevalley switching controller 450 proceeds to step 605, where it checks the switching frequency of the previous switching cycle. Has it fallen to the default lower limit? If the result ofstep 605 is positive, and the previous value of N is greater than 1, thevalley switching controller 450 proceeds to step 606, where the value of N is reduced by 1. The operation of thevalley switching controller 450 then returns to step 602. However, if the result ofstep 605 is negative, then we know the switching frequency of the previous switching cycle. is maintained between the upper and lower limits. Therefore, there is no need to change the value of N. Then the operation of thevalley switching controller 450 returns to step 602. Please note that in actual design, and Not necessarily two fixed values. Most current valley switching controllers adjust according to the current value of N. and The setting value of .

圖 7 顯示了一個典型波谷切換控制器的開關頻率對應於負載電流的特性曲線。請注意，從100% 負載到大約 50% 負載，波谷切換控制器 450 會在第一個波谷時接通功率開關 117。但是，會從 100% 負載時的 50kHz上升到 50% 負載時的約略 100kHz。從 50% 負載到大約 37% 負載，波谷切換控制器 450 會在第二個波谷時接通功率開關 117。從 37% 負載到大約 28% 負載，則在第三個波谷時動作。從 28% 負載到 19% 負載，則在第四個波谷時動作。從 19% 負載到大約 11% 負載，則在第五個波谷時動作。低於 11% 負載時，大多數現今波谷切換控制器將進入某種低頻跳越模式操作。Figure 7 shows the switching frequency of a typical valley switching controller. The characteristic curve corresponding to the load current. Note that from 100% load to about 50% load, thevalley switching controller 450 turns on thepower switch 117 at the first valley. However, will rise from 50kHz at 100% load to approximately 100kHz at 50% load. From 50% load to approximately 37% load, thevalley switching controller 450 will turn on thepower switch 117 at the second valley. From 37% load to approximately 28% load, it will act at the third valley. From 28% load to 19% load, it will act at the fourth valley. From 19% load to approximately 11% load, it will act at the fifth valley. Below 11% load, most of today's valley switching controllers will enter some kind of low frequency skip mode operation.

圖 8 顯示了圖 4 準諧振式返馳轉換器，工作在四種不同的負載電流條件下，其汲源極電壓 116 和電流偵測信號 138 的波形。對應於 100% 負載和 50% 負載， 波谷切換控制器 450 在第一個波谷時接通功率開關 117，如圖 8(a) 及 8(b) 所示。對應於 40% 的負載，它會在第二個波谷時動作，如圖 8(c) 所示。對應於 15% 的負載，它會在第五個波谷時動作，如圖 8(d) 所示。FIG8 shows the waveforms of the drain-source voltage 116 and thecurrent detection signal 138 of the quasi-resonant flyback converter of FIG4 under four different load current conditions. Corresponding to 100% load and 50% load, thevalley switching controller 450 switches to the first Thepower switch 117 is turned on at the valley, as shown in Figures 8(a) and 8(b). Corresponding to a 40% load, it will The trough action is shown in Figure 8(c). Corresponding to a 15% load, it will be at the fifth The action at the trough is shown in Figure 8(d).

然而，現有準諧振式返馳轉換器及其波谷切換控制器存在兩個缺點：(a) 第N個波谷鎖定機制相當複雜，它給控制器的設計和驗證帶來了額外的負擔。(b) 開關頻率範圍變化較大，可能導致較高的 EMI 雜訊水準。However, the existing quasi-resonant flyback converter and its valley switching controller have two disadvantages: (a) The Nth valley locking mechanism is quite complicated, which brings additional burden to the design and verification of the controller. (b) The switching frequency Larger range variations may result in higher EMI noise levels.

圖 9 顯示了本發明的一個優選實施例。恆定頻率準諧振式返馳轉換器 900 包括定頻波谷切換控制器 950。而定頻波谷切換控制器 950 則包括波谷檢測子電路，m 倍速時鐘產生器 953，和導通空檔 (turn-on window) 子電路 954。該 m 倍速時鐘產生器 953 以預定開關頻率的 m 倍速度發出一系列脈衝，其中 m 是等於或大於 3 的整數。在圖 9 的示範實施例中，預定開關頻率為 100kHz，而 m 設定為 4。換言之，m 倍速時鐘產生器 953 會以 400kHz 的頻率在每一個開關週期之內，發出四個脈衝，分別標記為，，及，如圖 10(a) 所示。脈衝及耦合到導通空檔子電路 954，其輸出稱為導通空檔 (turn-on window) 信號 955，如圖 10(b) 所示。在圖 9 優選實施例中，導通空檔是從脈衝開始，到脈衝結束。該導通空檔會限制 SR正反器 133 只能在脈衝之後出現的第一個波谷時才能設定（set）。但是，當處於啟動暫態或短時間過載條件下時，該準諧振式返馳轉換器可能會漂移到連續導通模式，造成在整個正常開關週期內都不會產生任何波谷。因此，在導通空檔結束時，如果仍然沒有出現任何波谷，脈衝將逕自設定 SR正反器 133。而 SR正反器 133 的復歸（reset），它是由兩個條件觸發：(a) 當 ISEN 信號 138 超越調節用誤差信號 136，或 (b) 脈衝已經到來。請注意，採用條件 (b) 是為了防止定頻準諧振式返馳轉換器 900 以大於 50% 的佔空比工作，引發穩定度問題。FIG9 shows a preferred embodiment of the present invention. The constant frequencyquasi-harmonic flyback converter 900 includes a constant frequencyvalley switching controller 950. The constant frequencyvalley switching controller 950 includes a valley detection subcircuit, an m-speed clock generator 953, and a turn-onwindow subcircuit 954. The m-speed clock generator 953 generates a series of pulses at a speed m times the predetermined switching frequency, where m is an integer equal to or greater than 3. In the exemplary embodiment of FIG9, the predetermined switching frequency is 100kHz, and m is set to 4. In other words, the m-speed clock generator 953 will generate four pulses at a frequency of 400kHz in each switching cycle, marked as , ,and , as shown in Figure 10(a). and The turn-on window is coupled to the turn-onwindow subcircuit 954, whose output is called the turn-onwindow signal 955, as shown in FIG10(b). In the preferred embodiment of FIG9, the turn-on window is generated from the pulse Start, to pulse The conduction gap will limit the SR flip-flop 133 to only be able to The first one that appeared after However, during a startup transient or short-term overload condition, the quasi-resonant flyback converter may drift into continuous conduction mode, resulting in no current being generated during the entire normal switching cycle. Therefore, at the end of the conduction gap, if there is still no Trough, Pulse The SR flip-flop 133 is reset automatically. The reset of the SR flip-flop 133 is triggered by two conditions: (a) when theISEN signal 138 exceeds theregulation error signal 136, or (b) when the pulse Note that condition (b) is adopted to prevent the fixed-frequencyquasi-resonant flyback converter 900 from operating at a duty cycle greater than 50%, which would cause stability problems.

圖 10 顯示了圖 9 優選實施例在三個不同負載電流水準下工作的關鍵波形。圖 10(a) 顯示了每個開關週期的四倍脈衝。圖 10(b) 顯示導通空檔信號 955，其範圍自脈衝出現開始，到脈衝出現結束。圖 10(c) 顯示當定頻準諧振式返馳轉換器 900 操作在 100% 負載電流時，其116 和138 的波形。圖 10(d) 顯示當定頻準諧振式返馳轉換器 900 操作在 66% 負載電流時，其116 和138 的波形。請注意，在開關週期 1，2，和 4 中，功率開關 117 在第二個波谷處導通。但在開關週期 3 和 5 中，功率開關 117 在第一個波谷處導通。圖 10(e) 顯示當定頻準諧振式返馳轉換器 900 操作在 25% 負載電流時，其116 和138 的波形。請注意，在除了開關週期 4 以外的所有開關週期中，功率開關 117 在第五個波谷處導通。但在開關週期 4 中，功率開關 117 在第四個波谷處導通。FIG10 shows the key waveforms of the preferred embodiment of FIG9 operating at three different load current levels. FIG10(a) shows the quadruple pulse of each switching cycle. FIG10(b) shows the conductionidle signal 955, which ranges from the pulse Start to pulse FIG10(c) shows that when the fixed-frequencyquasi-resonant flyback converter 900 operates at 100% load current, its 116 and 138. FIG10(d) shows that when the fixed frequencyquasi-resonant flyback converter 900 operates at 66% load current, its 116 and 138. Note that in switchingcycles 1, 2, and 4,power switch 117 is However, in switchingcycles 3 and 5, thepower switch 117 is turned on at the first FIG10(e) shows that when the fixed frequencyquasi-resonant flyback converter 900 operates at 25% load current, its 116 and 138. Note that in all switching cycles except switchingcycle 4,power switch 117 is However, in switchingcycle 4, thepower switch 117 is turned on at the fourth Conductivity at the trough.

請注意，如圖 10(d) 和圖 10(e) 所示，本發明並無要求在穩態操作中，每個開關週期必須具有完全相同的週期時間。事實上，每個開關週期可以略長或略短於 10.0 us，這是對應於 100kHz 預定開關頻率的開關週期時間。但是，在操作一段時間後， 這些開關週期的平均值會正好等於 10.0 us。這是由於導通空檔信號 955 對 SR正反器 133 施加的一種同步效應。請另注意，定頻波谷切換控制器 950 有一個設計限制，該設計限制要求導通空檔信號 955 的寬度必須大於諧振振蕩的週期時間。如先所述，。實際上，只要定頻準諧振式返馳轉換器 900 在 DCM 模式中工作，遵守這個設計限制就可保證在每個開關週期的導通空檔信號 955 期間至少會出現一次波谷。Please note that, as shown in Figures 10(d) and 10(e), the present invention does not require that each switching cycle must have exactly the same cycle time in steady-state operation. In fact, each switching cycle can be slightly longer or shorter than 10.0 us, which is the switching cycle time corresponding to a predetermined switching frequency of 100kHz. However, after a period of operation, the average value of these switching cycles will be exactly equal to 10.0 us. This is due to a synchronization effect exerted by the on-time signal 955 on the SR flip-flop 133. Please also note that the fixed frequencyvalley switching controller 950 has a design limitation that requires that the width of the on-time signal 955 must be greater than the cycle time of the resonant oscillation. As mentioned above, In fact, as long as the fixed-frequencyquasi-resonant flyback converter 900 operates in DCM mode, complying with this design restriction can ensure that the conductionidle signal 955 will appear at least once during each switching cycle. trough.

雖然已經通過範例和優選實施例描述了本發明，但應當理解，本發明不限於所公開的實施例。相反地，其本意乃在涵蓋對本領域技術人員顯而易見的各種修改和類似的安排。Although the present invention has been described by way of examples and preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements that are obvious to those skilled in the art.

100:PWM 返馳轉換器 110:輸入電壓 111:輸入濾波電容器 112:緩衝電路 (snubber circuit) 113:功率變壓器 114:功率變壓器的繞組 115:一次側電流 116:功率開關的汲源極電壓 117:功率開關 118:電流偵測電阻 120:輸出電壓 121:輸出二極體 122:二次側電流 123,124:分壓電阻 125:輸出濾波電容器 126:電阻分壓器的輸出電壓 130:脈寬調變控制器 131:PWM時鐘產生器 132:PWM時鐘信號 133:SR正反器 134:閘極驅動放大器 135:電流斜坡比較器 136:調節用誤差信號 137:閘極驅動信號 138:電流偵測信號 139:一次側誤差電壓 150:並聯調節器 (shunt regulator) 151:誤差放大器 152:參考電壓 153:可選的反饋補償元件 154:誤差電壓信號 160:光耦合器 411,412:分壓電阻 413:波谷檢測信號 450:波谷切換控制器 451:電壓比較器 452:零交越信號 453:第N個波谷鎖定控制子電路 455:開關頻率上下限子電路 456:開關頻率上下限子電路455的輸出信號 600:波谷鎖定機制操作流程圖 601:波谷鎖定機制操作流程的起始步驟 602:流程步驟，執行一個週期的轉換器開關動作 603:流程步驟，檢視開關頻率是否超過預設上限 604:流程步驟，N的數值增加1 605:流程步驟，檢視開關頻率是否低於預設下限 606:流程步驟，N的數值減去1 900:定頻準諧振式返馳轉換器 950:定頻波谷切換控制器 953:四倍速時鐘產生器 954:導通空檔子電路 955:導通空檔信號100: PWM flyback converter 110: input voltage 111: input filter capacitor 112: snubber circuit 113: power transformer 114: power transformer Winding 115: Primary current 116: Power switch drain-source voltage 117: Power switch 118: Current detection resistor 120: Output voltage 121: Output diode 122: Secondary current 123, 124: Divider resistor 125: Output filter capacitor 126: Output voltage of resistor divider 130: Pulse width modulation Controller 131: PWM clock generator 132: PWM clock signal 133: SR flip-flop 134: gate drive amplifier 135: current slope comparator 136: error signal for regulation 137: gate drive signal 138: current detection signal 139: primary side error voltage 150: shunt regulator 151: Error amplifier 152: Reference voltage 153: Optional feedback compensation element 154: Error voltage signal 160: Optocoupler 411, 412: Divider resistor 413: Valley detection signal 450: Valley switching controller 451: Voltage comparator 452: Zero crossing signal 453: Nth valley lock control Control sub-circuit 455: Switching frequency upper and lower limit sub-circuit 456: Output signal of switching frequency upper and lower limit sub-circuit 455 600: Valley lock mechanism operation flow chart 601: Starting step of valley lock mechanism operation flow 602: Flow step, execute a cycle of converter switching action 603: Flow step, check the switching frequency Whether it exceeds the preset upper limit 604: process step, the value of N increases by 1 605: process step, check the switching frequency Is it lower than the preset lower limit 606: process step, the value of N is reduced by 1 900: fixed frequency quasi-harmonic flyback converter 950: fixed frequency valley switching controller 953: four-speed clock generator 954: conduction idle sub-circuit 955: conduction idle signal

圖 1 所示為在連續導通模式或非連續導通模式下工作的傳統電流控制模式的脈寬調變返馳轉換器。Figure 1 shows a conventional current control mode PWM flyback converter operating in either continuous conduction mode or discontinuous conduction mode.

圖 2 所示為圖 1 返馳轉換器工作在連續導通模式時的關鍵信號波形。Figure 2 shows the key signal waveforms when the flyback converter in Figure 1 operates in continuous conduction mode.

圖 3 所示為圖 1 返馳轉換器工作在非連續導通模式時的關鍵信號波形。Figure 3 shows the key signal waveforms when the flyback converter in Figure 1 operates in discontinuous conduction mode.

圖 4 所示為先前技術準諧振式返馳轉換器的一個實施範例。FIG4 shows an example implementation of a prior art quasi-resonant flyback converter.

圖 5 所示為圖 4 準諧振式返馳轉換器中波谷偵測線路的關鍵信號波形。Figure 5 shows the key signal waveforms of the valley detection circuit in the quasi-resonant flyback converter of Figure 4.

圖 6 所示為圖 4 準諧振式返馳轉換器使用的一個典型波谷鎖定機制的操作流程圖。FIG6 is a flow chart showing the operation of a typical valley locking mechanism used in the quasi-resonant flyback converter of FIG4.

圖 7 所示為圖 4 準諧振式返馳轉換器的開關頻率相對於負載電流的典型特性曲線。Figure 7 shows the typical characteristic curve of the switching frequency versus load current of the quasi-resonant flyback converter in Figure 4.

圖 8 所示為圖 4 準諧振式返馳轉換器在不同負載電流狀況下的關鍵信號波形。Figure 8 shows the key signal waveforms of the quasi-resonant flyback converter in Figure 4 under different load current conditions.

圖 9 所示為根據本發明的一個優選實施例的恆定頻率準諧振式返馳轉換器的示意圖。FIG9 is a schematic diagram of a constant frequency quasi-resonant flyback converter according to a preferred embodiment of the present invention.

圖 10 所示為圖 9 恆定頻率準諧振式返馳轉換器在不同負載電流條件下的關鍵信號波形。Figure 10 shows the key signal waveforms of the constant frequency quasi-resonant flyback converter in Figure 9 under different load current conditions.

請注意，除非另有說明，術語「耦合」及其相關的動詞形式涵蓋本領域已知的各種直接和間接電路連結或其他非電路連結方式。Please note that unless otherwise stated, the term "couple" and its related verb forms cover various direct and indirect circuit connections or other non-circuit connection methods known in the art.

110:輸入電壓110: Input voltage

111:輸入濾波電容器111: Input filter capacitor

112:緩衝電路(snubber circuit)112: Snubber circuit

113:功率變壓器113: Power transformer

114:功率變壓器的n₃繞組114:n3 winding_of power transformer

115:一次側電流115: Primary current

116:功率開關的汲源極電壓116: Power switch drain-source voltage

117:功率開關117: Power switch

118:電流偵測電阻118: Current detection resistor

120:輸出電壓120: Output voltage

121:輸出二極體121: Output diode

122:二次側電流122: Secondary current

123,124:分壓電阻123,124: voltage divider resistor

125:輸出濾波電容器125: Output filter capacitor

133:SR正反器133:SR flip-flop

134:閘極驅動放大器134: Gate driver amplifier

135:電流斜坡比較器135: Current ramp comparator

136:調節用誤差信號136: Error signal for adjustment

137:閘極驅動信號137: Gate drive signal

138:電流偵測信號138: Current detection signal

139:一次側誤差電壓139: Primary side error voltage

150:並聯調節器(shunt regulator)150: Shunt regulator

154:誤差電壓信號154: Error voltage signal

160:光耦合器160: Optocoupler

411,412:分壓電阻411,412: voltage divider resistor

413:波谷檢測信號413: Trough detection signal

451:電壓比較器451: Voltage comparator

452:零交越信號452: Zero crossing signal

900:定頻準諧振式返馳轉換器900: Fixed frequency quasi-resonant flyback converter

950:定頻波谷切換控制器950: Constant frequency valley switching controller

953:四倍速時鐘產生器953: Quadruple speed clock generator

954:導通空檔子電路954: Turn on the neutral sub-circuit

955:導通空檔信號955: conduction neutral signal

Claims (10)

Translated fromChinese

一種準諧振式返馳轉換器，在輸入電壓變化和輸出電流變化的較大範圍內以恆定的開關頻率工作，包括：一個功率變壓器，一個功率開關，一個輸出二極體，一個輸出濾波電容器，以及一個波谷切換控制器 ; 所述波谷切換控制器則包括一個波谷信號分壓子電路，一個波谷檢測子電路，一個m倍速時鐘產生器，和一個導通空檔信號子電路，該導通空檔信號子電路產生一個導通空檔信號。A quasi-resonant flyback converter operates at a constant switching frequency within a wide range of input voltage variation and output current variation, comprising: a power transformer, a power switch, an output diode, an output filter capacitor, and a valley switching controller; the valley switching controller comprises a valley signal voltage divider circuit, a valley detection circuit, an m-times-speed clock generator, and a conduction neutral signal circuit, which generates a conduction neutral signal.請求項1所述的功率變壓器，包括一個第一繞組，一個第二繞組，和一個第三繞組，所述第一繞組的第一端耦合到所述準諧振式返馳轉換器的輸入電壓，所述第一繞組的第二端耦合到所述功率開關的汲極，所述第二繞組的第一端耦合到所述準諧振式返馳轉換器的二次側接地點，所述第二繞組的第二端耦合到所述輸出二極體的陽極，該輸出二極體的陰極則耦合到所述輸出濾波電容器的正極，所述第三繞組耦合到所述波谷信號分壓子電路，其輸出信號耦合到所述波谷檢測子電路。The power transformer described in claim 1 includes a first winding, a second winding, and a third winding, wherein the first end of the first winding is coupled to the input voltage of the quasi-resonant flyback converter, the second end of the first winding is coupled to the drain of the power switch, the first end of the second winding is coupled to the secondary side ground of the quasi-resonant flyback converter, the second end of the second winding is coupled to the anode of the output diode, the cathode of the output diode is coupled to the positive electrode of the output filter capacitor, and the third winding is coupled to the valley signal divider circuit, and its output signal is coupled to the valley detection circuit.請求項1所述的波谷檢測子電路在每一次所述功率開關的汲源極電壓振盪至低於所述準諧振式返馳轉換器的輸入電壓電位時發出一次波谷預告信號。The valley detection subcircuit described in claim 1 sends a valley warning signal each time the drain-source voltage of the power switch oscillates to a level lower than the input voltage of the quasi-resonant flyback converter.請求項1所述的m倍速時鐘產生器，在所述準諧振式返馳轉換器的每個開關週期內發出m個脈衝，其中m為等於或大於3的整數，所述m個脈衝的第一例將所述導通空檔信號切換到高電位狀態，所述m個脈衝的第二例將所述導通空檔信號切換到低電位狀態。The m-fold speed clock generator described in claim 1 emits m pulses in each switching cycle of the quasi-resonant flyback converter, wherein m is an integer equal to or greater than 3, and the first of the m pulses switches the conduction idle signal to a high potential state, and the second of the m pulses switches the conduction idle signal to a low potential state.請求項1所述的波谷切換控制器，在所述導通空檔信號處於高電位的狀態下，並且首次出現波谷預告信號時接通所述功率開關，但是如果在整個導通空檔信號處於高電位的時間內未發生任何波谷預告信號，所述波谷切換控制器則隨即接通所述功率開關。The valley switching controller described in claim 1 turns on the power switch when the on-state neutral signal is at a high level and the valley warning signal appears for the first time. However, if no valley warning signal occurs during the entire time when the on-state neutral signal is at a high level, the valley switching controller immediately turns on the power switch.請求項1所述的波谷切換控制器另又使用所述m個脈衝的第三例來關閉功率開關，以便於將所述準諧振式返馳轉換器的佔空比限制在一個預設最大值之內。The valley switching controller described in claim 1 further uses a third instance of the m pulses to turn off the power switch so as to limit the duty cycle of the quasi-resonant flyback converter to a preset maximum value.一種波谷切換控制器，用於驅動在非連續導通模式下工作的定頻返馳轉換器的功率開關，所述波谷切換控制器包括一個波谷檢測子電路，一個m倍速時鐘產生器，和一個導通空檔信號子電路，所述導通空檔信號子電路產生一個導通空檔信號。A valley switching controller is used to drive a power switch of a constant frequency flyback converter operating in a discontinuous conduction mode. The valley switching controller includes a valley detection subcircuit, an m-times-speed clock generator, and a conduction neutral signal subcircuit. The conduction neutral signal subcircuit generates a conduction neutral signal.請求項7所述波谷檢測子電路在每一次所述功率開關的汲源極電壓振盪至低於所述定頻返馳轉換器的輸入電壓電位時發出一次波谷預告信號。The valley detection subcircuit of claim 7 sends a valley warning signal each time the drain-source voltage of the power switch oscillates to a level lower than the input voltage of the fixed-frequency flyback converter.請求項7所述 m倍速時鐘產生器，在所述定頻返馳轉換器的每個開關週期內發出m個脈衝，其中m為等於或大於3的整數，所述m個脈衝的第一例將所述導通空檔信號切換到高電位狀態，所述m個脈衝的第二例將所述導通空檔信號切換到低電位狀態。The m-times-speed clock generator described in claim 7 emits m pulses in each switching cycle of the fixed-frequency flyback converter, wherein m is an integer equal to or greater than 3, and the first of the m pulses switches the conduction idle signal to a high potential state, and the second of the m pulses switches the conduction idle signal to a low potential state.請求項7所述波谷切換控制器，在所述導通空檔信號處於高電位的狀態下，並且首次出現波谷預告信號時接通所述功率開關，但是如果在整個導通空檔信號處於高電位的時間內未發生任何波谷預告信號，所述波谷切換控制器則隨即接通所述功率開關。The valley switching controller described in claim 7 turns on the power switch when the on-state neutral signal is at a high level and the valley warning signal appears for the first time. However, if no valley warning signal occurs during the entire time when the on-state neutral signal is at a high level, the valley switching controller immediately turns on the power switch.

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