本發明是有關於一種晶片測試方法，且特別是有關於一種先切割晶圓再測試晶片的方法。The present invention relates to a wafer testing method, and more particularly to a method of first cutting a wafer and then testing the wafer.
目前半導體元件的測試方法包括以探針卡對晶圓上的多個晶片進行電性測試。接著，再將晶圓切割為多個彼此分離的晶片。具體而言，探針卡包括多個測試單元，且每個測試單元與晶圓上的一個晶片對應。各個測試單元包括多個探針，以在進行電性測試時接觸對應的晶片。Current testing methods for semiconductor components include electrically testing a plurality of wafers on a wafer with a probe card. Next, the wafer is diced into a plurality of wafers separated from each other. Specifically, the probe card includes a plurality of test cells, and each test cell corresponds to one wafer on the wafer. Each test unit includes a plurality of probes to contact a corresponding wafer when conducting an electrical test.
一般而言，探針卡的多個測試單元的佈局固定。以探針卡測試晶圓的外圍部分時，部分的測試單元會有無法接觸到晶片的情形。在此情形下，探針卡會重複地嘗試下針。因此，增加探針卡進行電性測試所需的時間，且降低探針卡的測試效率。In general, the layout of multiple test cells of the probe card is fixed. When the probe card is used to test the peripheral portion of the wafer, some of the test cells may not be able to touch the wafer. In this case, the probe card will repeatedly try to lower the needle. Therefore, the time required for the probe card to perform the electrical test is increased, and the test efficiency of the probe card is lowered.
本發明提供一種晶片測試方法，可縮短測試的時間。The invention provides a wafer testing method which can shorten the testing time.
本發明的晶片測試方法包括下列步驟。切割晶圓，以形成沿著第一方向與第二方向陣列排列且相互分離的多個晶片。提供一探針卡，其包括多個測試單元。在多個測試單元中，至少一個測試單元在第一方向以及第二方向上不與其餘的測試單元對齊。依據多個測試單元的排列將多個晶片重新排列或將多個晶片中的部分晶片排列成測試排列。測試排列包括多個彼此相鄰的排列單元，各個排列單元分別與探針卡的多個測試單元的佈局對應。藉由探針卡的多個測試單元逐一對各個排列單元中的多個晶片進行測試。The wafer testing method of the present invention comprises the following steps. The wafer is diced to form a plurality of wafers arranged in an array along the first direction and the second direction and separated from each other. A probe card is provided that includes a plurality of test units. Among the plurality of test units, at least one of the test units is not aligned with the remaining test units in the first direction and the second direction. A plurality of wafers are rearranged according to an arrangement of a plurality of test cells or a plurality of wafers of the plurality of wafers are arranged into a test arrangement. The test arrangement includes a plurality of arrangement units adjacent to each other, each of the alignment units respectively corresponding to a layout of a plurality of test units of the probe card. The test is performed by a plurality of test cells of the array card by a plurality of test cells of the probe card.
基於上述，本實施例的晶片測試方法依照探針卡的多個測試單元的排列以將多個晶片重新排列或將多個晶片中的部分晶片排列（局部重新排列）成測試排列。測試排列的各個排列單元分別與探針卡的多個測試單元的佈局對應。因此，在進行電性測試時，探針卡的多個測試單元每次可與一個排列單元中的所有晶片接觸。如此一來，可減少探針卡的測試單元因未接觸到晶片而重複地嘗試下針所消耗的時間，亦即可縮短電性測試的時間。此外，藉由依照探針卡的多個測試單元的排列以將多個晶片重新排列，本發明的晶片測試方法可適用於具有各種測試單元佈局的探針卡。Based on the above, the wafer testing method of the present embodiment follows the arrangement of a plurality of test cells of the probe card to rearrange a plurality of wafers or arrange (partially rearrange) a portion of the plurality of wafers into a test arrangement. Each of the array units of the test array respectively corresponds to the layout of the plurality of test units of the probe card. Therefore, during the electrical test, the plurality of test cells of the probe card can be in contact with all of the wafers in one of the aligned cells at a time. In this way, the time taken for the test unit of the probe card to repeatedly attempt to lower the needle without contacting the wafer can be reduced, and the time for the electrical test can be shortened. Furthermore, the wafer testing method of the present invention can be applied to probe cards having various test cell layouts by rearranging a plurality of wafers in accordance with the arrangement of a plurality of test cells of the probe card.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1A至圖1B是依照本發明的一實施例的晶片測試流程的上視示意圖。本實施例的晶片測試方法包括下列步驟。1A-1B are top schematic views of a wafer testing process in accordance with an embodiment of the present invention. The wafer test method of this embodiment includes the following steps.
請參照圖1A，切割晶圓，以形成多個晶片100。在一些實施例中，晶圓可為半導體晶圓。半導體晶圓的材料可包括矽、矽鍺、三五族半導體或其他半導體材料。此外，半導體晶圓亦可為絕緣層上覆矽（silicon on insulator，SOI）晶圓。此外，半導體晶圓還可包括形成於其上/其中的主動元件、被動元件、連線結構、保護層以及導電凸塊等構件。以簡潔起見，圖1A省略繪示上述的構件。在一些實施例中，可以刀具或雷射切割晶圓。此外，可透過黏著層（未繪示）將晶圓附著在載台102上以進行切割。然而，本發明並不以切割晶圓的方法為限。Referring to FIG. 1A, the wafer is diced to form a plurality of wafers 100. In some embodiments, the wafer can be a semiconductor wafer. The material of the semiconductor wafer may include germanium, germanium, a tri-five semiconductor or other semiconductor material. In addition, the semiconductor wafer may also be a silicon on insulator (SOI) wafer. In addition, the semiconductor wafer may further include active components, passive components, wiring structures, protective layers, and conductive bumps formed thereon/into the semiconductor wafer. For the sake of brevity, the above-described components are omitted from FIG. 1A. In some embodiments, the wafer can be cut by a tool or laser. In addition, the wafer can be attached to the stage 102 through an adhesive layer (not shown) for cutting. However, the present invention is not limited to the method of cutting the wafer.
切割晶圓所形成的多個晶片100沿著第一方向D1與第二方向D2陣列排列，且彼此互相分離。第一方向D1可與第二方向D2交錯。在一些實施例中，第一方向D1可與第二方向D2相互垂直。在第一方向D1上，相鄰的晶片100之間具有第一排列間距（pitch）P1。在第二方向D2上，相鄰的晶片100之間具有第二排列間距P2。第一排列間距P1可與第二排列間距P2相同或相異，本發明並不以此為限。The plurality of wafers 100 formed by dicing the wafer are arranged in an array along the first direction D1 and the second direction D2, and are separated from each other. The first direction D1 may be interleaved with the second direction D2. In some embodiments, the first direction D1 can be perpendicular to the second direction D2. In the first direction D1, adjacent wafers 100 have a first pitch P1 between them. In the second direction D2, the adjacent wafers 100 have a second arrangement pitch P2 therebetween. The first arrangement pitch P1 may be the same as or different from the second arrangement pitch P2, and the invention is not limited thereto.
請參照圖1B，提供探針卡104，以在後續的步驟中對多個晶片100進行電性測試。探針卡104包括多個測試單元。在本實施例中，多個測試單元包括3個測試單元106。在第一方向D1與第二方向D2上，3個測試單元106彼此不對齊。在第一方向D1上，相鄰的測試單元106之間的偏移量F1可與晶片100之間的第一排列間距P1（如圖1A所示）相同。在第二方向D2上，相鄰的測試單元之間的偏移量F2可與晶片100之間的第二排列間距P2（如圖1A所示）相同。在其他實施例中，多個測試單元的數量可多於或少於3個。此外，多個測試單元中的至少一者可在第一方向D1以及第二方向D2上不與其餘的測試單元對齊。Referring to FIG. 1B, a probe card 104 is provided to electrically test a plurality of wafers 100 in a subsequent step. The probe card 104 includes a plurality of test units. In this embodiment, the plurality of test units includes three test units 106. In the first direction D1 and the second direction D2, the three test units 106 are not aligned with each other. In the first direction D1, the offset F1 between adjacent test cells 106 may be the same as the first arrangement pitch P1 (shown in FIG. 1A) between the wafers 100. In the second direction D2, the offset F2 between adjacent test cells may be the same as the second arrangement pitch P2 (shown in FIG. 1A) between the wafers 100. In other embodiments, the number of multiple test units may be more or less than three. Further, at least one of the plurality of test units may not be aligned with the remaining test units in the first direction D1 and the second direction D2.
接著，依據探針卡104的多個測試單元106的排列將多個晶片100中的部分晶片排列（局部重新排列）成測試排列A1。在一些實施例中，可將多個晶片100從載台102轉移到載板108上，且局部重新排列多個晶片100以形成測試排列A1。舉例而言，可藉由機械手臂轉移並局部重新排列多個晶片100，且可預先將測試排列A1的圖案輸入至機械手臂的控制器。此外，在將多個晶片100局部重新排列於載板108上之前，可在載板108上形成黏著層（未繪示），以提高多個晶片100與載板108之間的附著力。Next, a portion of the plurality of wafers 100 are aligned (partially rearranged) into a test array A1 in accordance with the arrangement of the plurality of test cells 106 of the probe card 104. In some embodiments, a plurality of wafers 100 can be transferred from the stage 102 to the carrier 108 and the plurality of wafers 100 can be partially rearranged to form a test arrangement A1. For example, the plurality of wafers 100 can be transferred and partially rearranged by the robot arm, and the pattern of the test array A1 can be input to the controller of the robot arm in advance. In addition, an adhesive layer (not shown) may be formed on the carrier 108 before the plurality of wafers 100 are partially rearranged on the carrier 108 to improve the adhesion between the plurality of wafers 100 and the carrier 108.
測試排列A1包括多個彼此相鄰的排列單元U1。各個排列單元U1分別與探針卡104的多個測試單元106的佈局對應。在本實施例中，各個排列單元U1中晶片100的數量與探針卡104中測試單元106的數量相同。此外，各個排列單元U1中的多個晶片100對應於探針卡104中的多個測試單元106排列。The test array A1 includes a plurality of array units U1 adjacent to each other. Each of the array units U1 corresponds to the layout of the plurality of test units 106 of the probe card 104, respectively. In the present embodiment, the number of wafers 100 in each of the array units U1 is the same as the number of test units 106 in the probe card 104. Further, the plurality of wafers 100 in each of the array units U1 are arranged corresponding to the plurality of test units 106 in the probe card 104.
各個排列單元U1中相鄰的晶片100在第一方向D1上具有第三排列間距P3，且在第二方向D2上具有第四排列間距P4。在本實施例中，探針卡104中相鄰的測試單元106之間的偏移量F1與圖1A所示的第一排列間距P1相同，且偏移量F2與圖1A所示的第二排列間距P2相同。在此情況下，第三排列間距P3及第四排列間距P4分別與第一排列間距P1及第二排列間距P2相同。因此，在本實施例中僅需局部地將切割晶圓所形成的多個晶片100重新排列，即可形成測試排列A1。在其他實施例中，可將所有的晶片100重新排列成所需的測試排列A1，且第三排列間距P3及第四排列間距P4可與第一排列間距P1及第二排列間距P2相同。在另一實施例中，可將所有的晶片100重新排列成所需的測試排列A1，且第三排列間距P3及第四排列間距P4可與第一排列間距P1及第二排列間距P2不同。The adjacent wafers 100 in the respective array units U1 have a third arrangement pitch P3 in the first direction D1 and a fourth arrangement pitch P4 in the second direction D2. In this embodiment, the offset F1 between adjacent test cells 106 in the probe card 104 is the same as the first alignment pitch P1 shown in FIG. 1A, and the offset F2 is the second shown in FIG. 1A. The arrangement pitch P2 is the same. In this case, the third arrangement pitch P3 and the fourth arrangement pitch P4 are the same as the first arrangement pitch P1 and the second arrangement pitch P2, respectively. Therefore, in this embodiment, only a plurality of wafers 100 formed by dicing wafers need to be partially rearranged to form a test array A1. In other embodiments, all of the wafers 100 may be rearranged into a desired test arrangement A1, and the third arrangement pitch P3 and the fourth arrangement pitch P4 may be the same as the first arrangement pitch P1 and the second arrangement pitch P2. In another embodiment, all of the wafers 100 may be rearranged into a desired test arrangement A1, and the third arrangement pitch P3 and the fourth arrangement pitch P4 may be different from the first arrangement pitch P1 and the second arrangement pitch P2.
接著，以探針卡104逐一對測試排列A1的各個排列單元U1進行電性測試。在進行電性測試的過程中，探針卡104沿著第一方向D1及/或第二方向D2移動以逐一對各個排列單元U1中的多個晶片100進行測試。換言之，探針卡104多次接觸測試排列A1，且每次接觸測試排列A1中的一個排列單元U1。探針卡104可藉由各個測試單元106中的多個探針接觸測試排列A1中的多個晶片100。各個排列單元U1中的多個晶片100的排列間距分別與探針卡104的多個測試單元106的排列間距相同。因此，在進行電性測試的過程中，探針卡104的多個測試單元106每次分別與一個排列單元U1中的所有晶片100接觸。如此一來，可減少探針卡104的測試單元106未接觸到晶片而重複地嘗試下針所需的時間。換言之，可縮短探針卡104進行電性測試的時間。Next, each of the array units U1 of the array A1 is tested by the probe card 104 one by one to perform an electrical test. During the electrical test, the probe card 104 is moved along the first direction D1 and/or the second direction D2 to test a plurality of wafers 100 in each of the array units U1. In other words, the probe card 104 contacts the test array A1 a plurality of times, and each time contacts one of the array units U1 in the test array A1. The probe card 104 can contact the plurality of wafers 100 in the test array A1 by a plurality of probes in the respective test units 106. The arrangement pitch of the plurality of wafers 100 in each of the array units U1 is the same as the arrangement pitch of the plurality of test units 106 of the probe card 104, respectively. Therefore, during the electrical test, the plurality of test cells 106 of the probe card 104 are each in contact with all of the wafers 100 in one of the alignment units U1. In this way, the time required for the test unit 106 of the probe card 104 to repeatedly touch the wafer without repeatedly touching the wafer can be reduced. In other words, the time during which the probe card 104 is electrically tested can be shortened.
在一些實施例中，可在切割晶圓之後對多個晶片100進行切割後檢測（post-slicing inspection），以判斷多個晶片100是否具有切割造成的缺陷。接著，可依照上述的方法將判斷為不具有缺陷的晶片100轉移並局部重新排列，之後以探針卡104對此些晶片100進行電性測試。如此一來，可避免對具有切割造成的缺陷的晶片進行電性測試，故可進一步縮短電性測試的時間。此外，更可提高電性測試步驟的良率。In some embodiments, a plurality of wafers 100 may be post-sliced after the wafer is diced to determine whether the plurality of wafers 100 have defects due to dicing. Next, the wafers 100 judged to have no defects can be transferred and partially rearranged according to the above method, and then the wafers 100 are electrically tested by the probe card 104. In this way, the electrical test of the wafer with the defects caused by the cutting can be avoided, so that the time of the electrical test can be further shortened. In addition, the yield of the electrical test step can be improved.
圖2A至圖2B是依照本發明的一實施例的晶片測試流程的上視示意圖。本實施例的晶片測試方法與圖1A至圖1B所示的方法類似，以下僅針對差異處進行說明，而相同或相似處則不再贅述。2A-2B are top plan views of a wafer testing process in accordance with an embodiment of the present invention. The wafer testing method of the present embodiment is similar to the method shown in FIG. 1A to FIG. 1B, and the following description is only for differences, and the same or similar parts will not be described again.
請參照圖2A與圖2B，探針卡204包括4個測試單元，亦即測試單元206a、測試單元206b、測試單元206c以及測試單元206d。在第一方向D1上，測試單元206a與測試單元206b之間的偏移量F3可相異於第一排列間距P1。相似地，測試單元206c與測試單元206d之間的偏移量F3亦可相異於第一排列間距P1。在第二方向D2上，測試單元206a與測試單元206b之間的偏移量F4可相異於第二排列間距P2。相似地，測試單元206c與測試單元206d之間的偏移量F4亦可相異於第二排列間距P2。在本實施例中，至少一測試單元在第一方向D1上自其餘的測試單元的偏移量F3可為第一排列間距P1的非正整數倍。相似地，至少一測試單元在第二方向D2上自其餘的測試單元的偏移量F4可為第二排列間距P2的非正整數倍。舉例而言，偏移量F3可為第一排列間距P1的1.5倍。偏移量F4可為第二排列間距的1.5倍。在其他實施例中，至少一測試單元在第一方向D1及/或第二方向D2上自其餘的測試單元的偏移量可分別為第一排列間距P1的正整數倍或第二排列間距P2的正整數倍。Referring to FIG. 2A and FIG. 2B, the probe card 204 includes four test units, that is, a test unit 206a, a test unit 206b, a test unit 206c, and a test unit 206d. In the first direction D1, the offset F3 between the test unit 206a and the test unit 206b may be different from the first arrangement pitch P1. Similarly, the offset F3 between the test unit 206c and the test unit 206d may also be different from the first arrangement pitch P1. In the second direction D2, the offset F4 between the test unit 206a and the test unit 206b may be different from the second arrangement pitch P2. Similarly, the offset F4 between the test unit 206c and the test unit 206d may also be different from the second arrangement pitch P2. In this embodiment, the offset F3 of the at least one test unit from the remaining test units in the first direction D1 may be a non-positive integer multiple of the first arrangement pitch P1. Similarly, the offset F4 of the at least one test unit from the remaining test units in the second direction D2 may be a non-positive integer multiple of the second arrangement pitch P2. For example, the offset F3 may be 1.5 times the first arrangement pitch P1. The offset F4 can be 1.5 times the second arrangement pitch. In other embodiments, the offset of the at least one test unit from the remaining test units in the first direction D1 and/or the second direction D2 may be a positive integer multiple of the first arrangement pitch P1 or a second arrangement pitch P2, respectively. Positive integer multiples.
如此一來，在將切割晶圓所形成的多個晶片100重新排列的步驟中，是依照探針卡204的多個測試單元的排列將多個晶片100全面地重新排列成測試排列A2。多個晶片100經重新排列後，可改變在第一方向D1及/或第二方向D2上相鄰的晶片之間的排列間距。測試排列A2包括多個彼此相鄰的排列單元U2。各個排列單元U2中相鄰的晶片100在第一方向D1上具有第五排列間距P5，且在第二方向D2上具有第六排列間距P6。在第一方向D1上，排列單元U2的第五排列間距P5與偏移量F3相同，但可相異於第一排列間距P1。此外，在第二方向D2上，第六排列間距P6可與偏移量F4相同，但可相異於第二排列間距P2。因此，本實施例的晶片測試方法更可適用於具有各種測試單元之間的偏移量的探針卡。In this way, in the step of rearranging the plurality of wafers 100 formed by cutting the wafer, the plurality of wafers 100 are completely rearranged into the test array A2 in accordance with the arrangement of the plurality of test cells of the probe card 204. After the plurality of wafers 100 are rearranged, the arrangement pitch between adjacent wafers in the first direction D1 and/or the second direction D2 can be changed. The test array A2 includes a plurality of array units U2 adjacent to each other. The adjacent wafers 100 in the respective array units U2 have a fifth arrangement pitch P5 in the first direction D1 and a sixth arrangement pitch P6 in the second direction D2. In the first direction D1, the fifth arrangement pitch P5 of the array unit U2 is the same as the offset amount F3, but may be different from the first arrangement pitch P1. Further, in the second direction D2, the sixth arrangement pitch P6 may be the same as the offset amount F4, but may be different from the second arrangement pitch P2. Therefore, the wafer test method of the present embodiment is more applicable to a probe card having an offset between various test units.
綜上所述，本實施例的晶片測試方法依照探針卡的多個測試單元的排列以將多個晶片重新排列或局部重新排列成測試排列。測試排列的各個排列單元分別與探針卡的多個測試單元的佈局對應。因此，在以探針卡進行電性測試的過程中，探針卡的多個測試單元每次可與一個排列單元中的所有晶片接觸。如此一來，可減少探針卡的測試單元因未接觸到晶片而重複地嘗試下針所需的時間。換言之，可縮短電性測試的時間。此外，藉由依照探針卡的多個測試單元的排列以將多個晶片重新排列或局部重新排列，本發明的晶片測試方法可適用於具有各種測試單元佈局的探針卡。In summary, the wafer testing method of the present embodiment follows the arrangement of a plurality of test cells of the probe card to rearrange or partially rearrange the plurality of wafers into a test arrangement. Each of the array units of the test array respectively corresponds to the layout of the plurality of test units of the probe card. Therefore, during the electrical test with the probe card, the plurality of test cells of the probe card can be in contact with all of the wafers in one of the aligned cells at a time. In this way, the time required for the test unit of the probe card to repeatedly attempt to lower the needle due to not touching the wafer can be reduced. In other words, the time for electrical testing can be shortened. Furthermore, the wafer testing method of the present invention can be applied to probe cards having various test cell layouts by rearranging or partially rearranging a plurality of wafers in accordance with the arrangement of a plurality of test cells of the probe card.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧晶片100‧‧‧ wafer
102‧‧‧載台102‧‧‧ stage
104、204‧‧‧探針卡104, 204‧‧ ‧ probe card
106、206a～206d‧‧‧測試單元106, 206a ~ 206d‧‧‧ test unit
108‧‧‧載板108‧‧‧ Carrier Board
A1、A2‧‧‧測試排列A1, A2‧‧‧ test arrangement
D1‧‧‧第一方向D1‧‧‧ first direction
D2‧‧‧第二方向D2‧‧‧ second direction
F1~F4‧‧‧偏移量F1~F4‧‧‧ offset
P1‧‧‧第一排列間距P1‧‧‧first arrangement spacing
P2‧‧‧第二排列間距P2‧‧‧Second arrangement spacing
P3‧‧‧第三排列間距P3‧‧‧ third arrangement spacing
P4‧‧‧第四排列間距P4‧‧‧ fourth arrangement spacing
P5‧‧‧第五排列間距P5‧‧‧ fifth arrangement spacing
P6‧‧‧第六排列間距P6‧‧‧ sixth arrangement spacing
U1、U2‧‧‧排列單元U1, U2‧‧‧ Arrangement unit
圖1A至圖1B是依照本發明的一實施例的晶片測試流程的上視示意圖。 圖2A至圖2B是依照本發明的一實施例的晶片測試流程的上視示意圖。1A-1B are top schematic views of a wafer testing process in accordance with an embodiment of the present invention. 2A-2B are top plan views of a wafer testing process in accordance with an embodiment of the present invention.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106111356ATWI616658B (en) | 2017-04-05 | 2017-04-05 | Chip testing method |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106111356ATWI616658B (en) | 2017-04-05 | 2017-04-05 | Chip testing method |
| Publication Number | Publication Date |
|---|---|
| TWI616658B TWI616658B (en) | 2018-03-01 |
| TW201837478Atrue TW201837478A (en) | 2018-10-16 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106111356ATWI616658B (en) | 2017-04-05 | 2017-04-05 | Chip testing method |
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| TW (1) | TWI616658B (en) |
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