本發明係有關於半導體封裝技術領域，特別是有關於一種晶圓級封裝(wafer level package, WLP)，具有應力緩和結構特徵(stress-relief features)，設於成型模料(molding compound)的上部。The present invention relates to the field of semiconductor packaging technology, and more particularly to a wafer level package (WLP) having stress-relief features disposed on the upper portion of a molding compound. .
晶圓級封裝製程是該領域技術人員已熟知的技術。在晶圓級封裝製程中，包含積體電路形成其中或晶片安裝其上的晶圓會經過一連串製程，例如研磨、晶粒對準接合，以及封模成型等步驟，最後再經過切割得到最終產品。現今業界普遍認為晶圓級封裝製程是最適合應用在小尺寸與高速晶片封裝的技術。Wafer level packaging processes are well known to those skilled in the art. In a wafer-level packaging process, the wafer containing the integrated circuit formed therein or the wafer mounted thereon is subjected to a series of processes such as grinding, die-alignment bonding, and die-molding, and finally, the final product is cut. . Today's industry is widely recognized as a wafer-level packaging process that is best suited for small-scale and high-speed chip packaging.
通常，進行晶圓級封裝時，會使用一相對厚的成型模料(molding compound)覆蓋住晶圓與安裝在晶圓上的晶粒。由於成型模料的熱膨脹係數(CTE)與晶圓的不同，由一定厚度的成型模料所構成的封裝體受到熱變化時容易翹曲。不僅如此，成型模料的存在也使封裝體的整體厚度增加。晶圓翹曲的問題一直是該領域技術人員企圖解決的問題。Typically, when wafer level packaging is performed, a relatively thick molding compound is used to cover the wafer and the die mounted on the wafer. Since the coefficient of thermal expansion (CTE) of the molding material differs from that of the wafer, the package formed of a molding material having a certain thickness is easily warped when subjected to heat change. Moreover, the presence of the molding die also increases the overall thickness of the package. The problem of wafer warpage has been an attempt by technicians in the field.
晶圓翹曲造成不易維持晶粒與晶圓間的連接，致使晶粒與晶圓疊層組裝失敗。翹曲問題在大尺寸晶圓上更是明顯，使大尺吋晶圓的晶圓級封裝更加困難。因此，業界仍需要一個改良的晶圓級封裝方法，可以解決上述先前技術的問題。Wafer warpage makes it difficult to maintain the connection between the die and the wafer, resulting in failure of the die-to-wafer stack assembly. The warpage problem is even more pronounced on large-size wafers, making wafer-level packaging of large-size wafers more difficult. Therefore, the industry still needs an improved wafer level packaging method that can solve the above prior art problems.
本發明的主要目的在於提供一改良的半導體元件，可以減輕或消除晶圓或封裝體翹曲的問題，使製得的半導體封裝體具有更好的可靠度。SUMMARY OF THE INVENTION A primary object of the present invention is to provide an improved semiconductor device that can alleviate or eliminate the problem of wafer or package warpage and provide better reliability of the resulting semiconductor package.
本發明一實施例提供一種半導體元件，包含有一晶片，其具有一主動面以及一背面，相對於該主動面；一成型模料，封蓋住該晶片的該主動面以外的部分；一重佈線層，設於該主動面上以及該成型模料上，其中該重佈線層係電連接該晶片；以及一應力緩和結構特徵，埋設於該成型模料中。An embodiment of the present invention provides a semiconductor device including a wafer having an active surface and a back surface opposite to the active surface; a molding die covering a portion of the wafer other than the active surface; and a redistribution layer And disposed on the active surface and the molding die, wherein the redistribution layer is electrically connected to the wafer; and a stress relieving structural feature is embedded in the molding die.
根據本發明一實施例，所述半導體元件另包含一穿矽通孔(TSV)中介層，連接該重佈線層。該TSV中介層的一底面上設有複數個焊球，為後續連接用，例如，連結至一主機板或印刷電路板。According to an embodiment of the invention, the semiconductor device further includes a through via (TSV) interposer connected to the redistribution layer. A plurality of solder balls are disposed on a bottom surface of the TSV interposer for subsequent connection, for example, to a motherboard or a printed circuit board.
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。It will be apparent to those skilled in the art that the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;
接下來的詳細敘述須參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。The detailed description that follows is to be understood by reference to the accompanying drawings,
這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，可做結構、邏輯和電性上的修改應用在其他實施例上。These embodiments provide sufficient detail to enable those skilled in the art to fully understand and practice the invention. Structural, logical, and electrical modifications may be applied to other embodiments without departing from the scope of the invention.
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者，也應屬本發明涵蓋的範圍。Therefore, the following detailed description is not to be construed as limiting. The scope of the invention is defined by the claims. It is also within the scope of the present invention to have the same meaning as the claims of the present invention.
本發明實施例所參照的附圖為示意圖，並未按比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。The drawings referred to in the embodiments of the present invention are schematic and not drawn to scale, and the same or similar features are generally described with the same reference numerals.
在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交替使用。In the present specification, "die", "semiconductor wafer" and "semiconductor die" have the same meaning and may be used interchangeably.
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可在其上沉積材料並製作例如本發明實施例的重佈線層(RDL)電路結構的任何結構物。In the present specification, "wafer" and "substrate" mean any structure including an exposed face on which a material can be deposited and a rewiring layer (RDL) circuit structure such as the embodiment of the present invention is fabricated.
須了解的是，“基板”包含半導體晶圓，但不限於此。製程中，“基板”也用來表示包含製作於其上的材料層的半導體結構物。It should be understood that the "substrate" includes a semiconductor wafer, but is not limited thereto. In the process, "substrate" is also used to mean a semiconductor structure comprising a layer of material fabricated thereon.
在本說明書中，“穿矽通孔(TSV)”一詞被廣義定義為包括任何晶片或積體電路裸晶上所具有的孔洞或穿孔，其內填充有導電填料材料（例如，銅或鎢等金屬）。TSV通孔提供從晶片或積體電路裸晶的底面延伸到晶圓頂側上或晶片表面上的接觸層或任何金屬互連層的電連結。In this specification, the term "through-via via (TSV)" is broadly defined to include holes or perforations in the die of any wafer or integrated circuit that are filled with a conductive filler material (eg, copper or tungsten). Waiting for metal). The TSV vias provide electrical connections from the bottom surface of the wafer or integrated circuit die to the contact layer or any metal interconnect layer on the top side of the wafer or on the surface of the wafer.
請參照第1圖至第8圖。第1圖至第8圖為示意性剖面圖，說明根據本發明一實施例，製作一具有穿矽通孔(through substrate via, TSV)的晶圓級封裝體的方法。Please refer to Figures 1 to 8. 1 through 8 are schematic cross-sectional views illustrating a method of fabricating a wafer level package having a through substrate via (TSV) in accordance with an embodiment of the present invention.
如第1圖所示，首先提供一晶圓100。晶圓100包含矽晶圓、半導體晶圓或中介層晶圓，但不限於此。例如，晶圓100可為一矽中介層晶圓。晶圓100具有一正面100a與一背面100b，相對於正面100a。在晶圓100的正面100a上，形成有複數個穿矽通孔102。As shown in FIG. 1, a wafer 100 is first provided. The wafer 100 includes a germanium wafer, a semiconductor wafer, or an interposer wafer, but is not limited thereto. For example, wafer 100 can be an interposer wafer. The wafer 100 has a front side 100a and a back side 100b opposite to the front side 100a. On the front surface 100a of the wafer 100, a plurality of through-holes 102 are formed.
製作穿矽通孔102的方法已為該技術領域中通常知識者所熟悉。舉例來說，製作穿矽通孔102的方法包含首先在晶圓100的正面100a製作距離晶圓100主表面一預定深度的TSV孔洞，然後在TSV孔洞內沉積金屬層，例如擴散阻障金屬層與銅層，但不限於此。接著對晶圓100的正面100a進行一研磨製程，移除TSV孔洞外多餘的金屬層。Methods of making through-holes 102 are well known to those of ordinary skill in the art. For example, the method of fabricating the through vias 102 includes first forming a TSV hole at a predetermined depth from the front surface 100a of the wafer 100 at a predetermined depth, and then depositing a metal layer, such as a diffusion barrier metal layer, in the TSV holes. With copper layer, but not limited to this. A polishing process is then performed on the front side 100a of the wafer 100 to remove excess metal layers outside the TSV holes.
接著，如第2圖所示，在晶圓100的正面100a上形成一重佈線層(RDL)110。重佈線層110 可以包含至少一介電層112與至少一金屬層114。穿矽通孔102可以與金屬層114電性連接。重佈線層110可以包含一增層內連線(build-up interconnect)結構。Next, as shown in FIG. 2, a redistribution layer (RDL) 110 is formed on the front surface 100a of the wafer 100. The redistribution layer 110 may include at least one dielectric layer 112 and at least one metal layer 114. The through via 102 can be electrically connected to the metal layer 114. The redistribution layer 110 may include a build-up interconnect structure.
接著，在重佈線層110上形成複數個凸塊116，例如，微凸塊(micro-bumps)，為後續連接用。凸塊116可分別直接形成在金屬層114的接觸墊上。Next, a plurality of bumps 116, such as micro-bumps, are formed on the redistribution layer 110 for subsequent connections. The bumps 116 may be formed directly on the contact pads of the metal layer 114, respectively.
如第3圖所示，形成凸塊116後，接著將個別覆晶晶片或晶粒120主動面朝下，藉由凸塊116安裝至重佈線層110上，得到一晶片對晶圓疊合的構造。在各晶片或晶粒120的主動面上設有複數個輸出/輸入(I/O)接墊121，安裝時，使凸塊116對準輸出/輸入接墊121。As shown in FIG. 3, after the bumps 116 are formed, the individual flip chip or die 120 is then actively face down, and the bumps 116 are mounted on the redistribution layer 110 to obtain a wafer-to-wafer stack. structure. A plurality of output/input (I/O) pads 121 are disposed on the active faces of the respective wafers or die 120. When mounted, the bumps 116 are aligned with the output/input pads 121.
接下來，可選擇性地在每一晶片或晶粒120與晶圓100的正面100a之間填充一底膠118。然後，進行一熱處理，使凸塊116回焊。Next, a primer 118 can be selectively filled between each wafer or die 120 and the front side 100a of the wafer 100. Then, a heat treatment is performed to re-weld the bumps 116.
如第4圖所示，完成晶粒接合後，接著在晶圓100的正面100a上覆蓋一成型模料200。成型模料200封蓋住已貼合好的晶片或晶粒120，並且覆蓋重佈線層110的上表面。接著，成型模料200可以進行一固化製程。As shown in FIG. 4, after the die bonding is completed, a molding die 200 is then overlaid on the front surface 100a of the wafer 100. The molding die 200 covers the bonded wafer or die 120 and covers the upper surface of the redistribution layer 110. Next, the molding die 200 can be subjected to a curing process.
根據例示的實施例，成型模料200可使用例如轉印模具及熱固成型化合物來形成。可以使用其他手段來分配成型模料。也可使用在升高的溫度或環境溫度下為液體的環氧樹脂、樹脂和化合物。成型模料200是電絕緣體，並且可以是熱導體。不同填料可以被添加以增強成型模料200的熱傳導，剛度或黏附性能。According to the illustrated embodiment, the molding die 200 can be formed using, for example, a transfer mold and a thermosetting compound. Other means can be used to dispense the molding compound. Epoxy resins, resins and compounds that are liquid at elevated temperatures or ambient temperatures can also be used. Molding molding 200 is an electrical insulator and may be a thermal conductor. Different fillers may be added to enhance the heat transfer, stiffness or adhesion properties of the molding die 200.
如第5圖所示，形成成型模料200之後，在成型模料200的上部繼續形成複數個溝槽202。溝槽202可以利用切割、線鋸、雷射或蝕刻等方式形成，但不限於此。根據例示的實施例，溝槽202可以直接位於晶片或晶粒120的正上方。As shown in FIG. 5, after the molding die 200 is formed, a plurality of grooves 202 are continuously formed in the upper portion of the molding die 200. The trench 202 may be formed by cutting, wire saw, laser, or etching, but is not limited thereto. According to the illustrated embodiment, the trench 202 can be directly over the wafer or die 120.
第9A至9C圖是示意性上視圖，圖示成型模料200上的溝槽202的一些例示性佈局。如第9A圖所示，溝槽202可以被佈置成柵格圖案。如第9B圖所示，溝槽202可以被佈置成分離的孔洞圖案。如第9C圖所示，溝槽202可以被佈置成同心圓圖案。但是應該理解的是，根據設計要求，也可採用其它圖案。9A through 9C are schematic top views showing some exemplary layouts of the trenches 202 on the molding die 200. As shown in FIG. 9A, the trenches 202 may be arranged in a grid pattern. As shown in FIG. 9B, the trenches 202 can be arranged in separate hole patterns. As shown in FIG. 9C, the trenches 202 may be arranged in a concentric circular pattern. However, it should be understood that other patterns may be employed depending on design requirements.
如第6圖所示，隨後，應力緩和結構特徵204被形成在成型模料200的各溝槽202中。根據所示的實施例中，應力緩和結構特徵204可以完全填滿溝槽202。應力緩和結構特徵204可包括具有相對低楊氏係數(Young's Modulus)的彈性材料。例如，上述彈性材料可包括有機材料，例如光阻劑、聚醯亞胺(polyimide)或苯並環丁烯(benzocyclobutene)。As shown in FIG. 6, subsequently, stress relieving structural features 204 are formed in each of the trenches 202 of the molding die. In accordance with the illustrated embodiment, the stress relief structure feature 204 can completely fill the trench 202. The stress relief structural feature 204 can include an elastomeric material having a relatively low Young's Modulus. For example, the above elastic material may include an organic material such as a photoresist, a polyimide or a benzocyclobutene.
如第7圖所示，形成成型模料200和應力緩和結構特徵204後，繼續對晶圓100進行一晶背研磨製程，以從背面100b研磨掉部分厚度的晶圓100，從而形成TSV中介層101。例如，晶圓100可以首先被裝載到晶片研磨機(圖未示)。然後，使拋光墊與晶圓100的背面100b接觸，並開始研磨背面100b。上述研磨處理降低了晶圓100的厚度，從而露出所述的穿矽通孔102的下端。As shown in FIG. 7, after forming the molding die 200 and the stress relaxation structure feature 204, the wafer 100 is subjected to a crystal back grinding process to polish a portion of the wafer 100 from the back surface 100b to form a TSV interposer. 101. For example, wafer 100 can be loaded first into a wafer grinder (not shown). Then, the polishing pad is brought into contact with the back surface 100b of the wafer 100, and the back surface 100b is started to be polished. The above-described polishing process reduces the thickness of the wafer 100 to expose the lower end of the through-hole 102.
如第8圖所示，可以繼續在晶圓100的背面100b進行金屬化製程，以在絕緣層212內形成複數個凸塊接墊210。之後，可以在各個凸塊接墊210上形成焊錫凸塊或焊球220。然後，晶圓100可以被切割成彼此分離的各個晶圓級封裝10。As shown in FIG. 8, the metallization process can continue on the back side 100b of the wafer 100 to form a plurality of bump pads 210 in the insulating layer 212. Solder bumps or solder balls 220 may then be formed on each of the bump pads 210. The wafer 100 can then be diced into individual wafer level packages 10 that are separated from one another.
根據例示的實施例，嵌入在成型模料200的上部的應力緩和結構特徵204可以改善或避免晶圓100在晶圓層級或在晶片層級的翹曲情形。According to the illustrated embodiment, the stress relief structure feature 204 embedded in the upper portion of the molding die 200 can improve or avoid warpage of the wafer 100 at the wafer level or at the wafer level.
請參照第10圖至第17圖。第10圖至第17圖為示意性剖面圖，說明根據本發明另一實施例，製作一晶圓級封裝體的方法。Please refer to Figures 10 to 17. 10 through 17 are schematic cross-sectional views illustrating a method of fabricating a wafer level package in accordance with another embodiment of the present invention.
如第10圖所示，提供一載體300，其可以是一可撕除的基板材料，且其上可具有一黏著層302。在載體300上可形成有至少一介電層310。As shown in FIG. 10, a carrier 300 is provided which may be a tearable substrate material and may have an adhesive layer 302 thereon. At least one dielectric layer 310 may be formed on the carrier 300.
如第11圖所示，接著，在介電層310上形成一重佈線層(RDL)410。重佈線層410 可以包含至少一介電層412與至少一金屬層414。接著，在重佈線層410上形成複數個凸塊416，例如，微凸塊(micro-bumps)，為後續連接用。凸塊416可分別直接形成在金屬層414的接觸墊上。As shown in FIG. 11, next, a redistribution layer (RDL) 410 is formed on the dielectric layer 310. The redistribution layer 410 can include at least one dielectric layer 412 and at least one metal layer 414. Next, a plurality of bumps 416, such as micro-bumps, are formed on the redistribution layer 410 for subsequent connections. Bumps 416 can be formed directly on the contact pads of metal layer 414, respectively.
如第12圖所示，形成凸塊416後，接著將個別覆晶晶片或晶粒420主動面朝下，藉由凸塊416安裝至重佈線層410上，得到一晶片對晶圓疊合的構造。在各晶片或晶粒420的主動面上設有複數個輸出/輸入(I/O)接墊421，安裝時，使凸塊416對準輸出/輸入接墊421。接下來，可選擇性地在每一晶片或晶粒420下方填充一底膠418。然後，進行一熱處理，使凸塊416回焊。As shown in FIG. 12, after the bumps 416 are formed, the individual flip chip or die 420 is then actively face down, and the bumps 416 are mounted on the redistribution layer 410 to obtain a wafer-to-wafer overlap. structure. A plurality of output/input (I/O) pads 421 are provided on the active faces of the respective wafers or dies 420, and the bumps 416 are aligned with the output/input pads 421 during mounting. Next, a primer 418 can be optionally filled under each wafer or die 420. Then, a heat treatment is performed to re-weld the bumps 416.
如第13圖所示，完成晶粒接合後，接著覆蓋一成型模料500。成型模料500封蓋住已貼合好的晶片或晶粒420，並且覆蓋重佈線層410的上表面。接著，成型模料500可以進行一固化製程。As shown in Fig. 13, after the die bonding is completed, a molding die 500 is next covered. The molding die 500 covers the bonded wafer or die 420 and covers the upper surface of the redistribution layer 410. Next, the molding die 500 can be subjected to a curing process.
如第14圖所示，形成成型模料500之後，在成型模料500的上部繼續形成複數個溝槽502。溝槽502可以利用切割、線鋸、雷射或蝕刻等方式形成，但不限於此。根據例示的實施例，溝槽502可以直接位於晶片或晶粒420的正上方。As shown in Fig. 14, after the molding die 500 is formed, a plurality of grooves 502 are continuously formed in the upper portion of the molding die 500. The trench 502 may be formed by cutting, wire saw, laser, or etching, but is not limited thereto. According to the illustrated embodiment, the trench 502 can be directly over the wafer or die 420.
如第15圖所示，隨後，應力緩和結構特徵504被形成在成型模料500的各溝槽502中。根據所示的實施例中，應力緩和結構特徵504可以完全填滿溝槽502。應力緩和結構特徵504可包括具有相對低楊氏係數的彈性材料。例如，上述彈性材料可包括有機材料，例如光阻劑，聚醯亞胺或苯並環丁烯。As shown in FIG. 15, subsequently, stress relieving structural features 504 are formed in each of the grooves 502 of the molding die 500. In accordance with the illustrated embodiment, the stress relief structural feature 504 can completely fill the trench 502. The stress relief structural feature 504 can include an elastomeric material having a relatively low Young's modulus. For example, the above elastic material may include an organic material such as a photoresist, polyimide or benzocyclobutene.
如第16圖所示，形成成型模料500和應力緩和結構特徵504後，將載體300及黏著層302去除或撕除，以顯露出介電層310。As shown in FIG. 16, after the molding die 500 and the stress relaxation structure feature 504 are formed, the carrier 300 and the adhesive layer 302 are removed or removed to reveal the dielectric layer 310.
如第17圖所示，可以繼續在介電層310上進行金屬化製程，以在絕緣層512內形成複數個凸塊接墊510。之後，可以在各個凸塊接墊510上形成焊錫凸塊或焊球520。然後，可以被切割製程，形成彼此分離的各個晶圓級封裝10。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。As shown in FIG. 17, the metallization process can continue on the dielectric layer 310 to form a plurality of bump pads 510 in the insulating layer 512. Solder bumps or solder balls 520 may then be formed on each bump pad 510. The process can then be diced to form individual wafer level packages 10 that are separated from one another. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
10‧‧‧晶圓級封裝
100‧‧‧晶圓
100a‧‧‧正面
100b‧‧‧背面
101‧‧‧TSV中介層
102‧‧‧穿矽通孔
110、410‧‧‧重佈線層
112、412‧‧‧介電層
114、414‧‧‧金屬層
116、416‧‧‧凸塊
118、418‧‧‧底膠
120、420‧‧‧晶片或晶粒
121、421‧‧‧輸出/輸入(I/O)接墊
200、500‧‧‧成型模料
202、502‧‧‧溝槽
204、504‧‧‧應力緩和結構特徵
210、510‧‧‧凸塊接墊
212、512‧‧‧絕緣層
220、520‧‧‧焊球
300‧‧‧載體
302‧‧‧黏著層
310‧‧‧介電層10‧‧‧ Wafer level packaging
100‧‧‧ wafer
100a‧‧‧ positive
100b‧‧‧back
101‧‧‧TSV Intermediary
102‧‧‧through through hole
110, 410‧‧‧Rewiring layer
112, 412‧‧‧ dielectric layer
114, 414‧‧‧ metal layer
116, 416‧‧ ‧ bumps
118, 418‧‧ ‧ primer
120, 420‧‧‧ wafers or grains
121, 421‧‧‧Output/Input (I/O) pads
200, 500‧‧‧ molding materials
202, 502‧‧‧ trench
204, 504‧‧‧ stress mitigation structural features
210, 510‧‧‧ bump pads
212, 512‧‧‧ insulation
220, 520‧‧‧ solder balls
300‧‧‧ Carrier
302‧‧‧Adhesive layer
310‧‧‧Dielectric layer
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。 第1圖至第8圖為示意性剖面圖，說明根據本發明一實施例，製作一具有穿矽通孔的晶圓級封裝體的方法。 第9A至9C圖是示意性上視圖，圖示成型模料上的溝槽的例示性佈局。 第10圖至第17圖為示意性剖面圖，說明根據本發明另一實施例，製作一晶圓級封裝體的方法。The drawings provide a more in-depth understanding of this embodiment and are incorporated in this specification. These drawings and description are used to illustrate the principles of some embodiments. 1 through 8 are schematic cross-sectional views illustrating a method of fabricating a wafer level package having through vias in accordance with an embodiment of the present invention. Figures 9A through 9C are schematic top views showing an exemplary layout of the grooves on the molding die. 10 through 17 are schematic cross-sectional views illustrating a method of fabricating a wafer level package in accordance with another embodiment of the present invention.
10‧‧‧晶圓級封裝10‧‧‧ Wafer level packaging
100a‧‧‧正面100a‧‧‧ positive
100b‧‧‧背面100b‧‧‧back
101‧‧‧TSV中介層101‧‧‧TSV Intermediary
102‧‧‧穿矽通孔102‧‧‧through through hole
110‧‧‧重佈線層110‧‧‧Rewiring layer
112‧‧‧介電層112‧‧‧ dielectric layer
114‧‧‧金屬層114‧‧‧metal layer
116‧‧‧凸塊116‧‧‧Bumps
118‧‧‧底膠118‧‧‧Bottom glue
120‧‧‧晶片或晶粒120‧‧‧ wafer or die
121‧‧‧輸出/輸入(I/O)接墊121‧‧‧Output/Input (I/O) pads
200‧‧‧成型模料200‧‧‧ molding compound
202‧‧‧溝槽202‧‧‧ trench
204‧‧‧應力緩和結構特徵204‧‧‧stress mitigation structural features
210‧‧‧凸塊接墊210‧‧‧Bump pads
212‧‧‧絕緣層212‧‧‧Insulation
220‧‧‧焊球220‧‧‧ solder balls
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201514749619A | 2015-06-24 | 2015-06-24 |
| Publication Number | Publication Date |
|---|---|
| TW201701429Atrue TW201701429A (en) | 2017-01-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104125047ATW201701429A (en) | 2015-06-24 | 2015-08-03 | Wafer level package and fabrication method thereof |
| Country | Link |
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| CN (1) | CN106298683B (en) |
| TW (1) | TW201701429A (en) |
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