本發明是有關於一種發光元件及其製造方法，且特別是有關於一種增加發光面積的發光元件及其製造方法。The present invention relates to a light-emitting element and a method of fabricating the same, and, in particular, to a light-emitting element that increases a light-emitting area and a method of fabricating the same.
在發光元件(例如是高壓發光二極體)中，通常需要將連結兩個發光單元的橋接電路形成於斜面結構上，以改善金屬於蒸鍍製程期間之附著力，防止金屬斷線或在掀離(lift-off)光阻時造成金屬脫落(peeling)。傳統的發光元件中，斜面結構之製造方式一般為在半導體上以黃光微影製程製作光阻圖案，再使用感應式耦合電漿法(Inductively Coupled Plasma, ICP)及反應性離子蝕刻法(Reactive-Ion Etching, RIE)，以蝕刻半導體及光阻。然而，在利用光阻進行蝕刻的過程中，容易移除過多的半導體材料及發光材料，導致發光面積縮小，增加生產成本。此外，傳統的發光元件容易因為橋接電路與絕緣層之間的附著能力不佳的問題，使得橋接電路於製程中容易產生孔洞甚至是缺陷，進而影響電性之傳導。In a light-emitting element (for example, a high-voltage light-emitting diode), it is generally required to form a bridge circuit connecting two light-emitting units on a bevel structure to improve the adhesion of the metal during the evaporation process and prevent metal breakage or smashing. Metal peeling occurs when the photoresist is lifted off. In the conventional light-emitting element, the bevel structure is generally manufactured by forming a photoresist pattern on a semiconductor by a yellow lithography process, and then using Inductively Coupled Plasma (ICP) and reactive ion etching (Reactive-Ion). Etching, RIE) to etch semiconductors and photoresists. However, in the process of etching using photoresist, it is easy to remove too much semiconductor material and luminescent material, resulting in a reduction in light-emitting area and an increase in production cost. In addition, the conventional light-emitting element is prone to the problem of poor adhesion between the bridge circuit and the insulating layer, so that the bridge circuit is prone to holes or even defects in the process, thereby affecting the electrical conduction.
因此，目前仍需要提出一增加發光面積及可增加導電層之附著能力的解決方法。Therefore, there is still a need to propose a solution for increasing the light-emitting area and increasing the adhesion of the conductive layer.
本發明提出一種增加發光面積的發光元件及其製造方法，以保留較多的有效發光面積，增加發光強度並改善晶片效率。The present invention proposes a light-emitting element that increases the light-emitting area and a method of manufacturing the same, which retains more effective light-emitting area, increases light-emitting intensity, and improves wafer efficiency.
根據本發明之一方面，提供一種發光元件，包括一基板及一第一發光單元。第一發光單元配置於基板上，且包括一第一半導體層、一第一發光層、及一第二半導體層。第一半導體層配置於基板之上。第一發光層配置於第一半導體層與第二半導體層之間。其中，第一半導體層具有一第一側壁與一第二側壁，第一側壁與基板之間具有一第一夾角，第二側壁與基板之間具有一第二夾角，第一夾角小於該第二夾角。According to an aspect of the invention, a light emitting device includes a substrate and a first light emitting unit. The first light emitting unit is disposed on the substrate and includes a first semiconductor layer, a first light emitting layer, and a second semiconductor layer. The first semiconductor layer is disposed on the substrate. The first light emitting layer is disposed between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer has a first sidewall and a second sidewall. The first sidewall has a first angle between the substrate and the substrate. The second sidewall has a second angle between the second sidewall and the substrate. The first angle is smaller than the second angle. Angle.
根據本發明之一方面，提供一種發光元件，包括一基板及一第一發光單元。第一發光單元配置於基板上，且包括一第一半導體層、一第一發光層、及一第二半導體層。第一半導體層配置於基板之上。第一發光層配置於第一半導體層與第二半導體層之間。其中，第一半導體層具有一第一側壁及一第二側壁，其中第一側壁投影於基板的一第一長度大於第二側壁投影於基板的一第二長度。According to an aspect of the invention, a light emitting device includes a substrate and a first light emitting unit. The first light emitting unit is disposed on the substrate and includes a first semiconductor layer, a first light emitting layer, and a second semiconductor layer. The first semiconductor layer is disposed on the substrate. The first light emitting layer is disposed between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer has a first sidewall and a second sidewall. The first sidewall is projected onto the substrate by a first length greater than the second sidewall projected to the second length of the substrate.
根據本發明之一方面，提供一種發光元件之製造方法。方法包括：依序形成一第一型半導體層、一發光層與一第二型半導體層於一基板上；形成一第一圖案化光阻層於第二型半導體層上；以第一圖案化光阻層為遮罩，蝕刻第二型半導體層、該發光層以及部分第一型半導體層，以形成一開口，開口所暴露的第一型半導體層具有一第一寬度；移除第一圖案化光阻層後，形成一犧牲層覆蓋第一型半導體層與第二型半導體層；形成一第二圖案化光阻層覆蓋犧牲層；藉由第二圖案化光阻層圖案化犧牲層，其中，犧牲層於該開口內所露出的第一型半導體層具有一第二寬度，第二寬度小於第一寬度；形成一第三圖案化光阻層覆蓋犧牲層及部分第一型半導體層，其中第三圖案化光阻層於開口內所露出的第一型半導體層具有一第三寬度，第三寬度小於第二寬度；以第三圖案化光阻層及犧牲層為遮罩，蝕刻第一型半導體層；移除犧牲層及第三圖案化光阻層；於開口內形成一絕緣層覆蓋部分第一型半導體層；以及於開口內形成一導電層覆蓋絕緣層。According to an aspect of the invention, a method of manufacturing a light-emitting element is provided. The method includes: sequentially forming a first type semiconductor layer, a light emitting layer and a second type semiconductor layer on a substrate; forming a first patterned photoresist layer on the second type semiconductor layer; The photoresist layer is a mask, etching the second type semiconductor layer, the light emitting layer and a portion of the first type semiconductor layer to form an opening, the first type semiconductor layer exposed by the opening has a first width; and removing the first pattern After the photoresist layer is formed, a sacrificial layer is formed to cover the first type semiconductor layer and the second type semiconductor layer; a second patterned photoresist layer is formed to cover the sacrificial layer; and the sacrificial layer is patterned by the second patterned photoresist layer. The first type semiconductor layer exposed in the opening of the sacrificial layer has a second width, and the second width is smaller than the first width; forming a third patterned photoresist layer covering the sacrificial layer and a portion of the first type semiconductor layer, The first patterned semiconductor layer exposed in the opening of the third patterned photoresist layer has a third width, and the third width is smaller than the second width; the third patterned photoresist layer and the sacrificial layer are masked, and the etching is performed. One type semiconductor layer Removing the sacrificial layer and the third patterned photoresist layer; forming an insulating layer covering a portion of the first-type semiconductor layer within the opening; and forming a conductive layer covers the insulating layer in the opening.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
第1圖繪示依照本發明一實施例的發光元件10的上視圖。第2A圖繪示沿著第1圖之2A-2A’剖面線之本發明一實施例的發光元件10的剖面圖。第2B圖繪示沿著第1圖之2B-2B’剖面線之本發明一實施例的發光元件10的剖面圖。第2C圖繪示沿著第1圖之2A-2A’剖面線之本發明一實施例的發光元件10的局部放大剖面圖。1 is a top view of a light-emitting element 10 in accordance with an embodiment of the present invention. Fig. 2A is a cross-sectional view showing a light-emitting element 10 according to an embodiment of the present invention taken along line 2A-2A' of Fig. 1. Fig. 2B is a cross-sectional view showing a light-emitting element 10 according to an embodiment of the present invention taken along line 2B-2B' of Fig. 1. Fig. 2C is a partially enlarged cross-sectional view showing the light-emitting element 10 according to an embodiment of the present invention taken along line 2A-2A' of Fig. 1.
請同時參照第1、2A、2B圖，發光元件10包括一基板100、一第一發光單元110、一第一凹部120、一絕緣層130及一導電層140。Referring to FIGS. 1 , 2A and 2B , the light-emitting element 10 includes a substrate 100 , a first light-emitting unit 110 , a first recess 120 , an insulating layer 130 , and a conductive layer 140 .
基板100可以是一絕緣基板，例如是一藍寶石基板。The substrate 100 may be an insulating substrate such as a sapphire substrate.
第一發光單元110配置於基板100上。第一發光單元110包括一第一半導體層112、一第一發光層114及一第二半導體層116。第一半導體層112配置於基板100之上。第一發光層114配置於第一半導體層112與第二半導體層116之間。The first light emitting unit 110 is disposed on the substrate 100. The first light emitting unit 110 includes a first semiconductor layer 112 , a first light emitting layer 114 , and a second semiconductor layer 116 . The first semiconductor layer 112 is disposed on the substrate 100. The first light emitting layer 114 is disposed between the first semiconductor layer 112 and the second semiconductor layer 116.
第一半導體層112例如是N型半導體層，而第二半導體層116則為P型半導體層；或是，第一半導體層112是P型半導體層，而第二半導體層116則為N型半導體層。材料方面，P型半導體層的例如是摻雜鎂(Mg)之氮化鎵基半導體層，而N型半導體層例如是摻雜矽(Si)之氮化鎵基半導體層。The first semiconductor layer 112 is, for example, an N-type semiconductor layer, and the second semiconductor layer 116 is a P-type semiconductor layer; or, the first semiconductor layer 112 is a P-type semiconductor layer, and the second semiconductor layer 116 is an N-type semiconductor. Floor. In terms of materials, the P-type semiconductor layer is, for example, a gallium nitride-based semiconductor layer doped with magnesium (Mg), and the N-type semiconductor layer is, for example, a gallium nitride-based semiconductor layer doped with germanium (Si).
第一發光層114可以是InxAlyGa1-x-yN (0≦x、0≦y、x+y≦1)結構，可為單一層或多層構造。The first light-emitting layer 114 may be of an InxAlyGa1-x-yN (0≦x, 0≦y, x+y≦1) structure, and may be of a single layer or a multilayer structure.
第一凹部120貫穿第一半導體層112，且具有一第一側壁110a。第一側壁110a係由第一半導體層112所定義。亦即，第一半導體層112具有第一側壁110a。The first recess 120 penetrates the first semiconductor layer 112 and has a first sidewall 110a. The first sidewall 110a is defined by the first semiconductor layer 112. That is, the first semiconductor layer 112 has a first sidewall 110a.
絕緣層130覆蓋第一凹部120之第一側壁110a、第一半導體層112上、第一半導體層112的側壁、第二半導體層116的側壁、第一發光層114的側壁、第二半導體層116以及基板100上，第一側壁110a係由第一半導體層112的側壁所定義。絕緣層130的材料例如是二氧化矽(SiO2)、二氧化鈦(TiO2)或氧化物等絕緣材料。The insulating layer 130 covers the first sidewall 110a of the first recess 120, the first semiconductor layer 112, the sidewall of the first semiconductor layer 112, the sidewall of the second semiconductor layer 116, the sidewall of the first luminescent layer 114, and the second semiconductor layer 116. And on the substrate 100, the first sidewall 110a is defined by the sidewall of the first semiconductor layer 112. The material of the insulating layer 130 is, for example, an insulating material such as cerium oxide (SiO2 ), titanium oxide (TiO2 ) or oxide.
導電層140連接第一發光單元110與一第二發光單元160。導電層140的材料可以是金屬。導電層140例如是由金(Au)、鋁(Al)、鉻(Cr)、鉑(Pt)、鈦(Ti)、鎳(Ni)、或銦錫氧化物(Indium Tin Oxide, ITO)等導電材料所形成。導電層140可以是單層或多層結構。例如，導電層140可以是Cr/Al/Ti/Pt/Au的多層結構、可以是Cr/Al/Ti/Pt/Ti/Pt/Au的多層結構、或部分週期性金屬結構。或者，多層結構中的最外層為非金(Au)元素所構成，例如是由鉻(Cr)、鉑(Pt)、鈦(Ti)、鎳(Ni)或鋁(Al)所構成。此外，多層結構之導電層140的形成方法可以由一種或二種以上之鍍膜方式形成，例如是先藉由濺鍍法形成Cr/Al/Ti層之後，再藉由電子鎗蒸鍍法(e-beam gun)形成Ti/Pt/Au。The conductive layer 140 connects the first light emitting unit 110 and the second light emitting unit 160. The material of the conductive layer 140 may be a metal. The conductive layer 140 is electrically conductive, for example, of gold (Au), aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), nickel (Ni), or indium tin oxide (ITO). The material is formed. The conductive layer 140 may be a single layer or a multilayer structure. For example, the conductive layer 140 may be a multilayer structure of Cr/Al/Ti/Pt/Au, a multilayer structure of Cr/Al/Ti/Pt/Ti/Pt/Au, or a partially periodic metal structure. Alternatively, the outermost layer in the multilayer structure is composed of a non-gold (Au) element, for example, chromium (Cr), platinum (Pt), titanium (Ti), nickel (Ni) or aluminum (Al). In addition, the method for forming the conductive layer 140 of the multilayer structure may be formed by one or more coating methods, for example, after forming a Cr/Al/Ti layer by sputtering, and then evaporating by electron gun (e- Beam gun) forms Ti/Pt/Au.
第二發光單元160可配置於基板100，且包括一第三半導體層162、一第二發光層164及一第四半導體層166。第三半導體層162配置於基板100之上。第二發光層164配置於第三半導體層162與第四半導體層166之間。第三半導體層162、第四半導體層166及第二發光層164之材料分別類似於上述第一半導體層112、第二半導體層116及第一發光層114，容此不再贅述。The second light emitting unit 160 is disposed on the substrate 100 and includes a third semiconductor layer 162 , a second light emitting layer 164 , and a fourth semiconductor layer 166 . The third semiconductor layer 162 is disposed on the substrate 100. The second light emitting layer 164 is disposed between the third semiconductor layer 162 and the fourth semiconductor layer 166. The materials of the third semiconductor layer 162, the fourth semiconductor layer 166, and the second light-emitting layer 164 are similar to the first semiconductor layer 112, the second semiconductor layer 116, and the first light-emitting layer 114, respectively, and are not described herein.
第一發光單元110具有一第二側壁110b，第二側壁110b係由第一半導體層112所定義。亦即，第一半導體層112具有第二側壁110b。請參照第1圖，第一側壁110a與第二側壁110b係彼此連接，第二側壁110b可以是第一半導體層112於第一凹部120之外的側壁。The first light emitting unit 110 has a second sidewall 110b defined by the first semiconductor layer 112. That is, the first semiconductor layer 112 has the second sidewall 110b. Referring to FIG. 1 , the first sidewall 110 a and the second sidewall 110 b are connected to each other, and the second sidewall 110 b may be a sidewall of the first semiconductor layer 112 outside the first recess 120 .
第一凹部120更貫穿第三半導體層162且具有一第三側壁160a，第三側壁160a係由第三半導體層162所定義。亦即，第三半導體層162具有第三側壁160a。導電層140經由第一凹部120連接第一發光單元110及第二發光單元160。第一側壁110a及第三側壁160a係第一凹部120中相對二側壁，位於第一凹部120內的導電層140經由第一側壁110a及第三側壁160a電性連接第二半導體層116及第三半導體層162。The first recess 120 further penetrates the third semiconductor layer 162 and has a third sidewall 160a defined by the third semiconductor layer 162. That is, the third semiconductor layer 162 has a third sidewall 160a. The conductive layer 140 connects the first light emitting unit 110 and the second light emitting unit 160 via the first recess 120. The first sidewalls 110a and the third sidewalls 160a are the opposite sidewalls of the first recess 120. The conductive layer 140 in the first recess 120 is electrically connected to the second semiconductor layer 116 and the third via the first sidewall 110a and the third sidewall 160a. Semiconductor layer 162.
第二發光單元160具有一第四側壁160b，第四側壁160b係由第三半導體層162所定義。亦即，第三半導體層162具有第四側壁160b。請參照第1圖，第三側壁160a與第四側壁160b係彼此連接，第四側壁160b可以是第三半導體層162於第一凹部120之外的側壁。The second light emitting unit 160 has a fourth sidewall 160b defined by the third semiconductor layer 162. That is, the third semiconductor layer 162 has a fourth sidewall 160b. Referring to FIG. 1 , the third sidewall 160 a and the fourth sidewall 160 b are connected to each other, and the fourth sidewall 160 b may be a sidewall of the third semiconductor layer 162 outside the first recess 120 .
請參照第2A圖，在第一半導體層112中，第一側壁110a與基板100之間具有一第一夾角α1，第二側壁110b與基板100之間具有一第二夾角α2，第一夾角α1小於第二夾角α2。例如，第一夾角α1小於70度，而第二夾角α2大於70度。或者，第一夾角α1小於50度，而第二夾角α2大於50度。Referring to FIG. 2A, in the first semiconductor layer 112, the first sidewall 110a and the substrate 100 have a first angle α1 , and the second sidewall 110b and the substrate 100 have a second angle α2 , first The angle α1 is smaller than the second angle α2 . For example, the first angle α1 is less than 70 degrees and the second angle α2 is greater than 70 degrees. Alternatively, the first angle α1 is less than 50 degrees and the second angle α2 is greater than 50 degrees.
在第三半導體層162中，第三側壁160a與基板100之間具有一第三夾角α3，第四側壁160b與基板100之間具有一第四夾角α4，第三夾角α3小於第四夾角α4。例如，第三夾角α3小於70度，而第四夾角α4大於70度。或者，第三夾角α3小於50度，而第四夾角α4大於50度。In the third semiconductor layer 162, the third sidewall 160a and the substrate 100 have a third angle α3 , and the fourth sidewall 160b and the substrate 100 have a fourth angle α4 , and the third angle α3 is smaller than the fourth. Angle α4 . For example, the third angle α3 is less than 70 degrees and the fourth angle α4 is greater than 70 degrees. Alternatively, the third angle α3 is less than 50 degrees and the fourth angle α4 is greater than 50 degrees.
在一實施例中，第一夾角α1、第二夾角α2、第三夾角α3、及第四夾角α4可以為銳角。其中，第一夾角α1及第三夾角α3可以是介於20度到70度之間之夾角，較佳的是第一夾角α1及第三夾角α3介於30度到50度。In an embodiment, the first angle α1 , the second angle α2 , the third angle α3 , and the fourth angle α4 may be acute angles. The first angle α1 and the third angle α3 may be between 20 degrees and 70 degrees, and preferably the first angle α1 and the third angle α3 are between 30 degrees and 50 degrees.
在本實施例中，由於第一夾角α1或第三夾角α3小於70度，相較於第一半導體層中第二側壁與基板之間之夾角、或第三半導體層中第四側壁與基板之間之夾角大於70度的比較例而言，本發明之導電層140較不易受到重力的影響而產生脫落的現象，故能具有較佳的附著力。In this embodiment, since the first angle α1 or the third angle α3 is less than 70 degrees, compared with the angle between the second sidewall of the first semiconductor layer and the substrate, or the fourth sidewall of the third semiconductor layer In the comparative example in which the angle between the substrates is more than 70 degrees, the conductive layer 140 of the present invention is less susceptible to the influence of gravity and is detached, so that it has better adhesion.
在一實施例中，第一側壁110a投影於基板100的一第一長度L1大於第二側壁110b投影於基板100的一第二長度L2。第三側壁160a投影於基板100的一第三長度L3大於第四側壁160b投影於基板100的一第四長度L4。In one embodiment, a first length L1 of the first sidewall 110 a projected on the substrate 100 is greater than a second length L2 of the second sidewall 110 b projected onto the substrate 100 . A third length L3 of the third sidewall 160a projected on the substrate 100 is greater than a fourth length L4 of the fourth sidewall 160b projected onto the substrate 100.
在本實施例中，由於第一夾角α1小於第二夾角α2，且第一長度L1大於第二長度L2，故相較於第一夾角與第二夾角相似且第一長度與第二長度相似的比較例而言，本實施例之第一發光單元110保留較多的第一發光層114之上表面114a的面積，故而具有較大的發光面積。In this embodiment, since the first angle α1 is smaller than the second angle α2 and the first length L1 is greater than the second length L2 , the first angle is similar to the second angle and the first length is the same as the first angle In the second comparative example, the first light emitting unit 110 of the present embodiment retains a larger area of the upper surface 114a of the first light emitting layer 114, and thus has a larger light emitting area.
請參照第2B圖，第一發光單元110及第二發光單元160之間具有第二凹部122。由於第二側壁110b及第四側壁160b上不需形成導電層，故在第一半導體層112中，第二側壁110b與基板100所形成的第二夾角α2可大於50度，或者大於70度，且在第三半導體層162中，第四側壁160b與基板100所形成的第四夾角α4可大於50度，或者大於70度。因此，相較於第二夾角或第四夾角小於70度的比較例而言，本實施例之第一發光單元110保留較多的第一發光層114之上表面114a及第二發光層164之上表面164a的面積，故而具有較大的發光面積。Referring to FIG. 2B , a second recess 122 is defined between the first light emitting unit 110 and the second light emitting unit 160 . Since the conductive layer is not formed on the second sidewall 110b and the fourth sidewall 160b, the second angle α2 formed by the second sidewall 110b and the substrate 100 in the first semiconductor layer 112 may be greater than 50 degrees, or greater than 70 degrees. And in the third semiconductor layer 162, the fourth angle α4 formed by the fourth sidewall 160b and the substrate 100 may be greater than 50 degrees, or greater than 70 degrees. Therefore, the first light emitting unit 110 of the present embodiment retains more of the upper surface 114a and the second light emitting layer 164 of the first light emitting layer 114 than the second angle or the fourth angle is less than 70 degrees. The area of the upper surface 164a has a large light-emitting area.
請參照第2C圖，發光元件10中，導電層140包括一第一連接部1421、一第二連接部1422、一第一本體部1441及一第二本體部1442。第一連接部1421直接形成於基板100之上表面100a上方，而第一本體部1441形成於基板100之上表面100a上的絕緣層130上。第二連接部1422形成於第三側壁160a上，而第二本體部1442形成於第一側壁110a上之絕緣層130上。The conductive layer 140 includes a first connecting portion 1421, a second connecting portion 1422, a first body portion 1441, and a second body portion 1442. The first connection portion 1421 is directly formed over the upper surface 100a of the substrate 100, and the first body portion 1441 is formed on the insulating layer 130 on the upper surface 100a of the substrate 100. The second connecting portion 1422 is formed on the third sidewall 160a, and the second body portion 1442 is formed on the insulating layer 130 on the first sidewall 110a.
第一連接部1421的上表面1421a與基板100之上表面100a之間的第一距離D1可介於0.1µm與10µm之間，其中較佳的第一距離D1介於0.5µm與5µm之間。第一本體部1441的外表面1441a與基板100之上表面100a之間具有一第二距離D2，第一距離D1小於第二距離D2。第二距離D2可介於0.1µm與10µm之間，其中較佳的第二距離D2介於0.5µm與5µm之間。The first distance D1 between the upper surface 1421a of the first connecting portion 1421 and the upper surface 100a of the substrate 100 may be between 0.1 μm and 10 μm, wherein a preferred first distance D1 is between 0.5 μm and 5 μm. The outer surface 1441a of the first body portion 1441 and the upper surface 100a of the substrate 100 have a second distance D2, and the first distance D1 is smaller than the second distance D2. The second distance D2 may be between 0.1 μm and 10 μm, wherein the preferred second distance D2 is between 0.5 μm and 5 μm.
第二連接部1422的外表面1422a與第三側壁160a之間的第三距離D3介於0.1µm與10µm之間，其中較佳的第三距離D3介於0.3µm與3µm之間，第三距離D3小於或等於第一距離D1。第二本體部1442的外表面1442a與第一側壁110a之間的第四距離D4介於0.1µm與10µm之間，其中較佳的第四距離D4介於0.3µm與3µm之間，第四距離D4小於或等於第二距離D2。第三距離D3小於第四距離D4。The third distance D3 between the outer surface 1422a of the second connecting portion 1422 and the third sidewall 160a is between 0.1 μm and 10 μm, wherein the preferred third distance D3 is between 0.3 μm and 3 μm, and the third distance D3 is less than or equal to the first distance D1. The fourth distance D4 between the outer surface 1442a of the second body portion 1442 and the first sidewall 110a is between 0.1 μm and 10 μm, wherein the preferred fourth distance D4 is between 0.3 μm and 3 μm, and the fourth distance D4 is less than or equal to the second distance D2. The third distance D3 is smaller than the fourth distance D4.
在本實施例中，由於第一距離D1小於第二距離D2，且第三距離D3小於第四距離D4，表示導電層140係直接接觸於基板100之上表面100a及第三側壁160a。由於導電層140與基板100之間的附著力、或者是導電層140與第三側壁160a之間的附著力皆優於導電層140與絕緣層130之間的附著力。因此，相較於傳統的發光元件而言，本發明之導電層140可具有較佳的附著力，在製程期間，導電層140較不易產生剝離的現象且亦不易產生孔洞，進而改善電性之傳導。In this embodiment, since the first distance D1 is smaller than the second distance D2, and the third distance D3 is smaller than the fourth distance D4, the conductive layer 140 is directly in contact with the upper surface 100a and the third sidewall 160a of the substrate 100. The adhesion between the conductive layer 140 and the substrate 100 or the adhesion between the conductive layer 140 and the third sidewall 160a is superior to the adhesion between the conductive layer 140 and the insulating layer 130. Therefore, compared with the conventional light-emitting element, the conductive layer 140 of the present invention can have better adhesion. During the process, the conductive layer 140 is less prone to peeling and is less prone to holes, thereby improving electrical properties. Conduction.
第3圖至第14圖繪示第1圖之發光元件10的製造過程圖。3 to 14 are views showing a manufacturing process of the light-emitting element 10 of Fig. 1.
如第3圖所示，形成一基板100。基板100例如是一藍寶石基板。As shown in FIG. 3, a substrate 100 is formed. The substrate 100 is, for example, a sapphire substrate.
如第4圖所示，形成一第一型半導體層111於基板100上。第一型半導體層111例如是N型半導體層或者是P型半導體層。材料方面，P型半導體層例如是摻雜鈹(Be)、鋅(Zn)、錳(Mn)、鉻(Cr)、鎂(Mg)、鈣(Ca)等之氮化鎵基半導體層，而N型半導體層例如是摻雜矽(Si)、鍺(Ge)、錫(Sn)、硫(S)、氧(O)、鈦(Ti)及或鋯(Zr)等之氮化鎵基半導體層。As shown in FIG. 4, a first type semiconductor layer 111 is formed on the substrate 100. The first type semiconductor layer 111 is, for example, an N type semiconductor layer or a P type semiconductor layer. In terms of materials, the P-type semiconductor layer is, for example, a gallium nitride-based semiconductor layer doped with beryllium (Be), zinc (Zn), manganese (Mn), chromium (Cr), magnesium (Mg), calcium (Ca), or the like. The N-type semiconductor layer is, for example, a gallium nitride-based semiconductor doped with bismuth (Si), germanium (Ge), tin (Sn), sulfur (S), oxygen (O), titanium (Ti), or zirconium (Zr). Floor.
如第5圖所示，形成一發光層113於第一型半導體層111上。發光層113例如是InxAlyGa1-x-yN (0≦x、0≦y、x+y≦1)結構，亦可混雜硼(B)或磷(P)或砷(As)，可為單一層或多層構造。As shown in FIG. 5, a light-emitting layer 113 is formed on the first-type semiconductor layer 111. The light-emitting layer 113 is, for example, an InxAlyGa1-x-yN (0≦x, 0≦y, x+y≦1) structure, and may be mixed with boron (B) or phosphorus (P) or arsenic (As), and may be a single layer or Multi-layer construction.
如第6圖所示，形成一第二型半導體層115於發光層113上。第二型半導體層115與第一型半導體層111具有相反的導電型。例如，當第一型半導體層113是N型半導體層時，第二型半導體層115則是P形半導體層；或者當第一型半導體層113是P型半導體層時，第二型半導體層115則是N形半導體層。As shown in FIG. 6, a second type semiconductor layer 115 is formed on the light emitting layer 113. The second type semiconductor layer 115 has an opposite conductivity type to the first type semiconductor layer 111. For example, when the first type semiconductor layer 113 is an N type semiconductor layer, the second type semiconductor layer 115 is a P type semiconductor layer; or when the first type semiconductor layer 113 is a P type semiconductor layer, the second type semiconductor layer 115 Then it is an N-shaped semiconductor layer.
第7A、8A、9A、10A、11A、12A、13A圖繪示欲形成導電層之區域的剖面圖。形成導電層之區域的剖面圖例如是對應第1圖之2A-2A’剖面線的剖面圖。第7B、8B、9B、10B、11B、12B、13B圖繪示沒有形成導電層之區域的剖面圖。沒有形成導電層之區域的剖面圖例如是對應第1圖之2B-2B’剖面線的剖面圖。7A, 8A, 9A, 10A, 11A, 12A, and 13A are cross-sectional views showing a region where a conductive layer is to be formed. The cross-sectional view of the region in which the conductive layer is formed is, for example, a cross-sectional view corresponding to the hatching of 2A-2A' in Fig. 1 . 7B, 8B, 9B, 10B, 11B, 12B, and 13B are cross-sectional views showing a region where a conductive layer is not formed. A cross-sectional view of a region where the conductive layer is not formed is, for example, a cross-sectional view corresponding to the hatching of 2B-2B' in Fig. 1 .
如第7A及7B圖所示，形成一第一光阻層19於第二型半導體層115上。接著，圖案化第一光阻層19，以形成第一圖案化光阻層19於第二型半導體層115上且露出部分第二型半導體層115，其中圖案化之後的第一光阻層19具有一寬度Wa及一寬度Wb。寬度Wa小於寬度Wb。寬度Wa對應於欲形成導電層的區域(如第7A圖所示)，寬度Wb對應於沒有形成導電層的區域(如第7B圖所示)。可藉由旋轉塗佈法(spin coating)形成第一光阻層19，第一光阻層19例如是聚合物。As shown in FIGS. 7A and 7B, a first photoresist layer 19 is formed on the second type semiconductor layer 115. Next, the first photoresist layer 19 is patterned to form a first patterned photoresist layer 19 on the second type semiconductor layer 115 and expose a portion of the second type semiconductor layer 115, wherein the first photoresist layer 19 after patterning is formed. There is a width Wa and a width Wb . The width Wa is smaller than the width Wb . The width Wa corresponds to a region where the conductive layer is to be formed (as shown in FIG. 7A ), and the width Wb corresponds to a region where the conductive layer is not formed (as shown in FIG. 7B ). The first photoresist layer 19 can be formed by spin coating, and the first photoresist layer 19 is, for example, a polymer.
如第8A及8B圖所示，以第一光阻層19為遮罩，蝕刻第二型半導體層115、發光層113及部分第一型半導體層111，以在第二型半導體層115與發光層113上形成一第一開口124及一第二開口126，第一開口124及第二開口126暴露第一型半導體層111及一側面110s，其中側面110s係由第一型半導體層111的側面111s、第二型半導體層115的側面115s與發光層113的側面113s共同定義。第一開口124投影於基板100的一寬度W1大於第二開口126投影於基板100的一寬度W2。第一開口124對應於欲形成導電層的區域(如第8A圖所示)，第二開口126對應於沒有形成導電層的區域(如第8B圖所示)。可藉由乾式蝕刻形成第一開口124及第二開口126，乾式蝕刻例如是感應式耦合電漿法。As shown in FIGS. 8A and 8B, the second photoresist layer 19, the light-emitting layer 113, and a portion of the first-type semiconductor layer 111 are etched with the first photoresist layer 19 as a mask to illuminate the second-type semiconductor layer 115. A first opening 124 and a second opening 126 are formed on the layer 113. The first opening 124 and the second opening 126 expose the first type semiconductor layer 111 and a side surface 110s, wherein the side surface 110s is formed by the side of the first type semiconductor layer 111. 111s, the side surface 115s of the second type semiconductor layer 115 is defined in common with the side surface 113s of the light-emitting layer 113. A width W1 of the first opening 124 projected on the substrate 100 is greater than a width W2 projected by the second opening 126 on the substrate 100. The first opening 124 corresponds to a region where the conductive layer is to be formed (as shown in FIG. 8A), and the second opening 126 corresponds to a region where the conductive layer is not formed (as shown in FIG. 8B). The first opening 124 and the second opening 126 may be formed by dry etching, for example, an inductively coupled plasma method.
如第9A及9B圖所示，移除第一圖案化光阻層19後，形成一犧牲層117覆蓋第二型半導體層115、側面110s及第一型半導體層111。犧牲層117可包括一氧化物膜或一氮化物膜。As shown in FIGS. 9A and 9B, after the first patterned photoresist layer 19 is removed, a sacrificial layer 117 is formed to cover the second type semiconductor layer 115, the side surface 110s, and the first type semiconductor layer 111. The sacrificial layer 117 may include an oxide film or a nitride film.
如第10A及10B圖所示，形成一第二光阻層119於犧牲層117上，圖案化第二光阻層119以形成第二圖案化光阻層119覆蓋犧牲層117且露出部分犧牲層117。藉由第二圖案化光阻層119圖案化犧牲層117，於第一開口124內形成犧牲層117且露出第一型半導體層111，並於第二開口內126形成犧牲層117且露出第一半導體層111。其中，第一開口124內所暴露出的第一型半導體層111投影於基板100具有一寬度W3，寬度W3亦即是犧牲層117於第一開口124內所露出的第一型半導體層111投影於基板100的寬度。第二開口126內所暴露出的第一型半導體層111投影於基板100具有一寬度W4，寬度W4亦即是犧牲層117於第二開口126內所露出的第一型半導體層111投影於基板100的寬度。寬度W3係大於寬度W4。第二光阻層119之材料可類似於第一光阻層19，容此不再贅述。As shown in FIGS. 10A and 10B, a second photoresist layer 119 is formed on the sacrificial layer 117, and the second photoresist layer 119 is patterned to form a second patterned photoresist layer 119 covering the sacrificial layer 117 and exposing a portion of the sacrificial layer. 117. The sacrificial layer 117 is patterned by the second patterned photoresist layer 119, the sacrificial layer 117 is formed in the first opening 124 and the first type semiconductor layer 111 is exposed, and the sacrificial layer 117 is formed in the second opening 126 and exposed first. Semiconductor layer 111. The first type semiconductor layer 111 exposed in the first opening 124 has a width W3 projected on the substrate 100, and the width W3 is a projection of the first type semiconductor layer 111 exposed by the sacrificial layer 117 in the first opening 124. The width of the substrate 100. The first type semiconductor layer 111 exposed in the second opening 126 has a width W4 projected on the substrate 100, and the width W4, that is, the first type semiconductor layer 111 exposed by the sacrificial layer 117 in the second opening 126 is projected on the substrate. The width of 100. The width W3 is greater than the width W4. The material of the second photoresist layer 119 can be similar to the first photoresist layer 19, and will not be described again.
如第11A及11B圖所示，形成第三光阻層121於第二光阻層119之上。或者，第三光阻層121可在移除如10A及10B圖所示之第二光阻層119之後再形成於犧牲層117之上。圖案化第三光阻層121之後，形成第三圖案化光阻層121覆蓋第一開口124內之犧牲層117及部分第一型半導體層111，覆蓋第二開口126內之犧牲層117且露出第一型半導體層111，其中在圖案化第三光阻層121之後，第三光阻層121於第一開口124內所露出的第一型半導體層111投影於基板100上具有一寬度W5，寬度W5係小於寬度W3。其中，第三光阻層121與犧牲層117具有不同的蝕刻速率。在本實施例中，犧牲層117的蝕刻速率係小於第三光阻層121的蝕刻速率。犧牲層117之材料可以是二氧化矽(SiO2)。第二光阻層119及第三光阻層121之材料可類似於第一光阻層19，容此不再贅述。可藉由電漿輔助化學氣相沈積(Plasma-Enhanced Chemical Vapor Deposition, PECVD)、電子槍蒸鍍法形成犧牲層117。可藉由旋轉塗佈法形成第二光阻層119及第三光阻層121。As shown in FIGS. 11A and 11B, a third photoresist layer 121 is formed over the second photoresist layer 119. Alternatively, the third photoresist layer 121 may be formed on the sacrificial layer 117 after removing the second photoresist layer 119 as shown in FIGS. 10A and 10B. After the third photoresist layer 121 is patterned, the third patterned photoresist layer 121 is formed to cover the sacrificial layer 117 and the portion of the first type semiconductor layer 111 in the first opening 124, covering the sacrificial layer 117 in the second opening 126 and exposed. The first type semiconductor layer 111 has a width W5 projected on the substrate 100 by the first type semiconductor layer 111 exposed by the third photoresist layer 121 in the first opening 124 after the third photoresist layer 121 is patterned. The width W5 is smaller than the width W3. The third photoresist layer 121 and the sacrificial layer 117 have different etching rates. In the present embodiment, the etching rate of the sacrificial layer 117 is smaller than the etching rate of the third photoresist layer 121. The material of the sacrificial layer 117 may be cerium oxide (SiO2 ). The materials of the second photoresist layer 119 and the third photoresist layer 121 may be similar to the first photoresist layer 19, and will not be described again. The sacrificial layer 117 can be formed by plasma-assisted chemical vapor deposition (PECVD) or electron gun evaporation. The second photoresist layer 119 and the third photoresist layer 121 can be formed by a spin coating method.
如第12A及12B圖所示，以第三光阻層121及犧牲層117為遮罩，蝕刻第一型半導體層111，以於第一開口124內形成一第一凹部120貫穿第一型半導體層111且於第二開口126內形成一第二凹部122貫穿第一型半導體層111。第一凹部120具有一第一側壁110a，而第二凹部122具有一第二側壁110b，其中第一側壁110a對應於如第12A圖所示之第一型半導體層111的第一側壁110a，且對應於如第13A圖所示之第一半導體層112的第一側壁110a；第二側壁110b對應於如第12A~12B圖所示之第一型半導體層111的第二側壁110b，且對應於如第13A~13B圖所示之第一半導體層112的第二側壁110b。第一側壁110a與基板100之間具有一第一夾角α1，第二側壁110b與基板100之間具有一第二夾角α2，第一夾角α1及第二夾角α2可以為銳角，第一夾角α1小於第二夾角α2。第一側壁110a投影於基板100的一第一長度L1大於第二側壁110b投影於基板100的一第二長度L2。第一凹部120之最大寬度係大於第二凹部122之最大寬度。第一凹部120及第二凹部122暴露基板100。此外，可藉由感應式耦合電漿法及反應性離子蝕刻法形成第一凹部120及第二凹部122。As shown in FIGS. 12A and 12B, the first photoresist layer 111 is etched by using the third photoresist layer 121 and the sacrificial layer 117 as a mask to form a first recess 120 through the first semiconductor in the first opening 124. A second recess 122 is formed in the layer 111 and penetrates the first type semiconductor layer 111 in the second opening 126. The first recess 120 has a first sidewall 110a, and the second recess 122 has a second sidewall 110b, wherein the first sidewall 110a corresponds to the first sidewall 110a of the first type semiconductor layer 111 as shown in FIG. 12A, and Corresponding to the first sidewall 110a of the first semiconductor layer 112 as shown in FIG. 13A; the second sidewall 110b corresponds to the second sidewall 110b of the first type semiconductor layer 111 as shown in FIGS. 12A-12B, and corresponds to The second sidewall 110b of the first semiconductor layer 112 as shown in FIGS. 13A-13B. The first side wall 110a and the substrate 100 have a first angle α1 , and the second side wall 110b and the substrate 100 have a second angle α2 , and the first angle α1 and the second angle α2 can be acute angles. An angle α1 is smaller than the second angle α2 . A first length L1 of the first sidewall 110a projected on the substrate 100 is greater than a second length L2 projected by the second sidewall 110b on the substrate 100. The maximum width of the first recess 120 is greater than the maximum width of the second recess 122. The first recess 120 and the second recess 122 expose the substrate 100. Further, the first concave portion 120 and the second concave portion 122 may be formed by an inductively coupled plasma method and a reactive ion etching method.
在本實施例中，由於犧牲層117的蝕刻速率小於第三光阻層121的蝕刻速率，在蝕刻的過程中，覆蓋犧牲層117之區域相較於沒有覆蓋犧牲層117之區域而言，蝕刻速率亦較小，使得在第一開口124及第二開口126內沒有覆蓋犧牲層117之區域具有較快的蝕刻速率，第二凹部122之側壁相較於第一凹部120之側壁更為陡峭。此外，由於犧牲層117於第一開口124內所露出的第一型半導體層111投影於基板100的寬度W3係大於犧牲層117於第二開口126內所露出的第一型半導體層111投影於基板100的寬度W4，且第三光阻層121於第一開口124內所露出的第一型半導體層111投影於基板100上的寬度W5係小於寬度W3，使得第二凹部122之側壁相較於第一凹部120之側壁更為陡峭。因此，透過犧牲層117以及第三光阻層121之使用，能夠控制所蝕刻的圖案，使得受到犧牲層117保護之第一型半導體層111較不易受到蝕刻，並讓第一側壁110a與第二側壁110b具有不同的傾斜程度，如此不但能夠避免導電層的斷線或脫落，亦可保留較大的發光區域，以改善晶片的效率。In the present embodiment, since the etching rate of the sacrificial layer 117 is smaller than the etching rate of the third photoresist layer 121, the region covering the sacrificial layer 117 is etched during the etching as compared with the region not covered with the sacrificial layer 117. The rate is also small such that the regions of the first opening 124 and the second opening 126 that are not covered by the sacrificial layer 117 have a faster etch rate, and the sidewalls of the second recess 122 are steeper than the sidewalls of the first recess 120. In addition, the width W3 of the first type semiconductor layer 111 exposed by the sacrificial layer 117 in the first opening 124 is greater than the width of the first type semiconductor layer 111 exposed by the sacrificial layer 117 in the second opening 126. The width W4 of the substrate 100 and the width W5 of the first type semiconductor layer 111 exposed by the third photoresist layer 121 on the substrate 100 are smaller than the width W3, so that the sidewalls of the second recess 122 are compared. The side wall of the first recess 120 is steeper. Therefore, through the use of the sacrificial layer 117 and the third photoresist layer 121, the etched pattern can be controlled such that the first type semiconductor layer 111 protected by the sacrificial layer 117 is less susceptible to etching, and the first sidewall 110a and the second sidewall are made The sidewalls 110b have different degrees of inclination, so that not only the disconnection or detachment of the conductive layer can be avoided, but also a large illuminating region can be retained to improve the efficiency of the wafer.
如第13A及13B圖所示，移除犧牲層117、第二光阻層119及第三光阻層121，並形成第一發光單元110與第二發光單元160。可藉由濕式蝕刻移除犧牲層117、第二光阻層119及第三光阻層121，濕式蝕刻之蝕刻劑例如是氫氟酸(HF)或緩衝氧化蝕刻劑(Buffered Oxide Etchant, BOE)。第一發光單元110包括一第一半導體層112、一第一發光層114、及一第二半導體層116。第一半導體層112配置於基板100之上。第一發光層114配置於第一半導體層112與第二半導體層116之間。第二發光單元160包括一第三半導體層162、一第二發光層164、及一第四半導體層166。第三半導體層162配置於基板100之上。第二發光層164配置於第三半導體層162與第四半導體層166之間。第一發光單元110與第二發光單元160之間具有第一凹部120及第二凹部122。As shown in FIGS. 13A and 13B, the sacrificial layer 117, the second photoresist layer 119, and the third photoresist layer 121 are removed, and the first light emitting unit 110 and the second light emitting unit 160 are formed. The sacrificial layer 117, the second photoresist layer 119 and the third photoresist layer 121 may be removed by wet etching, for example, hydrofluoric acid (HF) or buffered etchant (Buffered Oxide Etchant, BOE). The first light emitting unit 110 includes a first semiconductor layer 112 , a first light emitting layer 114 , and a second semiconductor layer 116 . The first semiconductor layer 112 is disposed on the substrate 100. The first light emitting layer 114 is disposed between the first semiconductor layer 112 and the second semiconductor layer 116. The second light emitting unit 160 includes a third semiconductor layer 162, a second light emitting layer 164, and a fourth semiconductor layer 166. The third semiconductor layer 162 is disposed on the substrate 100. The second light emitting layer 164 is disposed between the third semiconductor layer 162 and the fourth semiconductor layer 166. The first light emitting unit 110 and the second light emitting unit 160 have a first concave portion 120 and a second concave portion 122 .
如第14圖所示，於第一開口124及第一凹部120內形成一絕緣層130覆蓋部分第一半導體層112(例如是覆蓋第一凹部120之第一側壁110a)，並於第一開口124及第一凹部120內形成一導電層140以覆蓋絕緣層130，使得導電層140係連接第一發光單元110的第二半導體層116與一第二發光單元160的第三半導體層162。由於第二凹部122之第二側壁110b並沒有絕緣層130及導電層140，故在形成絕緣層130及導電層140之後，第二凹部122暴露基板100，並不具有絕緣層130及導電層140形成於第一發光單元110與一第二發光單元160之間，如第13B圖所示。As shown in FIG. 14, an insulating layer 130 is formed in the first opening 124 and the first recess 120 to cover a portion of the first semiconductor layer 112 (eg, the first sidewall 110a covering the first recess 120), and is in the first opening. A conductive layer 140 is formed in the first recess 120 to cover the insulating layer 130 such that the conductive layer 140 is connected to the second semiconductor layer 116 of the first light emitting unit 110 and the third semiconductor layer 162 of the second light emitting unit 160. Since the second sidewall 110b of the second recess 122 does not have the insulating layer 130 and the conductive layer 140, after the insulating layer 130 and the conductive layer 140 are formed, the second recess 122 exposes the substrate 100 without the insulating layer 130 and the conductive layer 140. Formed between the first light emitting unit 110 and a second light emitting unit 160, as shown in FIG. 13B.
本實施例中，發光元件10具有2個相鄰的發光單元，然本發明並不限定於此。在其他實施例中，只要在1個發光單元中第一凹部之第一側壁的傾斜程度與第二凹部之第二側壁的傾斜程度不相同，皆能涵蓋於本發明之範疇之中。例如，發光元件可以是由大於2個的發光單元串聯或並聯所組成。In the present embodiment, the light-emitting element 10 has two adjacent light-emitting units, but the present invention is not limited thereto. In other embodiments, as long as the degree of inclination of the first side wall of the first recess in one of the light-emitting units is different from the degree of tilt of the second side wall of the second recess, it can be covered by the scope of the present invention. For example, the light-emitting element may be composed of more than two light-emitting units connected in series or in parallel.
第15圖繪示依照本發明另一實施例的發光元件20的上視圖。Figure 15 is a top plan view of a light-emitting element 20 in accordance with another embodiment of the present invention.
請參照第15圖，發光元件20具有5個發光單元，包括第一發光單元210、第二發光單元260、第三發光單元270、第四發光單元280、及第五發光單元290。第一發光單元210上具有電極E1，第五發光單元290上具有電極E2。電極E1可連接於正電壓，電極E2可連接於負電壓，或者電極E1可連接於負電壓，電極E2可連接於正電壓。第一發光單元210與第二發光單元260之間、第二發光單元260與第三發光單元270之間、第三發光單元270與第四發光單元280之間、及第四發光單元280、與第五發光單元290之間分別具有2個第一凹部220，在另一實施例中可以只具有一個第一凹部220。本實施例中第一凹部220之間或第一凹部220以外則具有第二凹部222。導電層240形成於絕緣層230上，且延伸於第一凹部220中，以電性連接相鄰的2個發光單元。第二凹部222中則不具有導電層240。在本實施例中導電層240是以相同之圖型配置於各發光單元之間，以簡化至生產流程。Referring to FIG. 15, the light-emitting element 20 has five light-emitting units, including a first light-emitting unit 210, a second light-emitting unit 260, a third light-emitting unit 270, a fourth light-emitting unit 280, and a fifth light-emitting unit 290. The first light emitting unit 210 has an electrode E1 thereon, and the fifth light emitting unit 290 has an electrode E2. The electrode E1 can be connected to a positive voltage, the electrode E2 can be connected to a negative voltage, or the electrode E1 can be connected to a negative voltage, and the electrode E2 can be connected to a positive voltage. Between the first illuminating unit 210 and the second illuminating unit 260, between the second illuminating unit 260 and the third illuminating unit 270, between the third illuminating unit 270 and the fourth illuminating unit 280, and the fourth illuminating unit 280, and There are two first recesses 220 between the fifth lighting units 290, and only one first recess 220 in another embodiment. In the present embodiment, the second recess 222 is provided between the first recesses 220 or outside the first recesses 220. The conductive layer 240 is formed on the insulating layer 230 and extends in the first recess 220 to electrically connect the adjacent two light emitting units. There is no conductive layer 240 in the second recess 222. In the present embodiment, the conductive layer 240 is disposed between the respective light emitting units in the same pattern to simplify the production process.
綜上，在本發明實施例的發光元件在製造過程中，可在形成第一凹部及第二凹部之前，形成犧牲層與覆蓋犧牲層的第三光阻層，由於第三光阻層與犧牲層具有不同的蝕刻速率，且犧牲層於第一開口內所露出的第一型半導體層投影於基板的一寬度係大於犧牲層於第二開口內所露出的第一型半導體層投影於基板之一寬度，第三光阻層於第一開口內所露出的第一型半導體層投影於基板上的一寬度亦小於犧牲層於第一開口內所露出的第一型半導體層投影於基板的寬度，因此能夠在形成第一凹部及第二凹部時，產生傾斜程度不同的第一側壁及第二側壁，其中第一側壁與基板之間的第一夾角小於第二側壁與基板之間的第二夾角，第一側壁投影於基板的一第一長度大於第二側壁投影於基板的一第二長度。如此一來，僅需要針對具有導電層的區域(第一凹部)，形成與基板之夾角較小的第一側壁即可，對於導電層之外的區域(第二凹部)，則不需要提供與基板之夾角較小的斜坡結構給導電層，因此可以形成與基板之夾角較大的第二側壁，減少發光元件被蝕刻的面積，以改善發光區域縮小、生產成本增加的問題。In summary, in the manufacturing process of the light-emitting device of the embodiment of the present invention, the sacrificial layer and the third photoresist layer covering the sacrificial layer may be formed before the first recess and the second recess are formed, due to the third photoresist layer and the sacrifice The layers have different etch rates, and the first type semiconductor layer exposed by the sacrificial layer in the first opening is projected onto the substrate, and the first type semiconductor layer exposed in the second opening is projected on the substrate. a width, a width of the first type semiconductor layer exposed by the third photoresist layer in the first opening is smaller than a width of the first type semiconductor layer exposed by the sacrificial layer in the first opening Therefore, when the first recess and the second recess are formed, the first sidewall and the second sidewall having different degrees of inclination are generated, wherein the first angle between the first sidewall and the substrate is smaller than the second between the second sidewall and the substrate The first length of the first sidewall projected on the substrate is greater than a second length projected by the second sidewall onto the substrate. In this way, it is only necessary to form a first sidewall having a small angle with the substrate for the region having the conductive layer (the first recess), and for the region other than the conductive layer (the second recess), it is not necessary to provide The slope structure with a small angle between the substrates is applied to the conductive layer, so that a second sidewall having a larger angle with the substrate can be formed, and the area where the light-emitting elements are etched can be reduced, thereby improving the problem that the light-emitting area is reduced and the production cost is increased.
此外，由於導電層與基板之間的附著力、或者是導電層與第三側壁之間的附著力皆優於導電層與絕緣層之間的附著力。因此，相較於傳統的發光元件而言，由於本發明的發光元件中，導電層係直接接觸於基板之上表面及第三側壁，故本發明之導電層可具有較佳的附著力，在製程期間，導電層較不易產生剝離的現象且亦不易產生孔洞，進而改善電性之傳導。In addition, the adhesion between the conductive layer and the substrate, or the adhesion between the conductive layer and the third sidewall is superior to the adhesion between the conductive layer and the insulating layer. Therefore, compared with the conventional light-emitting element, since the conductive layer directly contacts the upper surface of the substrate and the third sidewall in the light-emitting element of the present invention, the conductive layer of the present invention can have better adhesion. During the process, the conductive layer is less prone to peeling and is less prone to holes, thereby improving electrical conduction.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
10、20‧‧‧發光元件
19‧‧‧第一光阻層
100‧‧‧基板
110、210‧‧‧第一發光單元
110a‧‧‧第一側壁
110b‧‧‧第二側壁
110s、111s、113s、115s‧‧‧側面
111‧‧‧第一型半導體層
112‧‧‧第一半導體層
113‧‧‧發光層
114‧‧‧第一發光層
114a、164a、1421a‧‧‧上表面
115‧‧‧第二型半導體層
116‧‧‧第二半導體層
117‧‧‧犧牲層
119‧‧‧第二光阻層
120、220‧‧‧第一凹部
122、222‧‧‧第二凹部
124‧‧‧第一開口
126‧‧‧第二開口
130‧‧‧絕緣層
140‧‧‧導電層
160、260‧‧‧第二發光單元
160a‧‧‧第三側壁
160b‧‧‧第四側壁
162‧‧‧第三半導體層
164‧‧‧第二發光單元
166‧‧‧第四半導體層
270‧‧‧第三發光單元
280‧‧‧第四發光單元
290‧‧‧第五發光單元
1421‧‧‧第一連接部
1422‧‧‧第二連接部
1441‧‧‧第一本體部
1442‧‧‧第二本體部
1422a、1441a、1442a‧‧‧外表面
2A、2A’、2B、2B’‧‧‧剖面線端點
D1、D2、D3、D4‧‧‧距離
E1、E2‧‧‧電極
L1、L2、L3、L4‧‧‧長度
W1、W2、W3、W4、W5‧‧‧寬度
α1、α2、α3、α4‧‧‧夾角10, 20‧‧‧Lighting elements
19‧‧‧First photoresist layer
100‧‧‧Substrate
110, 210‧‧‧ first lighting unit
110a‧‧‧First side wall
110b‧‧‧second side wall
110s, 111s, 113s, 115s‧‧‧ side
111‧‧‧First type semiconductor layer
112‧‧‧First semiconductor layer
113‧‧‧Lighting layer
114‧‧‧First luminescent layer
114a, 164a, 1421a‧‧‧ upper surface
115‧‧‧Second type semiconductor layer
116‧‧‧Second semiconductor layer
117‧‧‧ sacrificial layer
119‧‧‧second photoresist layer
120, 220‧‧‧ first recess
122, 222‧‧‧ second recess
124‧‧‧ first opening
126‧‧‧ second opening
130‧‧‧Insulation
140‧‧‧ Conductive layer
160, 260‧‧‧second lighting unit
160a‧‧‧ third side wall
160b‧‧‧fourth sidewall
162‧‧‧ third semiconductor layer
164‧‧‧second lighting unit
166‧‧‧fourth semiconductor layer
270‧‧‧3rd lighting unit
280‧‧‧fourth illumination unit
290‧‧‧ fifth illumination unit
1421‧‧‧First connection
1422‧‧‧Second connection
1441‧‧‧First Body Department
1442‧‧‧Second body
1422a, 1441a, 1442a‧‧‧ outer surface
2A, 2A', 2B, 2B'‧‧‧ hatch end points
D1, D2, D3, D4‧‧‧ distance
E1, E2‧‧‧ electrodes
L1 , L2 , L3 , L4 ‧‧‧ length
W1, W2, W3, W4, W5‧‧‧ width α1 , α2 , α3 , α4 ‧‧‧ angle
第1圖繪示依照本發明一實施例的發光元件的上視圖。 第2A圖繪示沿著第1圖之2A-2A’剖面線之本發明一實施例的發光元件的剖面圖。 第2B圖繪示沿著第1圖之2B-2B’剖面線之本發明一實施例的發光元件的剖面圖。 第2C圖繪示沿著第1圖之2A-2A’剖面線之本發明一實施例的發光元件的局部放大剖面圖。 第3圖至第14圖繪示依照本發明一實施例的發光元件的製造過程圖。 第15圖繪示依照本發明另一實施例的發光元件的上視圖。1 is a top view of a light-emitting element in accordance with an embodiment of the present invention. Fig. 2A is a cross-sectional view showing a light-emitting element according to an embodiment of the present invention taken along line 2A-2A' of Fig. 1. Fig. 2B is a cross-sectional view showing a light-emitting element according to an embodiment of the present invention taken along line 2B-2B' of Fig. 1. Fig. 2C is a partially enlarged cross-sectional view showing a light-emitting element according to an embodiment of the present invention taken along line 2A-2A' of Fig. 1. 3 to 14 are views showing a manufacturing process of a light-emitting element according to an embodiment of the present invention. Figure 15 is a top view of a light-emitting element in accordance with another embodiment of the present invention.
10‧‧‧發光元件10‧‧‧Lighting elements
100‧‧‧基板100‧‧‧Substrate
110‧‧‧第一發光單元110‧‧‧First lighting unit
110a‧‧‧第一側壁110a‧‧‧First side wall
110b‧‧‧第二側壁110b‧‧‧second side wall
112‧‧‧第一半導體層112‧‧‧First semiconductor layer
114‧‧‧第一發光層114‧‧‧First luminescent layer
114a、164a‧‧‧上表面114a, 164a‧‧‧ upper surface
116‧‧‧第二半導體層116‧‧‧Second semiconductor layer
120‧‧‧第一凹部120‧‧‧First recess
130‧‧‧絕緣層130‧‧‧Insulation
140‧‧‧導電層140‧‧‧ Conductive layer
160‧‧‧第二發光單元160‧‧‧second lighting unit
160a‧‧‧第三側壁160a‧‧‧ third side wall
160b‧‧‧第四側壁160b‧‧‧fourth sidewall
162‧‧‧第三半導體層162‧‧‧ third semiconductor layer
164‧‧‧第二發光單元164‧‧‧second lighting unit
166‧‧‧第四半導體層166‧‧‧fourth semiconductor layer
L1、L2、L3、L4‧‧‧長度L1 , L2 , L3 , L4 ‧‧‧ length
α1、α2、α3、α4‧‧‧夾角α1 , α2 , α3 , α4 ‧‧‧ angle
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562151380P | 2015-04-22 | 2015-04-22 | |
| US62/151,380 | 2015-04-22 | ||
| US201562192054P | 2015-07-13 | 2015-07-13 | |
| US62/192,054 | 2015-07-13 |
| Publication Number | Publication Date |
|---|---|
| TW201639187Atrue TW201639187A (en) | 2016-11-01 |
| TWI699902B TWI699902B (en) | 2020-07-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW110106366ATWI776403B (en) | 2015-04-22 | 2016-04-22 | Method for manufacturing light-emitting device |
| TW105112648ATWI699902B (en) | 2015-04-22 | 2016-04-22 | Light-emitting device and method for manufacturing the same |
| TW109119921ATWI723897B (en) | 2015-04-22 | 2016-04-22 | Method for manufacturing light-emitting device |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW110106366ATWI776403B (en) | 2015-04-22 | 2016-04-22 | Method for manufacturing light-emitting device |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW109119921ATWI723897B (en) | 2015-04-22 | 2016-04-22 | Method for manufacturing light-emitting device |
| Country | Link |
|---|---|
| US (3) | US10050081B2 (en) |
| CN (3) | CN110504342A (en) |
| TW (3) | TWI776403B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9917027B2 (en)* | 2015-12-30 | 2018-03-13 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with aluminum via structures and methods for fabricating the same |
| CN107516701B (en)* | 2017-07-14 | 2019-06-11 | 华灿光电(苏州）有限公司 | A high-voltage light-emitting diode chip and its manufacturing method |
| US20200251460A1 (en)* | 2017-08-25 | 2020-08-06 | Sharp Kabushiki Kaisha | Micro-led element, image display element, and production method |
| JP6822429B2 (en) | 2018-02-19 | 2021-01-27 | 日亜化学工業株式会社 | Light emitting element |
| US11282984B2 (en)* | 2018-10-05 | 2022-03-22 | Seoul Viosys Co., Ltd. | Light emitting device |
| CN109638119A (en)* | 2018-11-30 | 2019-04-16 | 广东德力光电有限公司 | The zanjon lithographic method and high-voltage chip of high-voltage chip |
| CN111293200A (en)* | 2018-12-07 | 2020-06-16 | 大连德豪光电科技有限公司 | LED high-voltage chip, preparation method thereof and manufacturing method of isolation groove |
| CN111477647A (en) | 2019-01-24 | 2020-07-31 | 晶元光电股份有限公司 | Light emitting element and method for manufacturing the same |
| TWI673888B (en)* | 2019-02-25 | 2019-10-01 | 友達光電股份有限公司 | Manufacturing method of a light-emitting element |
| CN111293080B (en)* | 2020-02-18 | 2024-05-31 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN111969088A (en)* | 2020-08-31 | 2020-11-20 | 福建兆元光电有限公司 | Mini LED chip structure and manufacturing method thereof |
| TWI746293B (en)* | 2020-11-27 | 2021-11-11 | 錼創顯示科技股份有限公司 | Micro light-emitting diode structure and micro light-emitting diode display device using the same |
| US20230007967A1 (en)* | 2021-07-12 | 2023-01-12 | Xiamen San'an Optoelectronics Co., Ltd. | Light emitting diode device |
| US20240297283A1 (en)* | 2022-03-31 | 2024-09-05 | BOE MLED Technology Co., Ltd. | Light emitting diode chip, display substrate and display device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3874971B2 (en)* | 1999-08-30 | 2007-01-31 | ローム株式会社 | Manufacturing method of light emitting diode chip |
| US7579771B2 (en)* | 2002-04-23 | 2009-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and method of manufacturing the same |
| WO2004013916A1 (en)* | 2002-08-01 | 2004-02-12 | Nichia Corporation | Semiconductor light-emitting device, method for manufacturing same and light-emitting apparatus using same |
| JP2004079901A (en)* | 2002-08-21 | 2004-03-11 | Nec Electronics Corp | Semiconductor device and method for manufacturing the same |
| CN1492482A (en)* | 2002-10-22 | 2004-04-28 | 旺宏电子股份有限公司 | method of opening |
| CN1763979A (en)* | 2004-10-22 | 2006-04-26 | 吴裕朝 | Uniform white light emitting diode and manufacturing method thereof |
| KR100721515B1 (en)* | 2006-01-09 | 2007-05-23 | 서울옵토디바이스주식회사 | Light Emitting Diode Having ITO Layer And Manufacturing Method Thereof |
| US7507998B2 (en)* | 2006-09-29 | 2009-03-24 | Tpo Displays Corp. | System for displaying images and method for fabricating the same |
| JP2010118509A (en)* | 2008-11-13 | 2010-05-27 | Panasonic Corp | Light-emitting element |
| US8072044B2 (en)* | 2009-09-17 | 2011-12-06 | Fairchild Semiconductor Corporation | Semiconductor die containing lateral edge shapes and textures |
| KR101072034B1 (en)* | 2009-10-15 | 2011-10-10 | 엘지이노텍 주식회사 | Semiconductor light emitting device and fabrication method thereof |
| TW201143078A (en)* | 2010-05-17 | 2011-12-01 | Ubilux Optoelectronics Corp | Light emitting diode module with bridging electrode and manufacturing method thereof |
| KR101650518B1 (en)* | 2010-09-13 | 2016-08-23 | 에피스타 코포레이션 | Light-emitting structure |
| CN102092673A (en)* | 2010-12-31 | 2011-06-15 | 上海集成电路研发中心有限公司 | Method for forming slowly changed side wall of micro-electro-mechanical system (MEMS) |
| CN103000770A (en)* | 2011-09-15 | 2013-03-27 | 张庆 | New process for controlling array type high-voltage LED side-wall inclination angle |
| KR20130109319A (en)* | 2012-03-27 | 2013-10-08 | 삼성전자주식회사 | Semiconductor light emitting device, light emitting module and lighting device |
| KR101186684B1 (en)* | 2012-03-29 | 2012-09-28 | 서울옵토디바이스주식회사 | Light emitting diode and method of fabricating the same |
| TW201407747A (en)* | 2012-08-03 | 2014-02-16 | Chi Mei Lighting Tech Corp | Light-emitting diode structure and manufacturing method thereof |
| KR20140006485A (en)* | 2012-07-05 | 2014-01-16 | 삼성전자주식회사 | Semiconductor light emitting device having a multi-cell array and method for manufacturing the same |
| KR102087933B1 (en)* | 2012-11-05 | 2020-04-14 | 엘지이노텍 주식회사 | Light Emitting device and light emitting array |
| KR20140059985A (en)* | 2012-11-09 | 2014-05-19 | 엘지이노텍 주식회사 | Light emitting device |
| KR20140073351A (en) | 2012-12-06 | 2014-06-16 | 엘지이노텍 주식회사 | Light Emitting Device |
| US9093627B2 (en)* | 2012-12-21 | 2015-07-28 | Seoul Viosys Co., Ltd. | Light emitting diode and method of fabricating the same |
| CN104241455A (en)* | 2013-06-11 | 2014-12-24 | 展晶科技(深圳)有限公司 | Led chip and manufacturing method thereof |
| CN104347473A (en)* | 2013-08-05 | 2015-02-11 | 中芯国际集成电路制造(北京)有限公司 | Shallow-trench isolation structure and forming method thereof |
| Publication number | Publication date |
|---|---|
| CN110491897B (en) | 2021-04-13 |
| CN110491897A (en) | 2019-11-22 |
| TW202127681A (en) | 2021-07-16 |
| US10050081B2 (en) | 2018-08-14 |
| US20180374892A1 (en) | 2018-12-27 |
| US20200006419A1 (en) | 2020-01-02 |
| US20160343910A1 (en) | 2016-11-24 |
| US10411065B2 (en) | 2019-09-10 |
| CN106067497B (en) | 2019-09-17 |
| TWI776403B (en) | 2022-09-01 |
| CN106067497A (en) | 2016-11-02 |
| CN110504342A (en) | 2019-11-26 |
| TWI699902B (en) | 2020-07-21 |
| TWI723897B (en) | 2021-04-01 |
| TW202036929A (en) | 2020-10-01 |
| US10784307B2 (en) | 2020-09-22 |
| Publication | Publication Date | Title |
|---|---|---|
| TWI699902B (en) | Light-emitting device and method for manufacturing the same | |
| JP2024518760A (en) | Conductive oxide overhang structures for OLED devices | |
| TWI384650B (en) | Method for manufacturing light-emitting diode wafer | |
| JP6176025B2 (en) | Method for forming metal film and method for manufacturing light-emitting element | |
| CN110808318B (en) | A flip-chip high-voltage light-emitting diode and its manufacturing method | |
| TWI455361B (en) | Method for manufacturing group III nitride semiconductor light-emitting device | |
| CN105374909B (en) | A kind of manufacturing method of high-voltage LED | |
| CN108400215B (en) | A kind of light-emitting diode chip for backlight unit and preparation method thereof | |
| CN106098892A (en) | A kind of manufacture method of high pressure light-emitting diode chip | |
| WO2015141166A1 (en) | Semiconductor light-emitting device and method for manufacturing same | |
| CN110957405A (en) | A kind of LED chip and its production method | |
| CN102479898A (en) | Light emitting diode and method for fabricating the same | |
| CN100385706C (en) | Organic electroluminescence element and its manufacturing method | |
| CN118825155B (en) | Preparation method of flip LED and flip LED | |
| CN109860349A (en) | A kind of LED chip and its manufacturing method | |
| CN101877456A (en) | Manufacturing method of semiconductor light emitting element and semiconductor light emitting element | |
| US8853057B2 (en) | Method for fabricating semiconductor devices | |
| CN115602775B (en) | Flip high-voltage light-emitting diode chip and preparation method thereof | |
| KR20160064363A (en) | Light emitting device and method for manufacturing the same | |
| CN114038952A (en) | Light emitting diode chip, preparation method thereof and display device | |
| TWI872365B (en) | Light emitting device | |
| CN108231961A (en) | A kind of production method of LED chip structure | |
| CN107799635A (en) | A kind of LED chip and its manufacture method | |
| CN102208502A (en) | Method for making light emitting diode invisible electrode with gallium-nitride-based vertical structure | |
| TWI396482B (en) | Circuit substrate process and circuit substrate structure |