本發明係關於一種薄膜場效型電晶體。This invention relates to a thin film field effect transistor.
近年來，由於液晶或電致發光(Electro Luminescence：EL)技術等之進步，故而平面薄型圖像顯示裝置(Flat Panel Display：FPD)得以實用化。尤其是使用藉由通入電流被激發而發光之薄膜材料之有機電場發光元件(以下，有時記載為「有機EL元件」)可於低電壓下獲得高亮度之發光，故而於包含行動電話顯示器、個人數位助理(PDA，Personal Digital Assistant)、電腦顯示器、汽車之資訊顯示器、TV(Television，電視)監視器、或通用照明之廣泛之領域中，期待器件(device)之薄型化、輕量化、小型化、及省電等效果。In recent years, due to progress in liquid crystal or electroluminescence (EL) technology, a flat panel display device (FPD) has been put into practical use. In particular, an organic electric field light-emitting element (hereinafter sometimes referred to as an "organic EL element") which uses a thin film material which emits light by being excited to emit light can obtain high-intensity light emission at a low voltage, and thus includes a mobile phone display. In the broad field of personal digital assistants (PDAs, Personal Digital Assistants), computer monitors, automotive information displays, TV (Television) monitors, or general-purpose lighting, devices are expected to be thinner and lighter. Miniaturization, power saving and other effects.
該等FPD係藉由將設置於玻璃基板上之非晶矽薄膜或多晶矽薄膜用於活性層之薄膜場效型電晶體(於以下之說明中，有時記載為Thin Film Transistor、或TFT)之主動矩陣電路而進行驅動。The FPD is a thin film field effect transistor in which an amorphous germanium film or a polycrystalline germanium film provided on a glass substrate is used for an active layer (hereinafter, referred to as Thin Film Transistor or TFT in the following description). The active matrix circuit is driven.
另一方面，伴隨著該等FPD之多樣化、高性能化，針對電晶體誤動作之對策亦要求更嚴格之基準。例如，若為有機EL，則電流與驅動電壓之平方成比例，故而必需儘可能地抑制動作時之閾值電壓漂移。關於液晶用途，因外部光或溫度上升所導致之漏電流之抑制亦愈加嚴格。On the other hand, with the diversification and high performance of these FPDs, a more stringent benchmark is required for countermeasures against transistor malfunction. For example, in the case of an organic EL, the current is proportional to the square of the driving voltage, and therefore it is necessary to suppress the threshold voltage drift during operation as much as possible. Regarding liquid crystal applications, the suppression of leakage current due to external light or temperature rise is becoming more stringent.
因此，積極地開發將對該等誤動作較強之寬能隙之非晶氧化物，例如In-Ga-Zn-O系非晶氧化物的半導體薄膜用於活性層之TFT(例如，參照專利文獻1、非專利文獻1)。近年來，作為進而遷移率較高之氧化物半導體材料，提出有富In(銦)之IGZO(Indium Gallium Zinc Oxide，氧化銦鎵鋅)、ITZO(Indium Tin Zinc Oxide，氧化銦錫鋅)、及結晶材料之IGO(Indium Gallium Oxide，氧化銦鎵)等(例如，參照專利文獻2、非專利文獻2及3)。Therefore, an amorphous oxide having a wide energy gap which is strongly erroneous, such as a semiconductor film of an In-Ga-Zn-O-based amorphous oxide, is actively developed for the TFT of the active layer (for example)For example, refer to Patent Document 1 and Non-Patent Document 1). In recent years, as an oxide semiconductor material having a higher mobility, an Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), and IGO (Indium Gallium Oxide) of a crystalline material (for example, refer to Patent Document 2, Non-Patent Documents 2 and 3).
然而，若欲提高氧化物半導體之遷移率，則帶隙較窄之In2O3之濃度增多，故而有斷態電流上升，或藉由光照射等而產生光載子(photocarrier)，導致閥值電壓漂移(Vt漂移)之情況。為了防止此種情況，若僅積層SiO2等保護膜，則不能成為對策。作為相對有效之方法，揭示有將通道設為2層之方法(專利文獻3)。例如有以下等技術：藉由在活性層之後通道側積層包含帶隙較寬之氧化物半導體之電阻層，雖犧牲遷移率但減少閾值電壓漂移。可認為，寬能隙之氧化物半導體比SiO2更適合作為電阻層之原因在於，其與活性層之折射率之差較小，可抑制因雜散光所導致之光傳導(photoconduction)。又，由於不存在帶隙之大小亦極端不同之情況，故而認為於接合界面、即活性層與電阻層之界面不易積存導致誤動作之阱。反之，若電阻層使用SiO2等寬能隙之絕緣體，則產生折射階差，故而於通道部分封入來自橫向之雜散光，變得容易導致因斷態電流之增加或閾值電壓漂移等所引起之誤動作。又，於活性層與電阻層之界面變得容易累積阱，同樣地變得容易導致誤動作。However, if the mobility of the oxide semiconductor is to be increased, the concentration of In2 O3 having a narrow band gap is increased, so that the off-state current is increased, or a photocarrier is generated by light irradiation or the like, resulting in a valve. The case of value voltage drift (Vt drift). In order to prevent this, if only a protective film such as SiO2 is laminated, it cannot be a countermeasure. As a relatively effective method, a method of setting the channel to two layers has been disclosed (Patent Document 3). For example, there is a technique in which a resistive layer containing a wide band gap oxide semiconductor is formed on the channel side after the active layer, while sacrificing mobility but reducing threshold voltage drift. It is considered that the reason why the oxide semiconductor having a wide band gap is more suitable as the resistance layer than SiO2 is that the difference in refractive index from the active layer is small, and photoconduction due to stray light can be suppressed. Further, since the size of the band gap is not extremely different, it is considered that the joint interface, that is, the interface between the active layer and the resistance layer is less likely to accumulate in the well which causes malfunction. On the other hand, if the resistive layer uses an insulator having a wide energy gap such as SiO2 , a refractive gradient is generated, so that stray light from the lateral direction is sealed in the channel portion, which is liable to cause an increase in off-state current or a threshold voltage drift. Malfunction. Further, it is easy to accumulate the well at the interface between the active layer and the resistance layer, and similarly, it is easy to cause malfunction.
另外，將寬能隙之氧化物半導體積層於後通道側之技術由於與絕緣膜側之通道相比高電阻之情形較多，故而有容易產生與源極/汲極電極之接觸電阻之課題。於電阻膜與源極/汲極電極之接觸電阻較大之情形時，導致輸出電流之降低，尤其是有機EL或高精細液晶之驅動容易成為問題。Further, the technique of laminating the oxide semiconductor having a wide band gap on the rear channel side is often caused by a high resistance compared with the channel on the insulating film side, so that the contact resistance with the source/drain electrode is likely to occur. When the contact resistance between the resistive film and the source/drain electrodes is large, the output current is lowered, and especially the driving of the organic EL or the high-definition liquid crystal is liable to be a problem.
又，以提高可靠性為目的而將通道製成積層構造之技術報告於專利文獻1及3~5等中。然而，於將該技術用於例如顯示裝置之驅動電路之情形時，有因源極/汲極電極與製成積層構造之通道之接觸電阻，而無法獲得所設計之遷移率之情況。為了解決該問題，對積層構造通道之高電阻層側進行蝕刻，以源極/汲極電極與低電阻層直接接觸之方式進行加工即可，但產生蝕刻液或蝕刻氣體亦會腐蝕低電阻層側之課題。Moreover, the technique of forming a channel into a laminated structure for the purpose of improving reliability is reported.Patent Documents 1 and 3 to 5, and the like. However, when this technique is applied to, for example, a driving circuit of a display device, there is a case where the designed mobility is not obtained due to the contact resistance of the source/drain electrode and the channel in which the build-up structure is formed. In order to solve this problem, the high resistance layer side of the laminated structure channel is etched, and the source/drain electrode is directly contacted with the low resistance layer, but the etching solution or the etching gas may also corrode the low resistance layer. The subject of the side.
專利文獻1：日本專利特開2006-165529號公報Patent Document 1: Japanese Patent Laid-Open Publication No. 2006-165529
專利文獻2：日本專利特開2010-45263號公報Patent Document 2: Japanese Patent Laid-Open Publication No. 2010-45263
專利文獻3：日本專利特開2012-59860號公報Patent Document 3: Japanese Patent Laid-Open Publication No. 2012-59860
專利文獻4：日本專利特開2010-73881號公報Patent Document 4: Japanese Patent Laid-Open Publication No. 2010-73881
專利文獻5：日本專利特開2010-21555號公報Patent Document 5: Japanese Patent Laid-Open Publication No. 2010-21555
非專利文獻1：IDW/AD' 05，845頁-846頁(6 December, 2005)Non-Patent Document 1: IDW/AD' 05, 845-846 (6 December, 2005)
非專利文獻2：Appl. Phys. Express, 5(2012)011102Non-Patent Document 2: Appl. Phys. Express, 5(2012)011102
非專利文獻3：Jpn. J. Appl. Phys, 51(2012)03CB01Non-Patent Document 3: Jpn. J. Appl. Phys, 51 (2012) 03CB01
本發明之目的在於提供一種場效遷移率較高、可靠性較高之薄膜場效型電晶體。It is an object of the present invention to provide a thin film field effect transistor having high field effect mobility and high reliability.
本發明者等人為了使用高遷移率之通道提高可靠性而努力探索以下方法：藉由使用閾值電壓漂移經抑制之氧化物半導體，即便積層電阻層，亦可減少與源極/汲極電極之接觸電阻。結果發現，藉由在基板上至少包含閘極電極、閘極絕緣膜、活性層、電阻層、源極電極及汲極電極，且上述活性層以直接連接於上述電阻層、源極電極及汲極電極之方式構成之薄膜場效型電晶體，可解決上述課題，從而完成本發明。The inventors of the present invention have tried to find a method for improving the reliability by using a channel having a high mobility: by using a threshold voltage to drift the suppressed oxide semiconductor, even if the resistive layer is laminated, the source/drain electrode can be reduced. Contact resistance. As a result, it has been found that at least the gate electrode, the gate insulating film, the active layer, the resistive layer, the source electrode, and the drain electrode are included on the substrate, and the active layer is directly connected to the resistive layer, the source electrode, and the gate electrode. A thin film field effect type transistor composed of a pole electrode can solve the above problems and completethis invention.
又，亦發現，本發明由於可利用選擇蝕刻性，故而不會增加光罩之步驟數，因此生產性較高。Further, it has been found that the present invention can utilize the selective etching property, so that the number of steps of the photomask is not increased, so that the productivity is high.
根據本發明，可提供以下之薄膜場效型電晶體、其製造方法、及使用其之電子機器。According to the present invention, the following thin film field effect type transistor, a method of manufacturing the same, and an electronic apparatus using the same can be provided.
1.一種薄膜場效型電晶體，其特徵在於：於基板上至少包含閘極電極、閘極絕緣膜、活性層、電阻層、源極電極及汲極電極，上述源極電極及上述汲極電極經由設置於上述電阻層之接觸孔而與上述活性層電性連接，並且上述活性層與上述電阻層之折射率之差為0.3以下，且上述電阻層之膜厚為5nm以上且300nm以下。A thin film field effect type transistor, comprising: a gate electrode, a gate insulating film, an active layer, a resistance layer, a source electrode, and a drain electrode on the substrate, the source electrode and the drain electrode The electrode is electrically connected to the active layer via a contact hole provided in the resistance layer, and a difference in refractive index between the active layer and the resistive layer is 0.3 or less, and a thickness of the resistive layer is 5 nm or more and 300 nm or less.
2.如1之薄膜場效型電晶體，其中上述活性層及上述電阻層含有包含選自由In、Zn、Ga、Sn、Al、Zr、Hf、Mg及Y所組成之群中之至少1種之氧化物。2. The thin film field effect transistor according to 1, wherein said active layer and said resistance layer contain at least one selected from the group consisting of In, Zn, Ga, Sn, Al, Zr, Hf, Mg, and Y. Oxide.
3.如1或2之薄膜場效型電晶體，其中上述活性層之電阻低於上述電阻層之電阻。3. The thin film field effect transistor according to 1 or 2, wherein the resistance of the active layer is lower than the resistance of the resistive layer.
4.如1至3中任一項之薄膜場效型電晶體，其中上述電阻層之氧化物為非晶氧化物。4. The thin film field effect transistor according to any one of 1 to 3, wherein the oxide of the above resistance layer is an amorphous oxide.
5.如1至4中任一項之薄膜場效型電晶體，其中上述活性層之氧化物為非晶氧化物。5. The thin film field effect transistor according to any one of 1 to 4, wherein the oxide of the active layer is an amorphous oxide.
6.如1至5中任一項之薄膜場效型電晶體，其進而包含接觸於上述電阻層之層間絕緣膜。6. The thin film field effect transistor according to any one of 1 to 5, which further comprises an interlayer insulating film which is in contact with the above-mentioned resistance layer.
7.如1至6中任一項之薄膜場效型電晶體，其中上述活性層之膜厚為5nm以上且300nm以下。7. The thin film field effect transistor according to any one of 1 to 6, wherein the active layer has a film thickness of 5 nm or more and 300 nm or less.
8.一種薄膜場效型電晶體之製造方法，其特徵在於：其係如6或7之薄膜場效型電晶體之製造方法，且以相同之曝光步驟形成貫通上述層間絕緣膜與上述電阻層之接觸孔。A method for producing a thin film field effect type transistor, which is characterized in that it is a method for manufacturing a thin film field effect type transistor such as 6 or 7, and is formed through the interlayer insulating film and the above resistance layer by the same exposure step. ConnectTouch hole.
9.一種電子機器，其特徵在於包含如1至7中任一項之薄膜場效型電晶體。An electronic machine characterized by comprising the thin film field effect type transistor according to any one of 1 to 7.
根據本發明，可提供一種場效遷移率較高、可靠性較高之薄膜場效型電晶體。According to the present invention, a thin film field effect type transistor having high field effect mobility and high reliability can be provided.
1‧‧‧薄膜場效型電晶體1‧‧‧Thin field effect transistor
2‧‧‧薄膜場效型電晶體2‧‧‧Thin field field effect transistor
3‧‧‧薄膜場效型電晶體3‧‧‧Thin field effect transistor
10‧‧‧玻璃基板10‧‧‧ glass substrate
20‧‧‧閘極電極20‧‧‧gate electrode
30‧‧‧閘極絕緣膜30‧‧‧gate insulating film
40‧‧‧活性層(半導體層)40‧‧‧active layer (semiconductor layer)
50‧‧‧電阻膜50‧‧‧Resistive film
60‧‧‧層間絕緣膜60‧‧‧Interlayer insulating film
62‧‧‧第1接觸孔62‧‧‧1st contact hole
70‧‧‧源極電極70‧‧‧Source electrode
72‧‧‧汲極電極72‧‧‧汲electrode
80‧‧‧保護膜80‧‧‧Protective film
82‧‧‧第2接觸孔82‧‧‧2nd contact hole
110‧‧‧基板110‧‧‧Substrate
120‧‧‧閘極電極120‧‧‧gate electrode
130‧‧‧閘極絕緣膜130‧‧‧gate insulating film
140‧‧‧通道層(半導體層)140‧‧‧channel layer (semiconductor layer)
150‧‧‧電阻層150‧‧‧resistance layer
160‧‧‧層間絕緣膜160‧‧‧Interlayer insulating film
170‧‧‧源極電極170‧‧‧Source electrode
172‧‧‧汲極電極172‧‧‧汲electrode
180‧‧‧保護膜180‧‧‧Protective film
182‧‧‧第2接觸孔182‧‧‧2nd contact hole
210‧‧‧基板210‧‧‧Substrate
220‧‧‧閘極電極220‧‧‧gate electrode
230‧‧‧閘極絕緣膜230‧‧‧gate insulating film
240‧‧‧通道層(半導體層)240‧‧‧channel layer (semiconductor layer)
250‧‧‧電阻層250‧‧‧resistance layer
252‧‧‧光阻劑252‧‧‧ photoresist
260‧‧‧層間絕緣膜260‧‧‧Interlayer insulating film
270‧‧‧源極電極270‧‧‧ source electrode
272‧‧‧汲極電極272‧‧‧汲electrode
280‧‧‧保護膜280‧‧‧Protective film
282‧‧‧接觸孔282‧‧‧Contact hole
圖1a係本發明之薄膜場效型電晶體製造之一步驟圖。Figure 1a is a step diagram of the fabrication of a thin film field effect transistor of the present invention.
圖1b係本發明之薄膜場效型電晶體製造之一步驟圖。Figure 1b is a step diagram of the fabrication of a thin film field effect transistor of the present invention.
圖1c係本發明之薄膜場效型電晶體製造之一步驟圖。Figure 1c is a step diagram of the fabrication of a thin film field effect transistor of the present invention.
圖1d係本發明之薄膜場效型電晶體製造之一步驟圖。Figure 1d is a step diagram of the fabrication of a thin film field effect transistor of the present invention.
圖1e係本發明之薄膜場效型電晶體製造之一步驟圖。Figure 1e is a step diagram of the fabrication of the thin film field effect transistor of the present invention.
圖1f係表示本發明之薄膜場效型電晶體之一實施形態之模式圖。Fig. 1f is a schematic view showing an embodiment of a thin film field effect transistor of the present invention.
圖2a係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 2a is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖2b係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 2b is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖2c係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 2c is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖2d係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 2d is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖2e係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 2e is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖2f係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 2f is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖2g係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 2g is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3a係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3a is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3b係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3b is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3c係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3c is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3d係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3d is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3e係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3e is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3f係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3f is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3g係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3g is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3h係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Fig. 3h is a step diagram showing a method of manufacturing another thin film field effect type transistor.
圖3i係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3i is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3j係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3j is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3k係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 3k is a step diagram of a method of fabricating another aspect of a thin film field effect transistor.
圖3l係另一態樣之薄膜場效型電晶體之製造方法之一步驟圖。Figure 31 is a step diagram showing a method of fabricating another aspect of the thin film field effect transistor.
本發明之薄膜場效型電晶體之特徵在於：至少包含閘極電極、閘極絕緣膜、活性層、電阻層、源極電極及汲極電極，上述源極電極及上述汲極電極經由設置於上述電阻層之接觸孔而與上述活性層電性連接，並且上述活性層與上述電阻層之折射率之差為0.3以下，且上述電阻層之膜厚為5nm以上且300nm以下。The thin film field effect transistor of the present invention is characterized in that it comprises at least a gate electrode, a gate insulating film, an active layer, a resistance layer, a source electrode and a drain electrode, and the source electrode and the drain electrode are disposed via The contact hole of the resistive layer is electrically connected to the active layer, and a difference in refractive index between the active layer and the resistive layer is 0.3 or less, and a thickness of the resistive layer is 5 nm or more and 300 nm or less.
其次，使用圖式詳細地說明本發明之薄膜場效型電晶體之構造。Next, the configuration of the thin film field effect type transistor of the present invention will be described in detail using the drawings.
圖1a~圖1f係表示本發明之薄膜場效型電晶體1之製造順序之圖，且為表示逆交錯構造之一例之模式圖。於玻璃基板10上積層閘極電極20，使用光處理(photoprocess)進行蝕刻(圖1a)。其次，利用PE-CVD(Plasma Enhanced-Chemical Vapor Deposition，電漿增強化學氣相沈積法)等堆積閘極絕緣膜30。其次，使用濺鍍等方法依序堆積活性層(半導體層)40、電阻膜50。繼而，使用第2次之光微影進行圖案化(圖1b)。1a to 1f are views showing a manufacturing sequence of the thin film field effect transistor 1 of the present invention, and are schematic views showing an example of an inverse staggered structure. The gate electrode 20 is laminated on the glass substrate 10 and etched using photoprocess (Fig. 1a). Next, the gate insulating film 30 is deposited by PE-CVD (Plasma Enhanced-Chemical Vapor Deposition) or the like. Next, the active layer (semiconductor layer) 40 and the resistive film 50 are sequentially deposited by a method such as sputtering. Then, patterning was performed using the second light lithography (Fig. 1b).
然後，利用CVD(Chemical Vapor Deposition，化學氣相沈積法)等在其上成膜SiO2等層間絕緣膜60作為蝕刻終止膜(圖1c)。其次，藉由第3次之光微影製程，而於層間絕緣膜60貫通第1接觸孔。繼而，藉由再次變更藥液或氣體而於電阻層亦貫通第1接觸孔62(圖1d)。可利用相同之曝光步驟形成貫通層間絕緣膜與電阻層之接觸孔。Then, an interlayer insulating film 60 such as SiO2 is formed thereon by CVD (Chemical Vapor Deposition) or the like as an etching stopper film (FIG. 1c). Next, the interlayer insulating film 60 penetrates the first contact hole by the third photolithography process. Then, the first contact hole 62 is also penetrated in the resistance layer by changing the chemical liquid or the gas again (Fig. 1d). The contact hole penetrating the interlayer insulating film and the resistance layer can be formed by the same exposure step.
其次，將電極進行濺鍍成膜後，利用第4次之光微影製程圖案化為源極/汲極電極70、72之形狀(圖1e)。最後，利用CVD等堆積SiO2作為保護膜80後，藉由第5次之光微影製程而貫通第2接觸孔82，從而完成本發明之薄膜場效型電晶體。Next, after the electrode was sputter-deposited, the electrode was patterned into the shape of the source/drain electrodes 70 and 72 by the fourth photolithography process (Fig. 1e). Finally, SiO2 is deposited as a protective film 80 by CVD or the like, and then through the second contact hole 82 by the fifth photolithography process, the thin film field effect transistor of the present invention is completed.
再者，於上述之例中，雖然設置有層間絕緣膜，但亦可不設置層間絕緣膜。於該情形時，僅於電阻層設置第1接觸孔而使源極/汲極電極與活性層電性連接。Further, in the above example, although the interlayer insulating film is provided, the interlayer insulating film may not be provided. In this case, the first contact hole is provided only in the resistance layer, and the source/drain electrode is electrically connected to the active layer.
如上所述，本發明之薄膜場效型電晶體之製造方法之特徵在於：利用相同之曝光步驟形成貫通上述層間絕緣膜與上述電阻層之接觸孔。As described above, the method for producing a thin film field effect transistor of the present invention is characterized in that a contact hole penetrating the interlayer insulating film and the resistive layer is formed by the same exposure step.
本發明之製造方法之特徵在於：利用電阻層(高電阻膜)與活性層(低電阻膜)之選擇蝕刻性。於其一實施形態中，利用相同之光處理加工電阻層與層間絕緣膜，並由相同之貫通孔而形成，藉此可不增加光罩之步驟數而兼具電晶體之高遷移率與高可靠性。The manufacturing method of the present invention is characterized by selective etching property of a resistive layer (high-resistance film) and an active layer (low-resistance film). In one embodiment, the resistive layer and the interlayer insulating film are processed by the same light treatment and formed by the same through holes, thereby achieving high mobility and high reliability of the transistor without increasing the number of steps of the mask. Sex.
於本發明之薄膜場效型電晶體之活性層及電阻層中，較佳為使用氧化物半導體。作為電阻層與活性層，可使用不同材料，更佳為使用可藉由分別不同之蝕刻液或蝕刻氣體而圖案化之材料之組合，即、使用於電阻層與活性層之間可進行選擇蝕刻之材料之組合。In the active layer and the resistance layer of the thin film field effect transistor of the present invention, an oxide semiconductor is preferably used. As the resistive layer and the active layer, different materials may be used, and it is more preferable to use a combination of materials which can be patterned by using different etching liquids or etching gases, that is, selective etching between the resistive layer and the active layer. a combination of materials.
本發明中之活性層與電阻層較佳為分別含有包含選自由In、Zn、Ga、Sn、Al、Zr、Hf、Mg及Y所組成之群中之至少1種之氧化物，較佳為含有包含選自由In、Zn、Ga、Sn及Al所組成之群中之至少1種之氧化物。又，亦可僅包含該氧化物。The active layer and the resistive layer in the present invention preferably each contain at least one oxide selected from the group consisting of In, Zn, Ga, Sn, Al, Zr, Hf, Mg, and Y, and preferably It contains an oxide containing at least one selected from the group consisting of In, Zn, Ga, Sn, and Al. Further, it is also possible to include only the oxide.
於使用下述者作為蝕刻液之情形時，將如能溶解電阻層且不溶解活性層之電阻層與活性層之組合示於以下。In the case where the following is used as the etching liquid, the combination of the resistance layer and the active layer which dissolve the resistance layer and does not dissolve the active layer is shown below.
於PAN(磷酸、乙酸及硝酸之混合酸)之情形時，可列舉：電阻層/活性層=IGZO/ITZO、IGZO/結晶IGO、及IGZO/ITAO(Indium Tin Aluminum Oxide，氧化銦錫鋁)等。於草酸或稀氫氟酸之情形時，可列舉：電阻層/活性層=Ga2O3/結晶IGO等。In the case of PAN (a mixed acid of phosphoric acid, acetic acid, and nitric acid), a resistive layer/active layer = IGZO/ITZO, IGZO/crystalline IGO, and IGZO/ITAO (Indium Tin Aluminum Oxide) may be mentioned. . In the case of oxalic acid or dilute hydrofluoric acid, a resistive layer/active layer = Ga2 O3 /crystalline IGO or the like can be mentioned.
又，於乾式蝕刻之情形時，於使用作為氯系氣體之BCl3系時，可列舉：電阻層/活性層=ZrO2/ITZO、Ga2O3/ITZO等。於CH4之情形時，可列舉：電阻層/活性層=IGZO/結晶IGO等。Further, in the case of dry etching, when a BCl3 system which is a chlorine-based gas is used, a resistive layer/active layer = ZrO2 /ITZO, Ga2 O3 /ITZO or the like can be mentioned. In the case of CH4 , a resistive layer/active layer = IGZO/crystalline IGO or the like can be mentioned.
再者，IGZO意指包含In、Ga及Zn之氧化物，ITZO意指包含In、Sn及Zn之氧化物，IGO意指包含In及Ga之氧化物，ITAO意指包含In、Sn及Al之氧化物。Further, IGZO means an oxide containing In, Ga, and Zn, ITZO means an oxide containing In, Sn, and Zn, IGO means an oxide containing In and Ga, and ITAO means including In, Sn, and Al. Oxide.
雖然電阻層與活性層之蝕刻速度之差異越大越好，但只要至少電阻層之蝕刻速度快於活性層之蝕刻速度即可。Although the difference in etching speed between the resistive layer and the active layer is as large as possible, at least the etching rate of the resistive layer is faster than the etching rate of the active layer.
於本發明中，由於電阻層不對源極/汲極電極與活性層之電性連接產生影響，故而電阻層之膜厚無需如先前般設計得較薄。然而，作為帶來動作可靠性之效果所必需之最低限之膜厚，較佳為5nm以上，更佳為10nm以上。又，若超出需要地積層得較厚，則藉由應力而對電晶體之動作特性或壽命造成不良影響，故而較佳為300nm以下，更佳為200nm以下。In the present invention, since the resistive layer does not affect the electrical connection between the source/drain electrodes and the active layer, the film thickness of the resistive layer does not need to be designed to be thin as before. However, the film thickness which is the minimum necessary for the effect of the operational reliability is preferably 5 nm or more, and more preferably 10 nm or more. Moreover, if it is thicker than necessary, it will adversely affect the operational characteristics and life of the transistor by stress, and therefore it is preferably 300 nm or less, more preferably 200 nm or less.
活性層之膜厚適宜選擇即可，較佳為5nm以上且300nm以下，更佳為20nm以上且200nm以下。The film thickness of the active layer may be appropriately selected, and is preferably 5 nm or more and 300 nm or less, more preferably 20 nm or more and 200 nm or less.
若活性層與電阻層之折射率之差較大，則於界面產生光之反射。該情況於照射到光之製品中容易成為問題，故而活性層與電阻層之折射率之差較佳為0.3以內，更佳為0.2以內。If the difference in refractive index between the active layer and the resistive layer is large, light reflection occurs at the interface. This is a problem in the article irradiated with light, and therefore the difference in refractive index between the active layer and the resistive layer is preferably within 0.3, more preferably within 0.2.
活性層與電阻層之折射率係使用光學式之測定系統進行測定。於本實施例中，準備使活性層與電阻層之各自於玻璃上成膜100nm左右而成之單膜，利用光學式薄膜測定系統(Ya-man公司之FilmTek)進行測定。The refractive indices of the active layer and the resistive layer were measured using an optical measurement system.In the present embodiment, a single film in which each of the active layer and the resistive layer was formed on the glass to a thickness of about 100 nm was prepared and measured by an optical film measuring system (FilmTek of Yaman Co., Ltd.).
電阻層較佳為電阻高於活性層。於電阻層之電阻低於活性層之情形時，有Off(斷態)電流變大而對消耗電力造成問題之情況。The resistive layer preferably has a higher electrical resistance than the active layer. When the resistance of the resistance layer is lower than that of the active layer, there is a case where the Off (off-state) current becomes large and the power consumption is caused.
電阻之測定方法係如實施例中所記載。The method of measuring the electrical resistance is as described in the examples.
藉由使用上述活性層及電阻層，可實現遷移率較高、顯示高ON/OFF比、且閾值電壓之漂移較小之優異之電晶體特性。By using the active layer and the resistive layer described above, it is possible to realize an excellent transistor characteristic in which the mobility is high, the ON/OFF ratio is high, and the threshold voltage drift is small.
作為活性層及電阻層之成膜方法，較佳為以氧化物半導體之多晶燒結體作為靶材而使用氣相成膜法。於氣相成膜法中，適用濺鍍法及脈衝雷射蒸鍍法(PLD(Pulsed Laser Deposition)法)。進而，就量產性之觀點而言，較佳為濺鍍法。As a film forming method of the active layer and the resistive layer, it is preferable to use a vapor phase film forming method using a polycrystalline sintered body of an oxide semiconductor as a target. In the vapor phase film formation method, a sputtering method and a pulsed laser deposition method (PLD (Pulsed Laser Deposition) method) are applied. Further, from the viewpoint of mass productivity, a sputtering method is preferred.
作為層間絕緣膜之材料，可列舉：SiO2、SiNx、SiON等絕緣體。層間絕緣膜之膜厚較佳為10~300nm，更佳為20~200nm。層間絕緣膜之成膜法並無特別限定，可藉由電漿CVD、TECS-CVD(Triethylchlorosilane-Chemical Vapor Deposition，三乙基氯矽烷化學氣相沈積法)、濺鍍法等而進行成膜。Examples of the material of the interlayer insulating film include insulators such as SiO2 , SiNx, and SiON. The film thickness of the interlayer insulating film is preferably from 10 to 300 nm, more preferably from 20 to 200 nm. The film formation method of the interlayer insulating film is not particularly limited, and film formation can be performed by plasma CVD, TECS-CVD (Triethylchlorosilane-Chemical Vapor Deposition), sputtering, or the like.
作為閘極絕緣膜之材料，可使用：SiO2、SiNx、SiON、Al2O3、Y2O3、Ta2O5、HfO2等絕緣體、或包含至少2種以上該等化合物之混合物。又，亦可使用如聚醯亞胺之高分子絕緣體作為閘極絕緣膜。As a material of the gate insulating film, an insulator such as SiO2 , SiNx, SiON, Al2 O3 , Y2 O3 , Ta2 O5 or HfO2 or a mixture containing at least two or more of these compounds can be used. Further, a polymer insulator such as polyimide may be used as the gate insulating film.
作為閘極絕緣膜之膜厚，較佳為10nm~10μm。The film thickness of the gate insulating film is preferably 10 nm to 10 μm.
為了減少漏電流或提高耐電壓性，閘極絕緣膜必須厚至某種程度。然而，若過厚，則有導致TFT之驅動電壓上升之虞。因此，關於閘極絕緣膜之膜厚，若為無機絕緣體，則更佳為設為50nm~1000nm，若為高分子絕緣體，則更佳為設為0.5μm~5μm。In order to reduce leakage current or improve withstand voltage, the gate insulating film must be thick to some extent.degree. However, if it is too thick, there is a fear that the driving voltage of the TFT rises. Therefore, the film thickness of the gate insulating film is preferably 50 nm to 1000 nm in the case of an inorganic insulator, and more preferably 0.5 μm to 5 μm in the case of a polymer insulator.
尤其是若使用如HfO2之高介電常數絕緣體作為閘極絕緣膜，則即便使膜厚較厚，亦可實現低電壓下之TFT驅動，故而尤佳。In particular, when a high dielectric constant insulator such as HfO2 is used as the gate insulating film, it is particularly preferable to realize TFT driving at a low voltage even if the film thickness is made thick.
作為閘極電極之材料，例如可列舉：Al、Mo、Cr、Ta、Ti、Au、或Ag等金屬、Al-Nd、APC等合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO，Indium Tin Oxide)、氧化鋅銦(IZO，Indium Zinc Oxide)等金屬氧化物導電膜、聚苯胺、聚噻吩、聚吡咯等有機導電性化合物、或該等之混合物。Examples of the material of the gate electrode include a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, an alloy such as Al-Nd or APC, tin oxide, zinc oxide, indium oxide, or indium tin oxide (ITO). , Indium Tin Oxide), a metal oxide conductive film such as indium zinc oxide (IZO, Indium Zinc Oxide), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
閘極電極之厚度較佳為設為10nm以上且1000nm以下。The thickness of the gate electrode is preferably set to 10 nm or more and 1000 nm or less.
閘極電極之成膜法並無特別限定，可考慮與上述材料之適合性而由印刷方式、塗佈方式等濕式方式、真空蒸鍍法、濺鍍法、離子鍍著法等物理方式、CVD、電漿CVD法等化學方式等適宜選擇，而將閘極電極形成於基板上。The film formation method of the gate electrode is not particularly limited, and may be a physical method such as a wet method such as a printing method or a coating method, a vacuum vapor deposition method, a sputtering method, or an ion plating method, in consideration of suitability for the above materials. A chemical method such as CVD or plasma CVD is suitably selected, and a gate electrode is formed on the substrate.
例如，於選擇ITO之情形時，可藉由直流或高頻濺鍍法、真空蒸鍍法、離子鍍著法等而進行。又，於選擇有機導電性化合物之情形時，可藉由濕式製膜法而進行。For example, in the case of selecting ITO, it can be carried out by a direct current or high frequency sputtering method, a vacuum evaporation method, an ion plating method, or the like. Further, in the case of selecting an organic conductive compound, it can be carried out by a wet film formation method.
作為源極電極及汲極電極之材料，例如可列舉：Al、Mo、Cr、Ta、Ti、Au、或Ag等金屬、Al-Nd、APC等合金、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等金屬氧化物導電膜、聚苯胺、聚噻吩、聚吡咯等有機導電性化合物、或該等之混合物。Examples of the material of the source electrode and the drain electrode include a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, an alloy such as Al-Nd or APC, tin oxide, zinc oxide, indium oxide, or oxidation. A metal oxide conductive film such as indium tin oxide (ITO) or zinc indium oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
源極電極及汲極電極之厚度較佳為分別設為10nm以上且1000nm以下。The thickness of the source electrode and the drain electrode is preferably 10 nm or more and 1000 nm or less.
源極電極及汲極電極之製膜法並無特別限定，可考慮與上述材料之適合性而由印刷方式、塗佈方式等濕式方式、真空蒸鍍法、濺鍍法、離子鍍著法等物理方式、CVD、電漿CVD法等化學方式等適宜選擇，而形成於基板上。The film forming method of the source electrode and the drain electrode is not particularly limited, and may be a wet method such as a printing method or a coating method, a vacuum deposition method, a sputtering method, or an ion plating method in consideration of suitability for the above materials. A chemical method such as a physical method, a CVD method, or a plasma CVD method is suitably selected and formed on a substrate.
例如於選擇ITO之情形時，可藉由直流或高頻濺鍍法、真空蒸鍍法、離子鍍著法等而進行。又，於選擇有機導電性化合物之情形時，可藉由濕式製膜法而進行。For example, when ITO is selected, it can be carried out by a direct current or high frequency sputtering method, a vacuum evaporation method, an ion plating method, or the like. Further, in the case of selecting an organic conductive compound, it can be carried out by a wet film formation method.
基板並無特別限定，例如可列舉：YSZ(yttrium stabilized zirconia，釔穩定氧化鋯)、玻璃等無機材料、聚對苯二甲酸乙二酯、聚對苯二甲酸丁二酯、聚萘二甲酸乙二酯等聚酯、聚苯乙烯、聚碳酸酯、聚醚碸、聚芳酯、烯丙基二乙二醇碳酸酯、聚醯亞胺、聚環烯烴、降烯樹脂、聚(氯三氟乙烯)等合成樹脂等有機材料等。於上述有機材料之情形時，較佳為耐熱性、尺寸穩定性、耐溶劑性、電氣絕緣性、加工性、低透氣性、或低吸濕性等優異。The substrate is not particularly limited, and examples thereof include YSZ (yttrium stabilized zirconia), inorganic materials such as glass, polyethylene terephthalate, polybutylene terephthalate, and polyethylene naphthalate B. Polyesters such as diesters, polystyrene, polycarbonate, polyether oxime, polyarylate, allyl diethylene glycol carbonate, polyimine, polycycloolefin, lower An organic material such as a synthetic resin such as an olefin resin or a poly(chlorotrifluoroethylene). In the case of the above organic material, it is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulating properties, workability, low gas permeability, or low moisture absorption.
又，作為基板，亦可較佳地使用可撓性基板。作為用於可撓性基板之材料，較佳為透過率較高之有機塑膠膜，例如可使用：聚對苯二甲酸乙二酯、聚鄰苯二甲酸丁二酯、聚萘二甲酸乙二酯等聚酯、聚苯乙烯、聚碳酸酯、聚醚碸、聚芳酯、聚醯亞胺、聚環烯烴、降烯樹脂、聚(氯三氟乙烯)等塑膠膜。又，膜狀塑膠基板於絕緣性不充分之情形時，亦較佳為包含絕緣層、用以防止水分或氧氣之透過之阻氣層、以及用以提高膜狀塑膠基板之平坦性或與電極或活性層之密接性之底塗層等。Further, as the substrate, a flexible substrate can also be preferably used. As a material for the flexible substrate, an organic plastic film having a high transmittance is preferably used, for example, polyethylene terephthalate, polybutylene phthalate, and polyethylene naphthalate. Ester and other polyesters, polystyrene, polycarbonate, polyether oxime, polyarylate, polyimine, polycycloolefin, drop Plastic film such as olefin resin or poly(chlorotrifluoroethylene). Further, in the case where the insulating film is insufficient in insulation, it is preferably an insulating layer, a gas barrier layer for preventing the permeation of moisture or oxygen, and an electrode for improving the flatness or the electrode of the film-shaped plastic substrate. Or an undercoat layer of an adhesive layer of an active layer or the like.
可撓性基板之厚度較佳為設為50μm以上且500μm以下。其原因在於：於將可撓性基板之厚度設為未達50μm之情形時，難以使基板本身保持充分之平坦性。又，於將可撓性基板之厚度設為厚於500μm之情形時，難以使基板本身自由地彎曲、即欠缺基板本身之可撓性。The thickness of the flexible substrate is preferably 50 μm or more and 500 μm or less. This is because when the thickness of the flexible substrate is less than 50 μm, it is difficult to maintain sufficient flatness of the substrate itself. Moreover, the thickness of the flexible substrate is set to be thicker than 500 μm.In this case, it is difficult to freely bend the substrate itself, that is, the flexibility of the substrate itself.
亦可視需要於TFT上設置保護絕緣膜。設置保護絕緣膜之目的在於：保護活性層或電阻層之半導體層以免其因大氣而劣化，或使於TFT上所製作之電子器件絕緣。A protective insulating film may also be provided on the TFT as needed. The purpose of providing the protective insulating film is to protect the semiconductor layer of the active layer or the resistive layer from being deteriorated by the atmosphere or to insulate the electronic device fabricated on the TFT.
作為保護絕緣膜之具體例，可列舉：MgO、SiO、SiO2、Al2O3、GeO、NiO、CaO、BaO、Fe2O3、Y2O3、或TiO2等金屬氧化物、SiNx、SiNxOy等金屬氮化物、MgF2、LiF、AlF3、或CaF2等金屬氟化物、聚乙烯、聚丙烯、聚甲基丙烯酸甲酯、聚醯亞胺、聚脲、聚四氟乙烯、聚氯三氟乙烯、聚二氯二氟乙烯、氯三氟乙烯與二氯二氟乙烯之共聚物、使包含四氟乙烯與至少1種共聚合單體之單體混合物進行共聚合而得之共聚物、於共聚合主鏈具有環狀結構之含氟共聚物、吸水率1%以上之吸水性物質、吸水率0.1%以下之防濕性物質等。Specific examples of the protective insulating film include metal oxides such as MgO, SiO, SiO2 , Al2 O3 , GeO, NiO, CaO, BaO, Fe2 O3 , Y2 O3 , or TiO2 , and SiNx. Metal nitride such as SiNxOy, metal fluoride such as MgF2 , LiF, AlF3 or CaF2 , polyethylene, polypropylene, polymethyl methacrylate, polyimine, polyurea, polytetrafluoroethylene, poly Copolymerization of chlorotrifluoroethylene, polydichlorodifluoroethylene, a copolymer of chlorotrifluoroethylene and dichlorodifluoroethylene, and copolymerization of a monomer mixture comprising tetrafluoroethylene and at least one copolymerized monomer A fluorinated copolymer having a cyclic structure in a main chain, a water-absorbent substance having a water absorption ratio of 1% or more, a moisture-proof substance having a water absorption ratio of 0.1% or less, or the like.
關於保護絕緣膜之形成方法，並無特別限定，例如可適用：真空蒸鍍法、濺鍍法、反應性濺鍍法、MBE(Molecular Beam Epitaxy，分子束磊晶)法、團簇離子束法、離子鍍著法、電漿聚合法(高頻激發離子鍍著法)、電漿CVD法、雷射CVD法、熱CVD法、氣體源CVD法、塗佈法、印刷法、或轉印法。The method for forming the protective insulating film is not particularly limited, and examples thereof include vacuum deposition method, sputtering method, reactive sputtering method, MBE (Molecular Beam Epitaxy) method, and cluster ion beam method. , ion plating method, plasma polymerization method (high frequency excitation ion plating method), plasma CVD method, laser CVD method, thermal CVD method, gas source CVD method, coating method, printing method, or transfer method .
亦可視需要進行熱處理作為TFT之後處理。作為熱處理，於溫度100℃以上、且大氣下或氮氣環境下進行。作為進行熱處理之步驟，可於成膜活性層後進行，亦可於TFT製作步驟之最後進行。藉由進行熱處理，而有抑制TFT之特性之面內不均，提高驅動穩定性等之效果。Heat treatment may also be performed as a post-TFT treatment as needed. The heat treatment is carried out at a temperature of 100 ° C or higher and under an atmosphere or a nitrogen atmosphere. The step of performing the heat treatment may be performed after the film formation of the active layer or at the end of the TFT fabrication step. By performing the heat treatment, there is an effect of suppressing the in-plane unevenness of the characteristics of the TFT, and improving the driving stability and the like.
本發明之薄膜場效型電晶體可用作使用液晶或電致發光元件之平面薄型圖像顯示裝置(FPD)、行動電話顯示器、個人數位助理(PDA)、電腦顯示器、汽車之資訊顯示器、TV監視器、通用照明等主動矩陣電路等之電子機器上所搭載之電晶體。The thin film field effect type transistor of the present invention can be used as a flat thin image display device (FPD), a mobile phone display, a personal digital assistant using a liquid crystal or an electroluminescence element.A transistor mounted on an electronic device such as a (PDA), a computer monitor, an information display of a car, a TV monitor, or an active matrix circuit such as general illumination.
以下，使用圖式對薄膜場效型電晶體之製造方法之其他態樣進行說明。Hereinafter, other aspects of the method of manufacturing the thin film field effect transistor will be described using the drawings.
圖2a~圖2g中所示之製造方法之特徵在於：藉由以閘極電極作為光罩之背面曝光而形成電阻層。藉由如此方式，可使電阻層與閘極電極之形狀吻合。藉由本製造方法，亦可於不增加光罩之步驟數之情況下兼具電晶體之高遷移率與高可靠性。以下，具體地進行說明。The manufacturing method shown in FIGS. 2a to 2g is characterized in that a resistance layer is formed by exposing the gate electrode as a back surface of the mask. In this way, the shape of the resistance layer can be matched with the shape of the gate electrode. According to the manufacturing method, the high mobility and high reliability of the transistor can be achieved without increasing the number of steps of the photomask. Hereinafter, it demonstrates concretely.
首先，於玻璃等基板110上形成閘極電極120(圖2a)，並於其上形成閘極絕緣膜130(圖2b)。First, a gate electrode 120 (FIG. 2a) is formed on a substrate 110 such as glass, and a gate insulating film 130 is formed thereon (FIG. 2b).
其次，於該附閘極絕緣膜之基板上成膜ITZO等作為通道層(半導體層)140，繼而成膜IGZO等作為電阻層150(圖2c)，並於其上積層層間絕緣膜160(圖2d)。Next, an ITZO or the like is formed as a channel layer (semiconductor layer) 140 on the substrate on which the gate insulating film is attached, and a film IGZO or the like is formed as the resistance layer 150 (FIG. 2c), and an interlayer insulating film 160 is laminated thereon (FIG. 2c) 2d).
於上述積層體上塗佈光阻劑，以閘極電極120作為光罩進行背面曝光(自基板側之曝光)。顯影後，藉由蝕刻而加工層間絕緣膜160與電阻層150之露出部分，使通道層140之上表面之一部分露出(圖2e)。A photoresist is applied onto the laminate, and the gate electrode 120 is used as a mask for back exposure (exposure from the substrate side). After development, the exposed portions of the interlayer insulating film 160 and the resistive layer 150 are processed by etching to expose a portion of the upper surface of the channel layer 140 (Fig. 2e).
其次，成膜電極材料後，藉由圖案化而形成源極/汲極電極170、172(圖2f)，設置保護膜180及第2接觸孔182，獲得薄膜場效電晶體2(圖2g)。Next, after forming the electrode material, the source/drain electrodes 170 and 172 are formed by patterning (FIG. 2f), and the protective film 180 and the second contact hole 182 are provided to obtain the thin film field effect transistor 2 (FIG. 2g). .
各層之形成材料或形成方法等製造方法、條件除特別記載以外，與本發明之製造方法相同。The production methods and conditions such as the forming material or the forming method of each layer are the same as those of the production method of the present invention unless otherwise specified.
圖3a~圖31中所示之製造方法之特徵在於：使用半色調光罩(halftone mask)。藉由使用半色調光罩，可以1次之曝光步驟加工通道層與電阻層。以下，具體地進行說明。The manufacturing method shown in Figs. 3a to 31 is characterized in that a halftone mask is used. By using a halftone mask, the channel layer and the resistive layer can be processed in one exposure step. Hereinafter, it demonstrates concretely.
首先，於基板210上形成閘極電極220及閘極絕緣膜230(圖3a、3b)。其次，藉由濺鍍等而成膜通道層(半導體層)240及電阻層250。First, a gate electrode 220 and a gate insulating film 230 are formed on the substrate 210 (Figs. 3a and 3b). Next, the channel layer (semiconductor layer) 240 and the resistance layer 250 are formed by sputtering or the like.
其次，塗佈光阻劑252後，使用半色調光罩進行曝光(圖3c~3h)。該光罩成為如下之設計：通道層240與源極/汲極電極270、272直接電性連接之部分為全面曝光，通道層240經由電阻層250而連接於源極/汲極電極270、272之部分為半色調曝光。Next, after the photoresist 252 is applied, exposure is performed using a halftone mask (Figs. 3c to 3h). The reticle is designed such that the portion of the channel layer 240 that is directly electrically connected to the source/drain electrodes 270, 272 is fully exposed, and the channel layer 240 is connected to the source/drain electrodes 270, 272 via the resistive layer 250. Part of it is halftone exposure.
藉由使用此種光罩，可以1次之曝光實現藉由電阻層被覆通道層之後通道，且通道層與源極/汲極電極電性地直接連接之構造。By using such a photomask, the channel after the channel layer is covered by the resistance layer can be realized by one exposure, and the channel layer and the source/drain electrode are electrically connected directly.
於圖3c~3h中使用半色調光罩，結果顯示出藉由顯影而於光阻劑中產生階差，露出面之蝕刻部分發生變化之情況。即，於圖3g、3h中，通道層240之上表面中，僅露出與源極/汲極電極270、272直接電性連接之部分。A halftone mask was used in Figs. 3c to 3h, and as a result, a step was generated in the photoresist by development, and the etching portion of the exposed surface was changed. That is, in FIGS. 3g and 3h, only the portion directly connected to the source/drain electrodes 270 and 272 is exposed in the upper surface of the channel layer 240.
其次，成膜層間絕緣膜260，進行蝕刻加工(圖3i、3j)。進行電極材料之成膜後，蝕刻為源極/汲極電極270、272之形狀(圖3k)。最後，設置保護膜280及接觸孔282而獲得薄膜氧化物電晶體3(圖3l)。Next, the interlayer insulating film 260 is formed and etched (Figs. 3i and 3j). After the electrode material is formed, it is etched into the shape of the source/drain electrodes 270 and 272 (Fig. 3k). Finally, the protective film 280 and the contact hole 282 are provided to obtain a thin film oxide crystal 3 (Fig. 3l).
各層之形成材料或形成方法等製造方法、條件除特別記載以外，與本發明之製造方法相同。The production methods and conditions such as the forming material or the forming method of each layer are the same as those of the production method of the present invention unless otherwise specified.
以下，藉由實施例對本發明之薄膜場效型電晶體進行說明，但本發明並不受該等實施例任何限定。Hereinafter, the thin film field effect type transistor of the present invention will be described by way of examples, but the present invention is not limited by the examples.
製作圖1中所示之具有底閘極構造之場效型電晶體1。A field effect transistor 1 having a bottom gate structure as shown in FIG. 1 was fabricated.
準備直徑4英吋之無鹼玻璃基板10，利用濺鍍法成膜厚度50nm之Cr後，藉由光微影法圖案化為閘極配線狀，而製成閘極電極20。其次，將該基板設置於PE-CVD裝置，導入SiH4、N2O、N2，獲得厚度150nm之閘極絕緣膜(SiO2膜)30。An alkali-free glass substrate 10 having a diameter of 4 inches was prepared, and Cr having a thickness of 50 nm was formed by a sputtering method, and then patterned into a gate wiring by photolithography to form a gate electrode 20. Next, the substrate was placed in a PE-CVD apparatus, and SiH4 , N2 O, and N2 were introduced to obtain a gate insulating film (SiO2 film) 30 having a thickness of 150 nm.
其次，將該附閘極絕緣膜30之玻璃基板10安裝於濺鍍裝置，於DC 100W、濺鍍壓力0.5Pa、氧分壓30%之條件下濺鍍ITZO(In：Sn：Zn=36.5：15：48.5 at%)，成膜50nm之通道層(半導體層)40。繼而，於DC 100W、濺鍍壓力0.5Pa、氧分壓30%之條件下濺鍍IGZO(In：Ga：Zn=1：2：2)，成膜50nm之電阻層50。其次，將該基板水洗、乾燥後，塗佈光阻劑，按預烘烤、曝光、後烘烤、顯影、蝕刻之順序進行處理，藉此使ITZO與IGZO同時圖案化。蝕刻係導入甲烷與氮氣，利用電感耦合方式(ICP，Inductively Coupled Plasma)之高密度電漿乾式蝕刻而進行。進而，將該基板導入至氧氣灰化裝置，進行氧氣灰化而剝離光阻劑。Next, the glass substrate 10 with the gate insulating film 30 is mounted on the sputtering device,ITZO (In:Sn:Zn=36.5:15:48.5 at%) was sputtered under conditions of a DC 100W, a sputtering pressure of 0.5 Pa, and an oxygen partial pressure of 30% to form a 50 nm channel layer (semiconductor layer) 40. Then, IGZO (In:Ga:Zn = 1:2:2) was sputtered under conditions of DC 100 W, a sputtering pressure of 0.5 Pa, and an oxygen partial pressure of 30% to form a 50 nm resistance layer 50. Next, after the substrate is washed with water and dried, a photoresist is applied and treated in the order of prebaking, exposure, post-baking, development, and etching, whereby ITZO and IGZO are simultaneously patterned. The etching is performed by introducing methane and nitrogen gas, and performing high-density plasma dry etching by inductively coupled plasma (ICP). Further, the substrate was introduced into an oxygen ashing apparatus, and oxygen ashing was performed to remove the photoresist.
再次將該基板設置於PE-CVD裝置，導入SiH4、N2O、N2，於基板溫度205℃下積層厚度200nm之層間絕緣膜60(半導體層保護膜：SiO2)。其次，將該基板設置於乾式蝕刻裝置，形成源極/汲極電極用之第1接觸孔62。The substrate was again placed in a PE-CVD apparatus, and SiH4 , N2 O, and N2 were introduced , and an interlayer insulating film 60 (semiconductor layer protective film: SiO2 ) having a thickness of 200 nm was laminated at a substrate temperature of 205 ° C. Next, the substrate is placed in a dry etching apparatus to form a first contact hole 62 for the source/drain electrode.
進而，將該積層體設置於濺鍍裝置，成膜ITO後，再次利用光微影法進行圖案化而製成源極電極70、汲極電極72。繼而，藉由與上述相同之方法，利用電漿CVD成膜保護膜80，開出第2接觸孔82，最後，於氮氣中350℃、1小時之條件下進行退火，獲得薄膜場效電晶體。Further, the layered body was placed in a sputtering apparatus, and ITO was formed, and then patterned by photolithography to form a source electrode 70 and a drain electrode 72. Then, by the same method as described above, the protective film 80 is formed by plasma CVD, the second contact hole 82 is opened, and finally, annealing is performed under nitrogen at 350 ° C for 1 hour to obtain a thin film field effect transistor. .
活性層及電阻層之折射率係準備使活性層及電阻層之各自於玻璃上成膜100nm左右而成之單膜，利用光學式薄膜測定系統(Ya-man公司之FilmTek)進行測定。The refractive index of the active layer and the resistive layer was prepared by forming a single film of each of the active layer and the resistive layer on the glass to a thickness of about 100 nm, and measuring it by an optical film measuring system (FilmTek of Ya-man Co., Ltd.).
活性層及電阻層之電阻值係將使活性層及電阻層之各自於玻璃上成膜100nm左右而成之單膜切出為1cm□(1cm×1cm)，設置於東陽技術公司製造之Resitest 8200並利用Van der Pauw法進行測定。The resistance value of the active layer and the resistive layer is such that a single film formed by forming an active layer and a resistive layer on the glass to a thickness of about 100 nm is cut into 1 cm □ (1 cm × 1 cm), and is placed in Resitest 8200 manufactured by Dongyang Technology Co., Ltd. The measurement was carried out by the Van der Pauw method.
對所獲得之薄膜場效型電晶體1進行下述評價。將結果示於表1。The obtained film field effect type transistor 1 was subjected to the following evaluation. The results are shown in Table 1.
使用半導體參數分析儀(Keithley 4200)，於大氣壓之乾燥氮氣環境下、室溫、遮光環境下測定4英吋玻璃之中央部之TFT。測定係將汲極電壓設為10V，觀察使閘極電壓自-15V變化至20V時之汲極電流。A TFT of a central portion of 4 inches of glass was measured using a semiconductor parameter analyzer (Keithley 4200) under a dry nitrogen atmosphere at atmospheric pressure at room temperature under a light-shielding environment. The measurement was performed by setting the drain voltage to 10 V and observing the drain current when the gate voltage was changed from -15 V to 20 V.
再者，遷移率係測定通道寬度W與通道長度L分別為W/L=50/50μm與50/10μm之2處，將各自之結果設為遷移率A、遷移率B。Further, the mobility was measured by measuring the channel width W and the channel length L as two points of W/L = 50/50 μm and 50/10 μm, respectively, and the respective results were referred to as mobility A and mobility B.
進而，計算遷移率比A/B作為表示接觸電阻之大小之指標。於接觸電阻較大之情形時，若通道長度變短，則接觸電阻對元件整體之動作之貢獻相對地增高，遷移率B計算為較小值。因此，若A/B=1.0~1.3，則接觸電阻之影響較小，但若超過1.5，則變得無法忽視影響。Further, the mobility ratio A/B is calculated as an index indicating the magnitude of the contact resistance. When the contact resistance is large, if the channel length is shortened, the contribution of the contact resistance to the overall operation of the element is relatively increased, and the mobility B is calculated to be a small value. Therefore, if A/B = 1.0 to 1.3, the influence of the contact resistance is small, but if it exceeds 1.5, the influence cannot be ignored.
其結果，遷移率A為45cm2/Vs、遷移率B為44cm2/Vs，顯示幾乎相同之遷移率，確認到接觸電阻較小。As a result, the mobility of A 45cm2 / Vs, mobility B is 44cm2 / Vs, showed almost the same mobility, it was confirmed that the contact resistance is small.
應力試驗係實施正偏壓加熱應力試驗(PBTS，Positive Bias Temperature Stress)與負偏壓光照射試驗(NBIS，Negative Bias Illumination Stress)之2種。PBTS係以50℃施加閘極偏壓+20V，將經過1萬秒後之閾值電壓(Vth)與試驗前相比，將其差量設為△Vth。NBIS係於室溫下一面以460nm之波長照射0.1mW/cm2之光，一面施加閘極偏壓-20V，將經過1萬秒後之閾值電壓(Vth)與試驗前相比，將其差量設為△Vth。The stress test is performed by two types of positive bias heating stress test (PBTS, Positive Bias Temperature Stress) and negative bias light exposure test (NBIS, Negative Bias Illumination Stress). The PBTS applied a gate bias of +20 V at 50 ° C, and set the threshold voltage (Vth) after 10,000 seconds to ΔVth as compared with that before the test. NBIS irradiates 0.1 mW/cm2 of light at a wavelength of 460 nm at room temperature, and applies a gate bias of -20 V. The threshold voltage (Vth) after 10,000 seconds is compared with that before the test. The amount is set to ΔVth.
PBTS與NBIS之△Vth表示電晶體動作點之偏移，其數值可謂越小越好，較佳為0~±1V之範圍內，更佳為0~±0.3V之範圍內。The ΔVth of the PBTS and the NBIS indicates the shift of the operating point of the transistor, and the value may be as small as possible, preferably in the range of 0 to ±1 V, more preferably in the range of 0 to ±0.3 V.
試驗之結果，PBTS與NBIS之△Vth分別顯示出0.1V、-0.8V之良好成績。將結果示於表1。As a result of the test, the ΔVth of PBTS and NBIS showed good results of 0.1 V and -0.8 V, respectively. The results are shown in Table 1.
以下，改變各種條件而試製積層TFT，評價遷移率與可靠性。將結果示於表1。Hereinafter, the laminated TFT was experimentally produced by changing various conditions, and the mobility and reliability were evaluated. The results are shown in Table 1.
表1中之活性層及電阻層之材料中之「a-」意指「非晶質(amorphous)」，「p-」意指「多晶質(polycrystalline)」。In the materials of the active layer and the resistive layer in Table 1, "a-" means "amorphous", and "p-" means "polycrystalline".
實施例5之活性層為2層構成，ITZO位於層間絕緣層側。The active layer of Example 5 was composed of two layers, and ITZO was located on the side of the interlayer insulating layer.
於比較例1中，由於電阻層之膜厚過小，故而無電阻膜積層之效果，藉由NBIS試驗所得之△Vth成為-2.3V，可知動作可靠性較低。In Comparative Example 1, since the film thickness of the resistive layer was too small, the effect of the resistive film lamination was not obtained, and the ΔVth obtained by the NBIS test was -2.3 V, and the operational reliability was low.
於比較例2中，由於活性層之膜厚過大，故而認為TFT中產生應力，藉由PBTS試驗所得之△Vth成為+1.2V，藉由NBIS試驗所得之Vth成為-2.5V，可知動作可靠性較低。In Comparative Example 2, since the film thickness of the active layer was too large, it was considered that stress was generated in the TFT, and the ΔVth obtained by the PBTS test was +1.2 V, and the Vth obtained by the NBIS test was -2.5 V, and the operational reliability was known. Lower.
於比較例3中，由於ITZO(電阻層)未溶解於PAN中，故而源極/汲極電極與活性層之界面殘留電阻層，觀測到接觸電阻。具體而言，通道長度較短為10μm之情形之遷移率計算為較小之20cm2/Vs。In Comparative Example 3, since ITZO (resistance layer) was not dissolved in PAN, a contact resistance was observed at the interface between the source/drain electrode and the active layer, and contact resistance was observed. Specifically, the mobility in the case where the channel length is as short as 10 μm is calculated as a small 20 cm2 /Vs.
相對於該等比較例，於實施例1~5中，遷移率比(A/B)為1.0~1.1，遷移率A與B顯示幾乎相同之值，可知接觸電阻較小。又，PBTS與NBIS之△Vth為±1.0V以內，可知動作可靠性較高。With respect to these comparative examples, in Examples 1 to 5, the mobility ratio (A/B) was 1.0 to 1.1, and the mobility A and B showed almost the same value, and it was found that the contact resistance was small. Further, the ΔVth of the PBTS and the NBIS is within ±1.0 V, and it is understood that the operational reliability is high.
變更各種條件而試製與實施例1相同之元件構成之積層TFT，對遷移率與可靠性進行評價。將結果示於表2。The laminated TFT having the same element structure as that of the first embodiment was produced by changing various conditions, and the mobility and reliability were evaluated. The results are shown in Table 2.
製作圖2g中所示之具有底閘極構造之場效型電晶體2。The field effect transistor 2 having the bottom gate structure shown in Fig. 2g was fabricated.
準備直徑4英吋之無鹼玻璃基板110，利用濺鍍法成膜厚度50nm之Mo後，藉由光微影法圖案化為閘極配線狀，而製成閘極電極120(圖2a)。其次，將該基板設置於PE-CVD裝置，導入SiH4、N2O、N2，獲得厚度150nm之閘極絕緣膜(SiO2膜)130(圖2b)。An alkali-free glass substrate 110 having a diameter of 4 inches was prepared, and Mo having a thickness of 50 nm was formed by a sputtering method, and then patterned into a gate wiring by photolithography to form a gate electrode 120 (FIG. 2a). Next, the substrate was placed in a PE-CVD apparatus, and SiH4 , N2 O, and N2 were introduced to obtain a gate insulating film (SiO2 film) 130 having a thickness of 150 nm ( FIG. 2 b ).
其次，將該附閘極絕緣膜之玻璃基板安裝於濺鍍裝置，於DC 100W、濺鍍壓力0.5Pa、氧分壓30%之條件下濺鍍ITZO(In：Sn：Zn=38.5：15：46.5 at%)，成膜50nm之通道層(半導體層)140。繼而，於DC 100W、濺鍍壓力0.5Pa、氧分壓30%之條件下濺鍍IGZO(In：Ga：Zn=20：40：40)，成膜50nm之電阻層150。Next, the glass substrate with the gate insulating film was mounted on a sputtering apparatus, and ITZO (In:Sn:Zn was sputtered under the conditions of DC 100W, sputtering pressure of 0.5 Pa, and oxygen partial pressure of 30%.=38.5:15:46.5 at%), a 50 nm channel layer (semiconductor layer) 140 was formed. Then, IGZO (In:Ga:Zn=20:40:40) was sputtered under conditions of DC 100 W, sputtering pressure of 0.5 Pa, and partial pressure of oxygen of 30% to form a 50 nm resistance layer 150.
其次，將該基板水洗、乾燥後，塗佈光阻劑，預烘烤後，使用通道區域用光罩進行曝光。其次，進行後烘烤、顯影，使用草酸蝕刻ITZO與IGZO之不需要部分。其後，進行光阻劑剝離、水洗，形成包含ITZO與IGZO之積層之通道(圖2c)。Next, after the substrate was washed with water and dried, a photoresist was applied, and after prebaking, exposure was performed using a mask in the channel region. Next, post-baking and developing were performed, and the unnecessary portions of ITZO and IGZO were etched using oxalic acid. Thereafter, the photoresist was peeled off and washed with water to form a channel including a laminate of ITZO and IGZO (Fig. 2c).
其次，再次將該基板設置於PE-CVD裝置，導入SiH4、N2O、N2，於基板溫度205℃下積層厚度200nm之層間絕緣膜160(半導體層保護膜：SiO2)(圖2d)。Next, the substrate was again placed in a PE-CVD apparatus, and SiH4 , N2 O, and N2 were introduced , and an interlayer insulating film 160 (semiconductor layer protective film: SiO2 ) having a thickness of 200 nm was deposited at a substrate temperature of 205 ° C ( FIG. 2 d ). ).
再次將該基板水洗、乾燥後，塗佈光阻劑，預烘烤後，進行將閘極電極(Mo)設為光罩之背面曝光。進行後烘烤、顯影後，設置於乾式蝕刻裝置，使用CF4氣體而加工層間絕緣膜160。進而，浸漬於PAN中而蝕刻IGZO之露出部分，使ITZO面露出(圖2e)。After the substrate was washed with water and dried again, a photoresist was applied, and after baking, the gate electrode (Mo) was exposed to the back side of the mask. After post-baking and development, the film was placed in a dry etching apparatus, and the interlayer insulating film 160 was processed using CF4 gas. Further, the exposed portion of the IGZO was immersed in the PAN to expose the ITZO surface (Fig. 2e).
進而，將該積層體設置於濺鍍裝置，成膜Mo後，再次利用光微影法進行圖案化而製成源極/汲極電極170、172(圖2f)。繼而，藉由與上述相同之方法，利用電漿CVD成膜保護膜180，開出第2接觸孔182，最後，於氮氣中350℃、1小時之條件下進行退火，獲得薄膜場效電晶體2(圖2g)。Further, the layered body was placed in a sputtering apparatus, and Mo was formed, and then patterned by photolithography to form source/drain electrodes 170 and 172 (FIG. 2f). Then, by the same method as described above, the protective film 180 is formed by plasma CVD, the second contact hole 182 is opened, and finally, annealing is performed under nitrogen at 350 ° C for 1 hour to obtain a thin film field effect transistor. 2 (Fig. 2g).
對薄膜場效電晶體2之遷移率與可靠性進行評價。將結果示於表2。The mobility and reliability of the thin film field effect transistor 2 were evaluated. The results are shown in Table 2.
製作圖31中所示之具有底閘極構造之場效型電晶體3。The field effect type transistor 3 having the bottom gate structure shown in Fig. 31 was fabricated.
準備直徑4英吋之無鹼玻璃基板210，利用濺鍍法成膜厚度50nm之Mo後，藉由光微影法圖案化為閘極配線狀，而製成閘極電極220(圖3a)。其次，將該基板設置於PE-CVD裝置，導入SiH4、N2O、N2，獲得厚度150nm之閘極絕緣膜(SiO2膜)230(圖3b)。An alkali-free glass substrate 210 having a diameter of 4 inches was prepared, and Mo having a thickness of 50 nm was formed by a sputtering method, and then patterned into a gate wiring by photolithography to form a gate electrode 220 (Fig. 3a). Next, the substrate was placed in a PE-CVD apparatus, and SiH4 , N2 O, and N2 were introduced to obtain a gate insulating film (SiO2 film) 230 having a thickness of 150 nm ( FIG. 3 b ).
其次，將該附閘極絕緣膜之玻璃基板安裝於濺鍍裝置，於DC 100W、濺鍍壓力0.5Pa、水分壓1%之條件下濺鍍IGO(In：Ga=92.8：7.2 at%)，成膜30nm之通道層(半導體層)240。繼而，於DC 100W、濺鍍壓力0.5Pa、氧分壓30%之條件下濺鍍IGZO(In：Ga：Zn=20：40：40 at%)，成膜30nm之電阻層250。Next, the glass substrate with the gate insulating film was mounted on a sputtering apparatus, and IGO (In:Ga=92.8: 7.2 at%) was sputtered under conditions of DC 100 W, sputtering pressure of 0.5 Pa, and water pressure of 1%. A channel layer (semiconductor layer) 240 of 30 nm was formed. Then, IGZO (In:Ga:Zn=20:40:40 at%) was sputtered under conditions of DC 100 W, sputtering pressure of 0.5 Pa, and partial pressure of oxygen of 30% to form a resistive layer 250 of 30 nm.
其次，將該基板水洗、乾燥後，塗佈光阻劑252，預烘烤後，使用半色調光罩進行曝光。該光罩成為如下之設計：通道層與源極/汲極電極直接電性連接之部分為全面曝光，通道層經由電阻層而連接於源極/汲極電極之部分為半色調曝光。於圖3c~3h中使用半色調光罩，結果顯示出藉由顯影而於光阻劑252中產生階差，露出面之蝕刻部分發生變化之情況。Next, after the substrate was washed with water and dried, the photoresist 252 was applied, and after prebaking, exposure was performed using a halftone mask. The reticle is designed such that the portion of the channel layer directly connected to the source/drain electrode is fully exposed, and the portion of the channel layer connected to the source/drain electrode via the resistive layer is halftone exposed. A halftone mask was used in Figs. 3c to 3h, and as a result, a step was generated in the photoresist 252 by development, and the etching portion of the exposed surface was changed.
其次，將該基板再次設置於PE-CVD裝置，導入SiH4、N2O、N2，獲得厚度150nm之層間絕緣膜(SiO2膜)260(圖3i)。層間絕緣膜(SiO2)260係使用光微影技術，僅留有高電阻氧化物半導體IGZO之後通道部分而進行蝕刻(圖3j)。其次，將該基板安裝於濺鍍裝置，按Ti/Cu之順序進行成膜後，蝕刻為源極/汲極電極270、272之形狀(圖3k)。Next, the substrate was again placed in a PE-CVD apparatus, and SiH4 , N2 O, and N2 were introduced to obtain an interlayer insulating film (SiO2 film) 260 having a thickness of 150 nm (Fig. 3i). The interlayer insulating film (SiO2 ) 260 is etched using the photolithography technique, leaving only the channel portion after the high-resistance oxide semiconductor IGZO (Fig. 3j). Next, the substrate was mounted on a sputtering apparatus, and formed into a film in the order of Ti/Cu, and then etched into the shape of the source/drain electrodes 270 and 272 (Fig. 3k).
再次將該基板設置於PE-CVD裝置，導入SiH4、N2O、N2，成膜厚度150nm之保護膜(SiO2膜)280。該保護膜280亦藉由使用光微影技術對源極、汲極、閘極之電極取出部分進行蝕刻，而形成接觸孔282。最後，於氮氣中350℃、1小時之條件下進行退火，獲得作為目標之薄膜氧化物電晶體3(圖3l)。This substrate was again placed in a PE-CVD apparatus, and SiH4 , N2 O, and N2 were introduced to form a protective film (SiO2 film) 280 having a thickness of 150 nm. The protective film 280 also forms a contact hole 282 by etching the electrode extraction portions of the source, the drain, and the gate using photolithography. Finally, annealing was carried out under nitrogen at 350 ° C for 1 hour to obtain a target thin film oxide transistor 3 (Fig. 3l).
藉由使用半色調光罩，可以1次之曝光步驟加工通道層與電阻層。對薄膜場效電晶體3之遷移率與可靠性進行評價。將結果示於表2。By using a halftone mask, the channel layer and the resistive layer can be processed in one exposure step. The mobility and reliability of the thin film field effect transistor 3 were evaluated. The results are shown in Table 2.
本發明之薄膜場效型電晶體可用作使用液晶或電致發光元件之平面薄型圖像顯示裝置(FPD)、行動電話顯示器、個人數位助理(PDA)、電腦顯示器、汽車之資訊顯示器、TV監視器、通用照明等主動矩陣電路等之電子機器上所搭載之電晶體。The thin film field effect type transistor of the present invention can be used as a flat thin image display device (FPD) using a liquid crystal or electroluminescence element, a mobile phone display, a personal digital assistant (PDA), a computer display, an information display of a car, and a TV. A transistor mounted on an electronic device such as an active matrix circuit such as a monitor or general illumination.
以上對本發明之若干實施形態及/或實施例進行了詳細說明，但業者容易於實質上不脫離本發明之新穎之教示及效果之情況下，對作為該等例示之實施形態及/或實施例進行大量變更。因此，該等大量變更包含於本發明之範圍中。The embodiments and/or examples of the present invention have been described in detail above, but the embodiments and/or embodiments of the present invention are susceptible to the embodiments of the present invention. Make a lot of changes. Accordingly, such numerous modifications are included within the scope of the invention.
將成為本申請案之巴黎優先之基礎的日本申請說明書之內容全部援用於本文中。The contents of the Japanese application specification, which is the basis of the Paris priority of the present application, are all incorporated herein by reference.
1‧‧‧薄膜場效型電晶體1‧‧‧Thin field effect transistor
10‧‧‧玻璃基板10‧‧‧ glass substrate
20‧‧‧閘極電極20‧‧‧gate electrode
30‧‧‧閘極絕緣膜30‧‧‧gate insulating film
40‧‧‧活性層(半導體層)40‧‧‧active layer (semiconductor layer)
50‧‧‧電阻膜50‧‧‧Resistive film
60‧‧‧層間絕緣膜60‧‧‧Interlayer insulating film
70‧‧‧源極電極70‧‧‧Source electrode
72‧‧‧汲極電極72‧‧‧汲electrode
80‧‧‧保護膜80‧‧‧Protective film
82‧‧‧第2接觸孔82‧‧‧2nd contact hole
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012288606 | 2012-12-28 |
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|---|---|
| TW201436231Atrue TW201436231A (en) | 2014-09-16 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102148877ATW201436231A (en) | 2012-12-28 | 2013-12-27 | Thin film field effect transistor |
| Country | Link |
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| JP (1) | JPWO2014103323A1 (en) |
| TW (1) | TW201436231A (en) |
| WO (1) | WO2014103323A1 (en) |
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