本發明係有關於數位系統中在複數個時脈域之間轉移資料信號的系統與方法，特別是當該等時脈域不同步時。The present invention relates to systems and methods for transferring data signals between a plurality of clock domains in a digital system, particularly when the clock domains are out of sync.
在許多不同的電子系統中，例如一個無線(如藍芽)系統，其至少零星地存在二或二個以上不同步的時脈域被需求用以相互通訊。舉例來說，一個中央處理器可執行在一高頻率上，而一或多個週邊裝置則執行在一低頻率上。此外，其中一個時脈域在不被使用時可進入數個不活動期間，用以保存電力，例如一個睡眠或待命模式。經過這些期間時，該較快的時脈域與較慢的時脈域典型地被作為計時器使用。在這些期間裡，二時脈域之間通常沒有通訊，然而當該一時脈域離開該睡眠或待命模式時，其通常將需要和較低時脈域進行通訊。此外，該快與慢時脈域不需要相互同步。In many different electronic systems, such as a wireless (e.g., Bluetooth) system, there are at least two or more unsynchronized clock domains that are sporadically required to communicate with one another. For example, one central processor can execute at a high frequency and one or more peripheral devices execute at a low frequency. In addition, one of the clock domains can enter several periods of inactivity when not in use to conserve power, such as a sleep or standby mode. The faster clock domain and the slower clock domain are typically used as timers during these periods. During these periods, there is typically no communication between the two clock domains, but when the one-time domain leaves the sleep or standby mode, it will typically need to communicate with the lower clock domain. In addition, the fast and slow clock domains do not need to be synchronized with each other.
目前已知包括不同時脈域頻率的系統會執行一種“交握(handshaking)”處理，藉此該等時脈域協議數個參數用於確立使該較慢的時脈域在轉移該資料信號至該較快的時脈域的過程中不改變該資料信號，例如藉由複數個旗標的使用。其為必要的用以使得一個信號可以經由該較慢時脈域的一安全期間而從該較慢的時脈域被轉移，即避開該較慢時脈域裡的一個變遷(該時脈從零變為一)與一個期間使該較慢時脈域不改變該被轉移的輸入信號，用於避免該信號的失誤或該系統的不穩。其係因為該較慢時脈域裡的值在該較慢時脈裡的數個變遷裡通常將被改變。然而已知的交握處理相當緩慢，此係由於它們需要該時脈域的多個週期來達到彼此間的同步。不僅變慢，當該較快時脈域必須在該處理過程中保持執行時也會消耗大量的電量。另外，在許多應用上，凍結該較慢時脈域裡的信號也不受到喜愛，例如在一個必須連續地計算的計時器上。目前已知解決此問題的方法是在該較慢的時脈域裡導入額外的掩蔽暫存器，並與一旗標結合來告訴該較快時脈域哪組掩蔽暫存器可確認為穩定。然而，此方法增加了大量所需的邏輯單元。It is currently known that systems including different clock domain frequencies perform a "handshaking" process whereby a plurality of parameters of the clock domain protocol are used to establish that the slower clock domain is transferring the data signal To the comparisonThe data signal is not changed during the fast clock domain, for example by the use of a plurality of flags. It is necessary to cause a signal to be transferred from the slower clock domain via a safe period of the slower clock domain, ie to avoid a transition in the slower clock domain (the clock) Changing from zero to one) and one period causes the slower clock domain to not change the transferred input signal for avoiding errors in the signal or instability of the system. This is because the values in the slower clock domain will usually be changed in several transitions in the slower clock. However, known handshake processes are quite slow, since they require multiple cycles of the clock domain to achieve synchronization with each other. Not only does it slow down, it also consumes a lot of power when the faster clock domain must remain executed during the process. In addition, in many applications, freezing the signals in the slower clock domain is not appreciated, for example on a timer that must be continuously calculated. A method known to solve this problem is to introduce an additional mask register in the slower clock domain and combine it with a flag to tell the faster clock domain which set of mask registers can be confirmed as stable. . However, this approach adds a large number of required logical units.
本發明的目的係提供用於兩個不同頻率的時脈域之間通訊的改良系統與方法。It is an object of the present invention to provide improved systems and methods for communication between clock domains of two different frequencies.
本發明的第一個發明概念係提供一個配置以用於一數位系統中將一資料信號從一第一時脈域轉移至一第二時脈域，其中該第一時脈域包括一第一時脈具有一頻率，一第二時脈具有一頻率，該第一時脈的頻率低於該第二時脈，該配置被設定用以：從該第一時脈域轉移該資料信號至該第二時脈域；使用藉由該第二時脈而被計時的偵測手段，偵測是否一預設的變遷發生在一預設時間之期間內的該第一時脈裡；假如該偵測手段偵測該預設時間之期間內的該第一時脈裡的該預設變遷，再次從該第一時脈域轉移該資料信號至該第二時脈域。A first inventive concept of the present invention provides a configuration for transferring a data signal from a first clock domain to a second clock domain in a digital system, wherein the first clock domain includes a first The clock has a frequency, a second clock has a frequency, and the frequency of the first clock is lower than the second clock. The configuration is configured to:Transmitting the data signal from the first clock domain to the second clock domain; detecting whether a predetermined transition occurs at a preset time by using a detecting means that is timed by the second clock In the first clock during the period; if the detecting means detects the preset transition in the first clock during the preset time period, the data signal is again transferred from the first clock domain to The second clock domain.
本發明也提供一種在一數位系統中用於將一數位資料由一第一時脈域轉移至一第二時脈域的方法，其中該第一時脈域包括一第一時脈具有一頻率，該第二時脈域包括一第二時脈具有一頻率，該第一時脈的頻率低於該第二時脈，該方法包括：從該第一時脈域轉移該資料信號至該第二時脈域；使用藉由該第二時脈而被計時的偵測手段，偵測是否一預設的變遷發生在一時間的預設週期內的該第一時脈裡；以及假如該偵測手段偵測一時間的預設週期內的該第一時脈裡的該預設變遷，再次從該第一時脈域轉移該資料信號至該第二時脈域。The present invention also provides a method for transferring a digital data from a first clock domain to a second clock domain in a digital system, wherein the first clock domain includes a first clock having a frequency The second clock domain includes a second clock having a frequency, the frequency of the first clock being lower than the second clock, the method comprising: transferring the data signal from the first clock domain to the first a second clock domain; detecting, by the detecting means that is timed by the second clock, whether a predetermined transition occurs in the first clock within a preset period of time; and The detecting means detects the preset transition in the first clock in a preset period of a time, and again transfers the data signal from the first clock domain to the second clock domain.
因此根據本發明可知，在不使用交握處理或忙碌旗標之情況下，該資料信號被簡單地從該第一時脈域轉移至該第二時脈域，但一個檢查被執行用於是否有一個時脈變遷發生在該預設期間內的該第一時脈裡。假如一個變遷被偵測到，該來自於該第一時脈域的資料信號被再次轉移至該第二時脈域，否則該信號的初始轉移被視為已“安全”，即沒有不穩定的風險。本案申請人也已領會此導致該資料信號的一個較快速的轉移從該第一時脈域至該第二時脈域，因為進行一個檢查於由該第二時脈所計時的第一時脈上。舉例來說，在已知包含交握處理的配置裡，該同步和轉移時間典型地至少是兩個第一時脈週期，即兩個緩慢的時間週期，與習知相比本發明實施例裡該同步與轉移時間可較短，其係為少數秒數的時脈週期，亦即少數的快速時脈週期。該資料信號接續在該第一時脈裡的一個變遷的轉移可以是在該預設期間的尾端，例如在該第二時脈的一個對應變遷，但較佳地發生在該第二時脈裡的後續變遷裡。Therefore, according to the present invention, the data signal is simply transferred from the first clock domain to the second clock domain without using a handshake process or a busy flag, but a check is performed for whether or not There is a clock transition that occurs in the first clock during the preset period. If a transition is detected, the data signal from the first clock domain is transferred again.Move to the second clock domain, otherwise the initial transfer of the signal is considered "safe", ie there is no risk of instability. The applicant of the present application has also appreciated that this results in a faster transition of the data signal from the first clock domain to the second clock domain because a check is made on the first clock counted by the second clock. on. For example, in configurations known to include a handshake process, the synchronization and transition times are typically at least two first clock cycles, ie, two slow time periods, as compared to conventional embodiments in the present invention. The synchronization and transfer time can be shorter, which is a few seconds of clock cycle, that is, a few fast clock cycles. The transition of the data signal to a transition in the first clock may be at the end of the predetermined period, such as a corresponding transition in the second clock, but preferably occurs in the second clock. In the subsequent changes in the.
該偵測手段可以被配置用以偵測一正緣或一負緣變遷，即藉由該被使用的系統以及技術的實現，該第一時脈域裡的資料值可以改變在該第一時脈裡一或全部的正緣或負緣變遷。然而，在一組實施例裡該被偵測的變遷係一個正緣變遷。The detecting means can be configured to detect a positive edge or a negative edge transition, that is, by using the system and the technology implemented, the data value in the first clock domain can be changed at the first time One or all of the positive or negative edges of the pulse change. However, in one set of embodiments the detected transition is a positive edge transition.
該第一時脈的檢查係用於確保該週期遠離一個變遷，即不論一個由零至一的正緣變遷或一個由一至零的負緣變遷，使得從該第一時脈域被轉移至該第二時脈域的該資料信號的起始轉移不與該第一時脈週期裡的一個變遷重疊。此係因為該第一時脈域裡的資料值被改變在該第一時脈的一或全部的變遷，其再次藉由該系統的實現而定，因此在此時從該第一時脈域轉移一個值，亦即當其正在改變，將可能造成資料錯誤或不穩。The first clock check is used to ensure that the period is far from a transition, that is, whether a zero-to-one positive edge transition or a negative transition from one to zero causes the first clock domain to be transferred to the The initial transition of the data signal of the second clock domain does not overlap with a transition in the first clock cycle. This is because the data value in the first clock domain is changed in one or all of the first clock, which is again determined by the implementation of the system, so at this time from the first clock domain Transfer a value, ie when it is positiveChanges may cause data errors or instability.
本案申請人已理解，由於該第一時脈的檢查確保該資料信號係安全而可以被轉移，使得該資料信號不管起始或後續的轉移皆發生在該第一、慢時脈週期的一個安全部分。在一些實施例裡，該資料信號不經由該配置裡的任何該等同步元件，例如該等偵測手段，而從該第一時脈域轉移至該第二時脈域。此外其不需要將該資料信號和該第二時脈域同步。在一組特別的實施例裡，沒有元件引發一時脈週期延遲介於該第一時脈域轉移該資料信號至該第二時脈域之間。The applicant of the present application has understood that since the inspection of the first clock ensures that the data signal is secure, it can be transferred so that the data signal occurs in a safe manner in the first, slow clock cycle regardless of whether the initial or subsequent transfer occurs. section. In some embodiments, the data signal is not transferred from the first clock domain to the second clock domain via any of the synchronization elements in the configuration, such as the detection means. In addition, it does not need to synchronize the data signal with the second clock domain. In a particular embodiment, no component causes a clock cycle delay to shift the data signal between the first clock domain and the second clock domain.
儘管對於該等單一位元的信號而言其具有一些優點，由於所有匯流排在該第一時脈的檢查的基礎上可以被確實地轉移，對於多位元的匯流排組而言其具有更大的優點。因此在一組實施例裡，該第一時脈域包括一第一匯流排，該第二時脈域包括一第二匯流排，以及不論是起始或假如被視為需要的後續轉移，資料皆從該第一匯流排被轉移至該第二匯流排。其也表示本發明的實施例不需要採用和串聯正反器有關的延遲時間或先前技術裡典型地被使用以配合該等時脈域的其他配置。Although it has some advantages for these single-bit signals, since all the bus bars can be reliably transferred on the basis of the inspection of the first clock, it has more for the multi-bit bus group. Great advantage. Thus, in one set of embodiments, the first clock domain includes a first bus bar, the second clock domain includes a second bus bar, and data that is either initiated or deemed to be needed for subsequent transfers All are transferred from the first bus bar to the second bus bar. It also means that embodiments of the present invention do not require the use of delay times associated with series flip-flops or other configurations typically used in the prior art to match the clock domains.
在本發明的一些實施例裡，資料匯流排包括至少8、16或32位元，因此將可得知該匯流排可包括任何數量的多個位元。In some embodiments of the invention, the data bus includes at least 8, 16, or 32 bits, so it will be appreciated that the bus can include any number of multiple bits.
一較快的轉移可達成的更進一步好處為用於減少電量消耗，此係由於其允許一或全部時脈在合適時更快地進入一睡眠狀態。舉例來說，該等已知的交握處理需要多個較慢的時脈週期來完成，而在此期間該較快的時脈被保持執行。其會消耗大量不需要的電量，特別係假如該較慢時脈域包括一低電量低頻率時脈以及該較率時脈域是高電量時，其為一低電量裝置裡的一個常見的配置。A further benefit that can be achieved with a faster transfer is to reduce power consumption, since it allows one or all of the clocks to be more appropriate when appropriate.Get into a sleep state quickly. For example, such known handshake processes require multiple slower clock cycles to complete, during which time the faster clocks are maintained. It consumes a large amount of unneeded power, especially if the slower time domain includes a low battery low frequency clock and the rate clock field is high, which is a common configuration in a low battery device. .
該用於該第一時脈裡預設變遷的檢查可以被執行於全部預設時間之週期裡。然而，在一組實施例裡，該偵測包括該第一時脈基於其他時脈，較佳地是該第二時脈，的離散取樣。在一些實施例裡，假如需要，其可使得該資料信號盡可能快速地重新被轉移，亦即，該離散取樣允許該第一時脈裡的預設變遷在發生後被短暫地偵測，使得該資料信號在此偵測後可以被轉移。在一組實施例裡，該偵測手段包括一邊緣偵測器，例如一個正緣偵測器。舉例來說，其可在該離散取樣的任何時點上將該第一時脈的值與其先前的值做比較，假如該第一時脈裡的一個變遷發生在該取樣期間裡，其可使得該變遷被偵測到。如先前所述，該邊緣偵測器方便地藉由該第二時脈而被計時。The check for the preset transition in the first clock can be performed during all preset time periods. However, in one set of embodiments, the detecting includes discrete sampling of the first clock based on other clocks, preferably the second clock. In some embodiments, the data signal can be re-transferred as quickly as possible, if desired, that is, the discrete sampling allows the preset transitions in the first clock to be detected briefly after occurrence, such that The data signal can be transferred after this detection. In one set of embodiments, the detection means includes an edge detector, such as a positive edge detector. For example, it may compare the value of the first clock to its previous value at any point in the discrete sampling, provided that a transition in the first clock occurs during the sampling period, which may cause the The transition is detected. As previously described, the edge detector is conveniently timed by the second clock.
該第一時脈裡的一個變遷之偵測需要一段有限的時間：該第一時脈變遷必須進入該偵測手段以及該等作為結果的邏輯信號必須經由該偵測手段以及任何其它的元件而被轉移，藉由此來影響該資料信號在該第一時脈域和該第二時脈域之間的轉移。一般而言，該偵測手段尋找該第一時脈裡的一個變遷所涵蓋的該預設期間係大於將在該第一時脈域裡的一信號的改變穩定在一有效值所使用的時間，以及將一個時脈變遷經由該偵測手段而傳播所使用的時間。舉例來說，該等離散取樣裡的取樣點數量一般將相關於將邏輯信號通過該等必要元件而傳播所使用的時間。在一個實施例裡，該預設期間係在該第二時脈的1和16週期之間，如在該第二時脈的2和8週期之間，如該第二時脈的4週期。然而，其不需要該預設期間對應一整數倍的第二時脈週期數量，例如其藉由一不同的時脈而被計時。假如一個變遷沒有在該預設期間內被偵測到，其可以安全地假設該資料信號從該第一時脈域至該第二時脈域的初始轉移並沒有和該第一時脈裡的一變遷重疊。The detection of a transition in the first clock requires a finite period of time: the first clock transition must enter the detection means and the resulting logic signal must pass the detection means and any other components. Transferred, thereby affecting the transfer of the data signal between the first clock domain and the second clock domain. In general, the detecting means finds that the preset period covered by a transition in the first clock is greater than the value of a signal that is to be stabilized in the first clock domain.Time, and the time it takes to propagate a clock through the detection means. For example, the number of sampling points in such discrete samples will generally be related to the time it takes to propagate the logic signal through the necessary elements. In one embodiment, the predetermined period is between 1 and 16 cycles of the second clock, such as between 2 and 8 cycles of the second clock, such as 4 cycles of the second clock. However, it does not require the number of second clock cycles corresponding to an integer multiple of the preset period, for example, it is clocked by a different clock. If a transition is not detected during the preset period, it can safely assume that the initial transition of the data signal from the first clock domain to the second clock domain is not in the first clock. A change overlaps.
該預設期間的進行可以藉由任何合適的計時機制而被計時，例如一個計時器或計數器。然而，如先前所述，在一些實施例裡，該第一時脈裡的一變遷之偵測包括數個階段及/或其被執行於該第二時脈的數個週期。因此較佳地該偵測手段包括一手段用以計數該離散取樣的多個階段及/或該預設期間之週期的數量。其可以係一個元件，如一向下計數器，一個格雷碼計數器，或一或多個串聯的正反器。較佳地該計數手段藉由該第二時脈而被計時，即與該偵測手段同步。The progress of the preset period can be timed by any suitable timing mechanism, such as a timer or counter. However, as previously described, in some embodiments, the detection of a transition in the first clock includes a number of stages and/or it is performed on a number of cycles of the second clock. Preferably, the detecting means comprises means for counting the plurality of phases of the discrete sampling and/or the number of periods of the predetermined period. It can be an element such as a down counter, a Gray code counter, or one or more series connected flip-flops. Preferably, the counting means is timed by the second clock, that is, synchronized with the detecting means.
在一組實施例裡，該第一時脈週期裡的該預設變遷之偵測可以執行在該第二時脈的任何變遷(不論正緣或負緣)。在一組實施例裡，該偵測被執行在該第二時脈的一個上升邊緣，即正緣變遷，例如其標記了該預設期間的起點。如先前所述，該偵測可包括多個步驟，以及數個後續步驟被執行於該第二時脈之接續，例如為下一個，上升邊緣。較佳地，該離散取樣的頻率相同於該第二時脈的頻率，亦即在該偵測期間，一個取樣被執行在該第二時脈的每個周期上，用以儘快偵測一個變遷，因而允許該資料信號之最快可能再變遷，假如有需要的話(儘管此非必要，其可以總是等到該預設期間結束才再次轉移該資料)。當該資料信號在該第一時脈裡的一變遷之後被再次轉移時，該第二時脈對第一時脈的頻率之比應該夠大，以足夠使其可以被保證該第一時脈裡的一個其它變遷將不發生在該段用於影響該資料信號從第一時脈域至第二時脈域之轉移的時間裡。In one set of embodiments, the detection of the predetermined transition in the first clock cycle can perform any transition (whether positive or negative) at the second clock. In one set of embodiments, the detection is performed at a rising edge of the second clock, i.e., a positive edge transition, e.g., it marks the beginning of the predetermined period. As previously described, the detection can include multiple steps, as well as several subsequent stepsThe step is performed on the continuation of the second clock, for example, the next, rising edge. Preferably, the frequency of the discrete sampling is the same as the frequency of the second clock, that is, during the detection, a sample is executed on each period of the second clock to detect a transition as soon as possible. Thus, the fastest possible transition of the data signal is allowed, if necessary (although this is not necessary, it can always wait until the end of the preset period to transfer the data again). When the data signal is transferred again after a transition in the first clock, the ratio of the frequency of the second clock to the first clock should be large enough to enable the first clock to be guaranteed One of the other transitions will not occur in the period during which the segment affects the transfer of the data signal from the first clock domain to the second clock domain.
儘管該第二時脈的頻率可為該第一時脈的頻率的整數倍數及/或具有一固定的相位，根據本發明可知在一般情況下沒有需要同步或特定的關係。此外，本發明的實施例可以忍受該第一及/或第二時脈域進入一睡眠或待命模式，以及相對於其他時脈域而非同步地重新啟動。Although the frequency of the second clock may be an integer multiple of the frequency of the first clock and/or has a fixed phase, it is known in accordance with the present invention that no synchronization or specific relationship is required in general. Moreover, embodiments of the present invention can tolerate the first and/or second clock domain entering a sleep or standby mode, and restarting relative to other clock domains rather than synchronously.
在一組實施例裡，該第二時脈的頻率至少是該第一時脈的頻率的四倍，如至少是該第一時脈的頻率的十倍，如至少是該第一時脈的頻率的一百倍，如至少是該第一時脈頻率的一千倍。同時滿足先前提供用於該時脈頻率比例的數個優點和理由，其確保此處具有足夠的時間用以偵測和處理該預設的變遷以及再次轉移該資料而無其他變遷的風險以及資料錯誤或不穩相關的風險。當該偵測手段藉由該第二時脈而被計時，其一般地係指(一些第二時脈週期的)該預設期間係遠小於該第一時脈的期間，因此隨著該第一時脈裡的一個變遷，所有必要的邏輯信號可以通過該配置，以及再次從該第一時脈域轉移該資料至該第二時脈域，係在使該第一時脈域裡的資料值可能被改變之該第一時脈的下一個變遷之前。其也影響該不同時脈域呈現在商業產品裡。在一個實施例的範例裡，該第一時脈的頻率是32kHz而該第二時脈的頻率是16MHz。In one embodiment, the second clock has a frequency that is at least four times the frequency of the first clock, such as at least ten times the frequency of the first clock, such as at least the first clock. One hundred times the frequency, such as at least one thousand times the first clock frequency. While satisfying several advantages and reasons previously provided for the clock frequency ratio, it ensures that there is sufficient time here to detect and process the preset transitions and to transfer the data again without the risk of other changes and data. Risk associated with errors or instability. When the detecting means is timed by the second clock, it generally means that the preset period (some of the second clock period) is much smaller than the period of the first clock, soa transition in the first clock, all necessary logic signals can pass through the configuration, and again transferring the data from the first clock domain to the second clock domain, in the first clock domain The data value may be changed before the next transition of the first clock. It also affects the different clock domains presented in commercial products. In an example of an embodiment, the frequency of the first clock is 32 kHz and the frequency of the second clock is 16 MHz.
如先前所述，該偵測手段可包括一邊緣偵測器被配置用以比較在連續時脈週期裡一個輸入端的數個值。然而，藉由該偵測的本質，任何合適的配置可以被提供，亦即任何可用於偵測該第一時脈裡的一個變遷的任何元件或配置可以被提供。因此一般地該偵測手段將具有該第一時脈為一輸入。在其他實施例裡該偵測手段包括一正反器，例如一D型正反器，或一比較器。多於一個正反器可以被串聯用以提供增強藉由該正反器而執行的檢查之可靠性。然而，如果該輸出繼續饋入至其他正反器的輸入端，一個不穩定狀態通過至兩個正反器的機會非常小，亦即由於該機率是倍增的。As previously described, the detection means can include an edge detector configured to compare a plurality of values of an input during a continuous clock cycle. However, with the nature of this detection, any suitable configuration can be provided, that is, any element or configuration that can be used to detect a transition in the first clock can be provided. Therefore, generally the detecting means will have the first clock as an input. In other embodiments, the detection means includes a flip-flop, such as a D-type flip-flop, or a comparator. More than one flip-flop can be connected in series to provide enhanced reliability for inspections performed by the flip-flop. However, if the output continues to feed to the inputs of the other flip-flops, the chance of passing an unstable state to the two flip-flops is very small, i.e., because the probability is multiplied.
在一組實施例裡，該用於該第一時脈裡一個變遷的檢查可以被執行在所有時間，例如該第二時脈的每個週期。然而，在其他實施例裡，該系統包括一手段用於起始該預設期間。其可以是一特別的信號被傳遞用以啟動該預設期間，或其可以被連結至該系統的其他信號或週期。舉例來說，該預設期間可以藉由該輸入信號裡的一個改變、或藉由該系統或第二時脈域進入或離開一個待命或睡眠狀態、或藉由一中央處理單元(CPU)而要求資料從該第一時脈域裡被讀取而被啟動。於該等實施例裡，該偵測被起動而不被連續地執行是有好處的，在只有該等檢查的執行是必要時它們幫助該系統用以減少該電量消耗，並且在該信號已經被轉移之後至一資料信號的下一個轉移被需要之前的期間裡，允許該第二時脈域進入一睡眠模式，因此保存了電量。本發明的實施例可特別地適合於一操作模式，其中該第二時脈域要求來自於該第一時脈域的該資料信號的一個轉移，例如當該第二時脈域離開一睡眠或待命模式並且要求某一資料信號，例如時間，其提供該信號來啟動該預設期間。In one set of embodiments, the check for a transition in the first clock can be performed at all times, such as each period of the second clock. However, in other embodiments, the system includes a means for initiating the predetermined period. It can be a special signal that is passed to initiate the preset period, or other signals or cycles that can be tied to the system. For example, the preset period can be changed by a change in the input signal, or enter or leave a standby or sleep by the system or the second clock domain.The sleep state, or by a central processing unit (CPU) requiring data to be read from the first clock domain is initiated. In such embodiments, it is advantageous that the detection is initiated without being performed continuously, and they assist the system to reduce the power consumption only if the execution of the checks is necessary, and the signal has been The second clock domain is allowed to enter a sleep mode after the transfer until the next transfer of a data signal is required, thus saving the power. Embodiments of the invention may be particularly adapted to an operational mode wherein the second clock domain requires a transfer of the data signal from the first clock domain, such as when the second clock domain leaves a sleep or Standby mode and requires a certain data signal, such as time, that provides the signal to initiate the preset period.
如先前所述，該預設期間隨著其的啟動，一般將被固定以及持續用於一串第二時脈週期。然而，實施例設想為一旦該第一時脈裡的一變遷已被偵測到時，即終止該轉移偵測，並且用以指示的必要的邏輯信號已通過該配置，亦即，在該預設期間終結之前。此係因為一旦其指示再次從該第一時脈域轉移該資料信號至該第二時脈域是安全的，該第一時脈較慢於該第二時脈的事實保證當該資料信號再次被轉移時不會有該第一時脈域裡的其他變遷，故此處沒有任何更長的偵測需要持續進行。As previously described, the preset period will generally be fixed and continued for a series of second clock cycles as it is activated. However, the embodiment contemplates that once a transition in the first clock has been detected, the branch detection is terminated and the necessary logic signal to indicate has passed the configuration, ie, in the pre- Set the period before the end. This is because the fact that the first clock is slower than the second clock once it is instructed to transfer the data signal from the first clock domain again to the second clock is guaranteed when the data signal is again There are no other transitions in the first clock domain when it is transferred, so there is no longer any detection needed to continue.
根據本發明的實施例，轉移的資料信號在同步時可以被改變在任何時間上，亦即在該預設期間，而不會影響該同步處理或該資料信號從該第一時脈域被轉移至該第二時脈域的再次轉移結果(假如有需要的話)，例如藉由造成該輸出信號裡的不穩定(meta-stability)。此不同於習知手握處理程序，其中放置一凍結在從該第一時脈域被轉移的資料信號上，例如經由該等忙碌旗標的使用，俾以執行該第一與第二時脈域間的同步的手握處理。其明確地增加了完成該轉移及因此造成該系統消耗電量之時間。值得領會的是，本發明移除這些限制而造成一個更快速且消耗較少電量的資料信號的轉移。According to an embodiment of the present invention, the transferred data signal can be changed at any time during synchronization, that is, during the preset period without affecting the synchronization process or the data signal is transferred from the first clock domain. The result of the retransmission to the second clock domain (if necessary), for example by makingThe meta-stability in the output signal. This differs from conventional hand-held handlers in which a freeze is placed on a data signal that is transferred from the first clock domain, such as via the use of the busy flag, to perform the first and second clock domains Synchronized hand grip processing. It explicitly increases the time to complete the transfer and thus the power consumption of the system. It is to be appreciated that the present invention removes these limitations resulting in a faster and less power-intensive transfer of data signals.
如先前所述一組實施例所述，靠著具有由該第二時脈而被計時的該偵測手段以及使用該第一時脈作為其輸出，該配置簡易地產生一“安全”同步信號以決定是否其需要從該第一時脈域再次轉移該資料至該第二時脈域。因此其在意該資料信號之狀態，其可以在該預設期間內改變，亦即其為位於該預設期間的末端時或在該預設期間內的其他時間時之該第一時脈域裡的該資料信號的值，假如該第一時脈週期裡已有一個轉移則該值被轉移至該第二時脈域，其通常係指該資料信號的值將被改變。假如在該預設期間裡該第一時脈週期裡沒有變遷，該資料信號維持初始被轉移通常意指該資料信號沒有被改變的值。然而，當該第一時脈裡的一個變遷被偵測到的情形下，該第一時脈域裡最接近的資料信號將隨著此變遷被轉移至該第二時脈域。As described in the previous set of embodiments, the configuration simply produces a "safe" synchronization signal by having the detection means timed by the second clock and using the first clock as its output. To determine if it needs to transfer the data from the first clock domain to the second clock domain again. Therefore, it cares about the state of the data signal, which can be changed within the preset period, that is, it is in the first clock domain at the end of the preset period or at other times within the preset period. The value of the data signal, if there is already a transition in the first clock cycle, the value is transferred to the second clock domain, which generally means that the value of the data signal will be changed. If there is no transition in the first clock cycle during the preset period, maintaining the data signal initially transferred generally means that the data signal has not been changed. However, when a transition in the first clock is detected, the closest data signal in the first clock domain will be transferred to the second clock domain along with the transition.
在該預設期間內自由改變該第一時脈域裡的該資料信號係不同於傳統的方法其中該被轉移的資料在該兩個時脈域的同步期間裡不允許被改變。其係因為該等同步處理，例如手握及/或包含數個忙碌旗標，係包含該被轉移的資料信號的檢查，也包含該等時脈週期。其設定數個限制在整個系統以及其使用上。舉例來說，需要一個CPU以探詢一個告訴該系統何時同步完成的旗標。本發明的系統不受這些限制，因此允許更高的自由度在其使用與架構上。The freely changing the data signal in the first clock domain during the preset period is different from the conventional method in which the transferred data is not allowed to be changed during the synchronization period of the two clock domains. Because it is equivalentStep processing, such as holding and/or containing a number of busy flags, is a check that includes the transferred data signal, and also includes the clock cycles. It sets several limits on the entire system and its use. For example, a CPU is needed to probe a flag that tells the system when synchronization is complete. The system of the present invention is not subject to these limitations, thus allowing for a higher degree of freedom in its use and architecture.
在一組實施例裡，該系統包括一手段用於儲存該資料信號，例如一儲存裝置或元件，以及該方法包括儲存該資料信號的步驟。在該資料信號被輸出至該第二時脈域之前，其允許該資料信號暫時地被儲存，用於任一或全部該初始轉移以及該後續轉移，假如需要的的話。該資料信號也可以被儲存在該預設期間裡，亦即當進行該第一時脈的檢查以及將該等邏輯信號通過該偵測手段。In one set of embodiments, the system includes a means for storing the data signal, such as a storage device or component, and the method includes the step of storing the data signal. Before the data signal is output to the second clock domain, it allows the data signal to be temporarily stored for any or all of the initial transfer and the subsequent transfer, if desired. The data signal may also be stored during the predetermined period, that is, when the first clock is checked and the logic signals are passed through the detecting means.
用於儲存來自於該第一時脈域的手段可包括任何合適的資料儲存元件、配置或裝置，其可在該第一時脈週期的不安全部分裡及/或在該預設期間裡用於儲存該資料信號，以當該檢查被啟動時及/或在該第一時脈的檢查已經被執行後使得該信號準備好被輸出至該第二時脈域。其可包括一暫存器，例如一個正反器或一個閂鎖器。對於一個被配置用以轉移一多位元匯流排的系統，多數個元件可根據該匯流排的大小而被提供，例如多個並聯的正反器。此一元件可以儲存該輸入信號直到其接收到表示轉移其至該第二時脈域是安全的一個信號，例如從該偵測手段接收。此外，一個保持可以被設定在該該儲存手段裡的該資料信號上以避免該轉移發生在該預設期間終結之前。該儲存手段可以接收該來自於該第一時脈域的資料信號，即該儲存手段和該第一時脈域可以包括數個分開的元件：一個用以接收該輸入信號以及一個用以儲存該輸入信號。然而此功能也可由該第一時脈域來執行以接收或儲存先前被傳送的資料信號。Means for storing the first clock domain may include any suitable data storage element, configuration or device that may be used in the unsafe portion of the first clock cycle and/or during the predetermined period The data signal is stored to cause the signal to be ready to be output to the second clock domain when the check is initiated and/or after the check of the first clock has been performed. It may include a register, such as a flip-flop or a latch. For a system configured to transfer a multi-bit bus, a plurality of components can be provided depending on the size of the bus, such as a plurality of parallel flip-flops. The component can store the input signal until it receives a signal indicating that it is safe to transfer it to the second clock domain, such as from the detection means. In addition, a fund that can be set in the storage meansThe signal is signaled to prevent the transfer from occurring before the end of the preset period. The storage means can receive the data signal from the first clock domain, that is, the storage means and the first clock domain can include a plurality of separate components: one for receiving the input signal and one for storing the input signal. However, this function can also be performed by the first clock domain to receive or store previously transmitted material signals.
當該資料信號被初始地轉移，其尚不知道是否此資料信號是安全而可以被系統所使用，即該初始轉移被冒險地產生並希望該第一時脈是位於其時間週期的安全部分，其歸因於該第一和第二時脈域的對應頻率一般而言相似。然而，假如該轉移被使用在該第一時脈裡的一個變遷上，該資料信號可能錯誤或不穩。在這些情況下其並非是一個好的構想來傳播該信號通過該系統，例如藉由讀取該信號被轉移之該第二匯流排。因此在一組實施例裡，該配置包括一手段用以避免該起始的轉移資料信號藉由該第二時脈域而被讀取。該藉由該第二時脈域而被讀取的資料信號上的區塊可包括一“預備(ready)”信號，例如當該區塊於適當位置時設定為零，以及當該資料信號已經被決定是安全並且準備好藉由該第二時脈域而被讀取時設定為一。該預備信號可以被連結至該偵測手段及/或該預設期間。舉例來說，假如該配置包括一計時器或計數器，該預備信號可以在一特別而和該預設期間相關的時間點上被發出，例如在該預設期間的終點時。When the data signal is initially transferred, it is not known whether the data signal is safe and can be used by the system, i.e., the initial transfer is risky and hopefully the first clock is in a safe part of its time period, It is generally similar due to the corresponding frequencies of the first and second clock domains. However, if the transfer is used on a transition in the first clock, the data signal may be erroneous or unstable. In these cases it is not a good idea to propagate the signal through the system, such as by reading the second bus that is transferred by the signal. Thus, in one set of embodiments, the configuration includes a means to prevent the initial transferred data signal from being read by the second clock domain. The block on the data signal read by the second clock domain may include a "ready" signal, such as zero when the block is in place, and when the data signal has been It is set to one when it is determined to be safe and ready to be read by the second clock domain. The preliminary signal can be coupled to the detecting means and/or the preset period. For example, if the configuration includes a timer or counter, the preliminary signal can be issued at a point in time that is particularly relevant to the preset period, such as at the end of the preset period.
一旦該第一時脈的檢查已進行且該預設期間已結束，任一該資料信號的初始轉移可知道是安全的，或是該後續轉移已進行，其如先前討論可知道是安全的，在讀取該資料信號的該第二時脈域上的區塊則可以被提出。Once the first clock has been checked and the preset periodHaving ended, the initial transfer of any of the data signals can be known to be safe, or the subsequent transfer has taken place, as previously discussed, it is known to be safe, on the second time domain in which the data signal is read. Blocks can be proposed.
2‧‧‧正緣偵測器2‧‧‧Positive edge detector
4‧‧‧向下計數器4‧‧‧down counter
6‧‧‧決策節點6‧‧‧ Decision node
8‧‧‧第一輸出8‧‧‧ first output
10‧‧‧第二輸出10‧‧‧second output
12‧‧‧第三輸出12‧‧‧ third output
14‧‧‧AND邏輯閘14‧‧‧AND logic gate
16‧‧‧OR邏輯閘16‧‧‧OR logic gate
18‧‧‧多工器18‧‧‧Multiplexer
20‧‧‧正反器20‧‧‧Fracture
22‧‧‧時間刻度22‧‧‧ time scale
在此參考示意圖來描述本發明的一個詳細的實施例，但僅是舉例：圖1係本發明一較佳實施例之一邏輯電路圖。DETAILED DESCRIPTION OF THE INVENTION A detailed embodiment of the present invention is described herein with reference to the drawings, but by way of example only, FIG.
圖2係圖1的邏輯電路相關的時序圖。FIG. 2 is a timing diagram related to the logic circuit of FIG. 1.
圖1顯示一個對應於本發明實施例一配置的邏輯電路示意圖。該配置被安排用以從一個第一時脈域裡的一個第一匯流排bus_slow轉移資料至一個第二時脈域裡的一個第二匯流排bus_fast。該第一時脈ck_slow的頻率小於該第二時脈ck_fast的頻率，該第一時脈ck_slow的通常頻率是32kHz，而該第二時脈ck_fast的通常頻率是16MHz。1 shows a schematic diagram of a logic circuit corresponding to the configuration of the embodiment of the present invention. The configuration is arranged to transfer data from a first busbus_slow in a first clock domain to a second busbus_fast in a second clock domain. The frequency of the first clockck_slow is less than the frequency of the second clockck_fast , the normal frequency of the first clockck_slow is 32 kHz, and the normal frequency of the second clockck_fast is 16 MHz.
該配置包括一個正緣偵測器2用於該第一時脈ck_slow，該正緣偵測器2將該時脈作為輸入。假如該第一時脈ck_slow裡的一個正緣已被偵測到，來自該正緣偵測器2的輸出posedge_detected為一，反之為零。該第二時脈ck_fast被使用於計時該正緣偵測器2，使得在該第二時脈的每一上升邊緣上，該輸入ck_slow之值被取樣並且和其在該第二時脈的先前上升邊緣上的值做比較。The configuration includes a positive edge detector 2 for the first clockck_slow , the positive edge detector 2 taking the clock as an input. If a positive edge in the first clockck_slow has been detected, the outputposedge_detected from the positive edge detector 2 is one, and vice versa. The second clockck_fast is used to time the positive edge detector 2 such that on each rising edge of the second clock, the value of the inputck_slow is sampled and its previous in the second clock The values on the rising edge are compared.
該配置也包括一個向下計數器4，其使其輸入是一初始信號start_sync，該信號指示同步處理要被啟動來轉移該資料。來自該向下計數器4的輸出sync_cnt是計數的值，其為整數且在每次計數時被減一。如圖1所示之實施例，該計數總是開始於三。該第二時脈ck_fast也被使用於計數該向下計數器4，亦即，在該第二時脈的每一上升邊緣，該向下計數器4將其輸出sync_cnt之值減去一。The configuration also includes a down counter 4 that causes its input to be an initial signalstart_sync indicating that synchronization processing is to be initiated to transfer the data. The outputsync_cnt from the down counter 4 is the counted value, which is an integer and is decremented by one each time it is counted. In the embodiment shown in Figure 1, the count always starts at three. The second clockck_fast is also used to count the down counter 4, i.e., at each rising edge of the second clock, the down counter 4 subtracts the value of its outputsync_cnt by one.
來自於該向下計數器4的該輸出sync_cnt被饋入至一決策節點6。依據來自該向下計數器4的輸出sync_cnt之值，具有三個輸出8、10、12來自於該決策節點6。假如來自於該向下計數器4的輸出sync_cnt等於零，該第一輸出8具有一個為一的值。假如來自於該向下計數器4的輸出sync_cnt等於三，該第二輸出10具有一個為一的值。假如來自於該向下計數器4的輸出sync_cnt不等於零，該第三輸出12具有一個為一的值。藉此將可領會，該來自該決策節點6的第二和第三輸出10、12可同時具有一個為一的值，亦即當來自於該向下計數器4的該輸出sync_cnt具有一個為三的值時。當來自於該向下計數器4的輸出sync_cnt等於零時，一個信號ready被輸出至該系統並指示來自該第一匯流排bus_slow的資料已經被轉移以及該配置已準備好用以接收另一初始信號start_sync。The outputsync_cnt from the down counter 4 is fed to a decision node 6. Depending on the value of the outputsync_cnt from the down counter 4, there are three outputs 8, 10, 12 from the decision node 6. If the outputsync_cnt from the down counter 4 is equal to zero, the first output 8 has a value of one. If the outputsync_cnt from the down counter 4 is equal to three, the second output 10 has a value of one. If the outputsync_cnt from the down counter 4 is not equal to zero, the third output 12 has a value of one. It will be appreciated from this that the second and third outputs 10, 12 from the decision node 6 can have a value of one at the same time, that is, when the outputsync_cnt from the down counter 4 has a three When the value is. When the outputsync_cnt from the down counter 4 is equal to zero, a signalready is output to the system and indicates that data from the first busbus_slow has been transferred and the configuration is ready to receive another initial signalstart_sync .
來自於該正緣偵測器2的輸出信號posedge_detected與來自於該決策節點6的第三輸出12結合於一AND邏輯閘14，來自於該AND閘14的輸出與來自於該決策節點6的第二輸出10結合在一個OR邏輯閘16上。來自於該OR閘16的輸出load_bus_fast被饋入至一個多工器18的選擇器輸入端。該多工器18的輸入為來自該第一匯流排bus_slow的資料信號以及輸出至該第二匯流排bus_fast的輸出資料信號。來自於該多工器18的輸出被饋入至一個由該第二時脈ck_fast計時的D型正反器20。該正反器20的Q輸出被輸出至該第二匯流排bus_fast。The output signalposedge_detected from the positive edge detector 2 is combined with a third output 12 from the decision node 6 in an AND logic gate 14, the output from the AND gate 14 and the first from the decision node 6. The two outputs 10 are combined on an OR logic gate 16. The outputload_bus_fast from the OR gate 16 is fed to the selector input of a multiplexer 18. The input of the multiplexer 18 is a data signal from the first busline bus_slow and an output data signal outputted to the second busline bus_fast . The output from the multiplexer 18 is fed to a D-type flip-flop 20 clocked by the second clockck_fast . The Q output of the flip-flop 20 is output to the second busbus_fast .
圖2顯示數個邏輯信號依序通過該系統，該系統之操作現在將參考圖1與圖2而被描述。一個代表性的時間刻度22被提供在50ns的分割刻度裡。如圖2所示和用於說明之目的，來自第二、較高頻率之時脈域4的第二時脈ck_fast的頻率係採取為16MHz，以及來自第一、較低頻率之時脈域8的第一時脈ck_slow的頻率係採取為1.5.MHz。在實際上，如在先前以詳細描述，這些頻率可能為更加地不同，但此處選擇這些更有比較性的值使得說明更方便。Figure 2 shows several logic signals sequentially passing through the system, the operation of which will now be described with reference to Figures 1 and 2. A representative time scale 22 is provided in a 50 ns split scale. As shown in FIG. 2 and for purposes of illustration, the frequency of the second clockck_fast from the second, higher frequency clock domain 4 is taken to be 16 MHz, and the clock domain 8 from the first, lower frequencies. The frequency of the first clockck_slow is taken as 1.5.MHz. In practice, these frequencies may be more different as previously described in detail, but selecting these more comparable values here makes the description more convenient.
起初該系統係處於一狀態，其中該多位元資料h9(一個十六進制的值)位於該第一匯流排bus_slow，以及該第二匯流排bus_fast為未知，亦即該匯流排裡的值來自於先前的轉移。該系統處於一個穩定狀態直到在565ns時，該初始信號start_sync由零轉變為一，藉此觸發該同步處理的啟動。典型上該初始化信號將藉由該第二時脈域(一般而言控制一較高電量的周邊系統)而產生，係在其離開一個睡眠模式以要求從該第一時脈域(一般而言一較低電量的時序電路)轉移該資料之時。在625ns時，該向下計數器4由該第二時脈ck_fast的下一個上升邊緣而被計時，使其從三開始向下計數，亦即在625ns時，來自於該向下計數器4的該輸出sync_cnt改變為三。該向下計數器4從三開始倒數係必需的，此係因為該正緣偵測器2使用該第二時脈ck_fast的兩個周期以使一個正緣變遷被偵測到，亦即用於使必需的邏輯信號通過其正反器。Initially, the system is in a state in which the multi-bit data h9 (a hexadecimal value) is located in the first busbus_slow , and the second busbus_fast is unknown, that is, the value in the bus bar. From the previous transfer. The system is in a steady state until at 565 ns, the initial signalstart_sync transitions from zero to one, thereby triggering the initiation of the synchronization process. Typically, the initialization signal will be generated by the second clock domain (generally controlling a higher power peripheral system) as it leaves a sleep mode to request from the first clock domain (generally A lower power sequential circuit) when the data is transferred. At 625 ns, the down counter 4 isclocked by the next rising edge of the second clockck_fast , causing it to count down from three, that is, at 625 ns, the output from the down counter 4Sync_cnt changes to three. The down counter 4 is required to count down from three, because the positive edge detector 2 uses two cycles of the second clockck_fast to cause a positive edge transition to be detected, that is, to make The necessary logic signal passes through its flip-flop.
來自該向下計數器4之為三的該輸出值sync_cnt造成該決策節點6的該第一輸出8具有一個為零的值以及該決策節點6的該第二與第三輸出10、12具有一個為一的值。不論來自該正緣偵測器2的輸出posedge_detected為何，該等輸入至該OR閘16皆造成該OR閘16的輸出值為一。該為一的值被饋入至該多工器18的選擇器輸入端使得該第一匯流排bus_slow裡的該資料信號h9被饋入至該正反器20的D輸入端，而使得在該第二時脈ck_fast的下一個上升邊緣時，該資料信號h9被轉移至該第二匯流排bus_fast。The output valuesync_cnt from the down counter 4 is three such that the first output 8 of the decision node 6 has a value of zero and the second and third outputs 10, 12 of the decision node 6 have one A value of one. Regardless of the outputposedge_detected from the positive edge detector 2, the input to the OR gate 16 causes the output value of the OR gate 16 to be one. The value of one is fed to the selector input of the multiplexer 18 such that the data signalh9 in the first bus barbus_slow is fed to the D input of the flip flop 20, so thatAt the next rising edge of the second clockck_fast , the data signalh9 is transferred to the second busbus_fast .
同時，在該第二時脈ck_fast的每一上升邊緣，該正緣偵測器2檢查該第一時脈ck_slow週期裡的一個正緣變遷。在670ns時，該第一時脈ck_slow具有一正緣變遷。在此範例裡，該變遷和該第一匯流排bus_slow裡的該資料信號從h9轉變為hC有關，但是在其他的情況裡，該資料信號可以維持該相同值。在750ns時，在計時該正緣偵測器2之該第二時脈ck_fast的兩個週期後之上升邊緣上，來自於該正緣偵測器2的輸出posedge_detected改變為一，表示該第一時脈ck_slow裡的該正緣變遷已被偵測到。該為一的值結合來自該決策節點6的該第三輸出12之為一的值(亦即在此時點該來自該向下計數器4的輸出sync_cnt為一，而不等於零)，造成該AND閘14具有一個值為一的輸出，並且該OR閘16也具有一個值為一的輸出load_bus_fast。此意指由於該第一時脈ck_slow裡的該正緣變遷發生在該第二時脈ck_fast裡的一個變遷，其中該資料信號從該第一匯流排bus_slow被初始轉移至該第二匯流排bus_fast，該第一匯流排裡的該資料被再次轉移。Meanwhile, at each rising edge of the second clockck_fast , the positive edge detector 2 checks a positive edge transition in the first clockck_slow period. At 670 ns, the first clockck_slow has a positive edge transition. In this example, the transition is related to the change of the data signal in the first busbus_slow fromh9 tohC , but in other cases, the data signal can maintain the same value. At 750 ns, on the rising edge after two cycles of timing the second clockck_fast of the positive edge detector 2, the outputposedge_detected from the positive edge detector 2 is changed to one, indicating the first This positive edge transition in the clockck_slow has been detected. The value of one is combined with the value of the third output 12 from the decision node 6 to one (ie, the output sync_cnt from the down counter 4 is one at this time, not equal to zero), resulting in the AND gate. 14 has an output of one value, and the OR gate 16 also has an outputload_bus_fast of one value. This means that since the first clock in theck_slow Change Change a positive edge occurs in the second clockck_fast, wherein the data signal is initially transferred from the first bus to the second busbus_fastbus_slow The data in the first bus is transferred again.
如同先前，一個為一的值load_bus_fast被饋入至該多工器18的該選擇器輸入端造成該第一匯流排bus_slow裡目前為hC的資料信號被饋入至該正反器20的D輸入端，使得在該第二時脈ck_fast的下一個上升邊緣時，該資料信號hC被轉移至該第二匯流排bus_fast。該第一時脈ck_slow的頻率非常低以確保該資料信號的轉移在該第一時脈的另外一個正緣變遷將發生之前被完成。As before, a value of oneload_bus_fast is fed to the selector input of the multiplexer 18 causing the data signal of the current busbarbus_slow to behC to be fed to the D input of the flip-flop 20 End, such that at the next rising edge of the second clockck_fast , the data signalhC is transferred to the second busbus_fast . The frequency of the first clockck_slow is very low to ensure that the transfer of the data signal is completed before another positive edge transition of the first clock will occur.
在812.5ns時，來自於該向下計數器4的該輸出sync_cnt已到達零，其造成來自於該決策節點6的該第一輸出8的值為一，表示該系統準備好接收一個新的初始信號，亦即該信號ready等於一。在此時點，當該預設期間已結束，該儲存在該正反器20的資料信號是一個有效且穩定的值，其接著被使用在該系統裡作為資料而被同步至該第二時脈ck_fast，例如，如先前所述地，在該第二時脈ck_fast的上升邊緣輸出至該第二匯流排bus_fast。當來自該向下計數器4的輸出sync_cnt為零時，來自該決策節點6的第二和第三輸出10、12為零，所以此時沒有新的資料信號可以從該第一匯流排bus_slow被轉移至該正反器20。因此，在一個實施例(未顯示)中，一個正緣變遷沒有發生在該預設期間內，亦即在該向下計數器4的輸出sync_cnt倒數期間裡，但當該向下計數器4的輸出sync_cnt為零時被偵測到，足夠的時間將經過在該資料信號被初始轉移在該預設期間的起點之後，此起點為使得在此情況下沒有資料毀損或不穩定的風險，此係因為該第一時脈ck_slow裡的正緣變遷沒有發生在該資料信號的該初始轉移的同一時間裡，且該第一匯流排bus_slow裡的資料值僅被改變(造成不穩定之原因)在該第一時脈ck_slow裡的一個變遷上。At 812.5 ns, the outputsync_cnt from the down counter 4 has reached zero, which causes the value of the first output 8 from the decision node 6 to be one, indicating that the system is ready to receive a new initial signal. That is, the signalready is equal to one. At this point, when the preset period has ended, the data signal stored in the flip-flop 20 is a valid and stable value, which is then used in the system as data to be synchronized to the second clock.Ck_fast , for example, is output to the second busbus_fast at the rising edge of the second clockck_fast as previously described. When the outputsync_cnt from the down counter 4 is zero, the second and third outputs 10, 12 from the decision node 6 are zero, so no new data signal can be transferred from the first busbus_slow at this time. To the flip-flop 20. Therefore, in one embodiment (not shown), a positive edge transition does not occur during the predetermined period, that is, during the countdown of the outputsync_cnt of the down counter 4, but when the output of the down counter 4 issync_cnt When it is zero, it is detected. Sufficient time will pass after the data signal is initially transferred at the beginning of the preset period. This starting point is such that there is no risk of data corruption or instability in this case. The positive edge transition in the first clockck_slow does not occur at the same time of the initial transfer of the data signal, and the data value in thebus_slow of the first bus is only changed (causing the cause of instability) at the first A change in the clockck_slow .
該技術領域具通常知識者由此將可以領會上述實施例僅係為了方便說明而舉例而已，本發明尚可有諸多變化。舉例來說，其並不一定需要提供一個最後的正反器用以輸出該被轉移的資料信號至該第二匯流排，其可以藉由任何其他資料儲存元件來執行，或甚至正好藉由開啟該電路使該輸入信號可以從該第一匯流排直接被轉移。該預設期間的長度可以是不同的值，特別地假如其依靠的元件型態被使用於偵測該第一時脈裡的一個變遷，即該時間被用於出自該元件的決策，或假如一或多個該等元件被計時在該第二時脈的全部變遷上。Those skilled in the art will appreciate that the above-described embodiments are merely illustrative for ease of illustration and the invention may be varied. For example, it is not necessary to provide a final flip-flop to output the transferred data signal to the second bus, which can be performed by any other data storage component, or even just by turning on the The circuit allows the input signal to be transferred directly from the first bus. The length of the preset period may be a different value, in particular if the component type it relies on is used to detect a transition in the first clock, ie the time is used for decision making from the component, or One or more of the elements are timed on all transitions of the second clock.
上述實施例僅係為了方便說明而舉例而已，本發明所主張之權利範圍自應以申請專利範圍所述為準，而非僅限於上述實施例。The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.
2‧‧‧正緣偵測器2‧‧‧Positive edge detector
4‧‧‧向下計數器4‧‧‧down counter
6‧‧‧決策節點6‧‧‧ Decision node
8‧‧‧第一輸出8‧‧‧ first output
10‧‧‧第二輸出10‧‧‧second output
12‧‧‧第三輸出12‧‧‧ third output
14‧‧‧AND邏輯閘14‧‧‧AND logic gate
16‧‧‧OR邏輯閘16‧‧‧OR logic gate
18‧‧‧多工器18‧‧‧Multiplexer
20‧‧‧正反器20‧‧‧Fracture
22‧‧‧時間刻度22‧‧‧ time scale
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1211425.2AGB2503473A (en) | 2012-06-27 | 2012-06-27 | Data transfer from lower frequency clock domain to higher frequency clock domain |
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| TW201401763Atrue TW201401763A (en) | 2014-01-01 |
| TWI604689B TWI604689B (en) | 2017-11-01 |
| Application Number | Title | Priority Date | Filing Date |
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| TW102121535ATWI604689B (en) | 2012-06-27 | 2013-06-18 | Data transfer between clock domains |
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|---|---|
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| EP (1) | EP2847664B1 (en) |
| JP (1) | JP6192065B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2528481B (en) | 2014-07-23 | 2016-08-17 | Ibm | Updating of shadow registers in N:1 clock domain |
| GB201907717D0 (en)* | 2019-05-31 | 2019-07-17 | Nordic Semiconductor Asa | Apparatus and methods for dc-offset estimation |
| TWI740564B (en)* | 2020-07-03 | 2021-09-21 | 鴻海精密工業股份有限公司 | Cross-clock-domain signal transmitting method, circuit, and electronic apparatus thereof |
| GB202014083D0 (en)* | 2020-09-08 | 2020-10-21 | Nordic Semiconductor Asa | Clock domain crossing |
| CN114461009B (en)* | 2022-01-07 | 2024-04-26 | 山东云海国创云计算装备产业创新中心有限公司 | A method for automatically identifying clock domain conversion for single-bit signals in FPGA |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5150313A (en) | 1990-04-12 | 1992-09-22 | Regents Of The University Of California | Parallel pulse processing and data acquisition for high speed, low error flow cytometry |
| US6112307A (en)* | 1993-12-30 | 2000-08-29 | Intel Corporation | Method and apparatus for translating signals between clock domains of different frequencies |
| US6260152B1 (en)* | 1998-07-30 | 2001-07-10 | Siemens Information And Communication Networks, Inc. | Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains |
| US6359479B1 (en)* | 1998-08-04 | 2002-03-19 | Juniper Networks, Inc. | Synchronizing data transfers between two distinct clock domains |
| DE10128396B4 (en)* | 2001-06-12 | 2005-02-24 | Infineon Technologies Ag | Method and circuit arrangement for transmitting data from a system operated with a first clock to a system operated with a second clock |
| US6928574B1 (en)* | 2001-08-23 | 2005-08-09 | Hewlett-Packard Development Company, L.P. | System and method for transferring data from a lower frequency clock domain to a higher frequency clock domain |
| US7085952B2 (en)* | 2001-09-14 | 2006-08-01 | Medtronic, Inc. | Method and apparatus for writing data between fast and slow clock domains |
| JP4122204B2 (en)* | 2002-09-27 | 2008-07-23 | 松下電器産業株式会社 | Synchronous circuit |
| US20040193931A1 (en)* | 2003-03-26 | 2004-09-30 | Akkerman Ryan L. | System and method for transferring data from a first clock domain to a second clock domain |
| JP2008544623A (en)* | 2005-06-13 | 2008-12-04 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method and apparatus for data transmission using clock domain |
| KR101086426B1 (en)* | 2007-01-23 | 2011-11-23 | 삼성전자주식회사 | Timing control device and method of controlling the change of state of serial data line in IC controller |
| US7809972B2 (en)* | 2007-03-30 | 2010-10-05 | Arm Limited | Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain |
| US8024597B2 (en)* | 2008-02-21 | 2011-09-20 | International Business Machines Corporation | Signal phase verification for systems incorporating two synchronous clock domains |
| US7733130B2 (en)* | 2008-03-06 | 2010-06-08 | Oracle America, Inc. | Skew tolerant communication between ratioed synchronous clocks |
| US8089378B1 (en)* | 2009-02-18 | 2012-01-03 | Marvell Israel (M.I.S.L) Ltd. | Synchronous multi-clock protocol converter |
| JP5483172B2 (en)* | 2009-10-19 | 2014-05-07 | 横河電機株式会社 | Data transfer apparatus and data transfer method |
| Publication number | Publication date |
|---|---|
| CN104412222B (en) | 2018-06-05 |
| EP2847664B1 (en) | 2018-04-18 |
| WO2014001765A1 (en) | 2014-01-03 |
| US9515812B2 (en) | 2016-12-06 |
| JP2015522188A (en) | 2015-08-03 |
| TWI604689B (en) | 2017-11-01 |
| US20150139373A1 (en) | 2015-05-21 |
| GB201211425D0 (en) | 2012-08-08 |
| EP2847664A1 (en) | 2015-03-18 |
| GB2503473A (en) | 2014-01-01 |
| KR20150037900A (en) | 2015-04-08 |
| CN104412222A (en) | 2015-03-11 |
| JP6192065B2 (en) | 2017-09-06 |
| Publication | Publication Date | Title |
|---|---|---|
| TWI604689B (en) | Data transfer between clock domains | |
| CN104597790B (en) | A kind of awakening method of serial ports controller and micro controller system based on it | |
| US11372461B2 (en) | Circuitry for transferring data across reset domains | |
| CN104283531A (en) | Clock Jitter and Power Supply Noise Analysis | |
| TWI585570B (en) | Data transfer between clock domains | |
| TWI585569B (en) | Data transfer between clock domains | |
| JP3604637B2 (en) | Asynchronous transfer device and asynchronous transfer method | |
| US20250315317A1 (en) | Asynchronous hardware control circuitry | |
| JPS626177A (en) | Trigger control device | |
| WO2023274928A1 (en) | Sampling signals | |
| JPH10303874A (en) | System for detecting synchronized edge between different clocks | |
| US6470459B1 (en) | Half-word synchronization method for internal clock | |
| CN114448403A (en) | Asynchronous wake-up circuit | |
| KR100418572B1 (en) | Asynchronous counting circuit | |
| JP2000347950A (en) | Serial interface | |
| JPH04169957A (en) | Microprocessor | |
| JP2010103824A (en) | Interface circuit, and clock/data supply method |
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |