TW201220292A - Liquid crystal display device - Google Patents

Abstract

The liquid crystal display device includes a pixel portion including first and second regions and light sources. The first and second regions each include a liquid crystal element whose transmissivity is controlled in accordance with a voltage of an image signal and a transistor for controlling holding of the voltage, whose off-state current is extremely low. The light sources perform first and second drivings: lights whose hues are different from each other are sequentially supplied to the first region in a first rotating order and the lights are sequentially supplied to the second region in a second rotating order which is different from the first rotating order in the first driving; and a light having a single hue is supplied consecutively to one or both of the first and second regions in the second driving. The period for holding the voltage is different between the first and second drivings.

Description

Translated fromChinese

201220292 六、發明說明： 【發明所屬之技術領域】 本發明有關包含電晶體於像素中之主動矩陣液晶顯示 裝置。 【先前技術】 在透射式液晶顯示裝置中，背光的功率消耗會大大地 影響整個液晶顯示裝置之功率消耗，且因此，對於功率消 耗的降低，在面板內之光損失的降低係重要的。在面板內 之光的損失係由於層間絕緣膜中之光折射，濾色片中之光 吸收，或其類似者而造成。原則上，光損失係在濾色片中 特別地大，其中藉由顏料的光吸收係使用以自白色光而提 取具有預定範圍之波長的光。實際上，來自背光的光之 70%或更多的能量係由濾色片所吸收。如上述，濾色片會 阻礙液晶顯示裝置之功率消耗的降.低。 爲了要避色由於濾色片之光損失的問題，場順序驅動 (FS驅動）係有效的。FS驅動係藉由順序點亮其中色相 係彼此互相不同的複數個光源，而顯示彩色影像之驅動方 法。在該FS驅動中，無需一定要使用濾色片，此將導致 面板內之光損失的降低，以致可增進面板的透射率。從而 ，可增進來自背光的光的使用效率，且可降低整個液晶顯 示裝置的功率消耗。進一步地，依據FS驅動，各個彩色 的影像可每一像素地顯示，以致可以以高清晰度而執行影 像顯示。 -5- 201220292 在專利文獻1中所揭示的係液晶顯示裝置，其中顯示 模式係切換於正常情況中之使用場順序顯示模式的彩色影 像顯示，與其中影像係正文或其類似物之情況中的單色顯 示之間。 〔參考文件〕 專利文獻1 :日本公開專利申請案第2003-248463號 【發明內容】 然而，針對各個彩色之影像而不合成它們的分離感覺 ，則可能會發生所謂的彩色中斷於FS驅動中。尤其，在 顯示移動影像中，彩色中斷會更易於顯著地發生。 進一步地，當與使用濾色片的情況中之功率消耗相較 時，則依據場順序驅動，可降低液晶顯示裝置的功率消耗 。惟’隨著移動式電子裝置的普及，針對液晶顯示裝置之 更低功率消耗的需求程度正變高，且在功率消耗中之更多 的降低亦正被要求著。 鑑於上述，本發明一實施例之一目的在於提供可防止 影像品質之劣化的液晶顯示裝置，及其驅動方法。本發明 一實施例之另一目的在於提供可降低功率消耗的液晶顯示 裝置，及其驅動方法。 依據本發明一實施例之液晶顯示裝置包含背光，該背 光包含複數個光源，而該複數個光源之光的色相係彼此互 相不同。進一步地，該等光源的驅動方法係在全彩色影像 顯不與單色影像顯示之間切換。 -6 -201220292 VI. Description of the Invention: [Technical Field] The present invention relates to an active matrix liquid crystal display device including a transistor in a pixel. [Prior Art] In a transmissive liquid crystal display device, the power consumption of the backlight greatly affects the power consumption of the entire liquid crystal display device, and therefore, the reduction in power loss in the panel is important for the reduction in power consumption. The loss of light in the panel is caused by light refracting in the interlayer insulating film, light absorption in the color filter, or the like. In principle, the light loss is particularly large in the color filter in which the light absorption by the pigment is used to extract light having a predetermined range of wavelengths from white light. In fact, 70% or more of the energy from the backlight is absorbed by the color filter. As described above, the color filter hinders the drop in power consumption of the liquid crystal display device. In order to avoid the problem of light loss due to the color filter, the field sequential drive (FS drive) is effective. The FS drive system displays a driving method of a color image by sequentially lighting a plurality of light sources in which the hue systems are different from each other. In the FS drive, it is not necessary to use a color filter, which causes a reduction in light loss in the panel, so that the transmittance of the panel can be improved. Thereby, the use efficiency of light from the backlight can be improved, and the power consumption of the entire liquid crystal display device can be reduced. Further, according to the FS drive, images of respective colors can be displayed every pixel, so that image display can be performed with high definition. -5-201220292 A liquid crystal display device disclosed in Patent Document 1, wherein the display mode is switched to a color image display using a field sequential display mode in a normal case, and in the case where the image system text or the like Between monochrome displays. [Reference Document] Patent Document 1: Japanese Laid-Open Patent Application No. 2003-248463. SUMMARY OF THE INVENTION However, so-called color interruption may occur in the FS drive for images of respective colors without synthesizing their separation feeling. In particular, in displaying moving images, color breaks are more likely to occur significantly. Further, when compared with the power consumption in the case of using the color filter, the power consumption of the liquid crystal display device can be lowered by driving in accordance with the field order. However, with the spread of mobile electronic devices, the demand for lower power consumption for liquid crystal display devices is becoming higher, and more reduction in power consumption is also required. In view of the above, it is an object of an embodiment of the present invention to provide a liquid crystal display device capable of preventing deterioration of image quality, and a method of driving the same. Another object of an embodiment of the present invention is to provide a liquid crystal display device which can reduce power consumption, and a driving method thereof. A liquid crystal display device according to an embodiment of the invention includes a backlight, the back light comprising a plurality of light sources, and the hue of the light of the plurality of light sources are different from each other. Further, the driving method of the light sources is switched between full color image display and monochrome image display. -6 -

S 201220292 在全彩色影像顯示的情況中， 個區域，且光源的照明係每一區域 發明之一實施例中，像素部係畫分 區，而色相係彼此互相不同的複數 而依序地供應至第一區，且色相係 個光係以與該第一旋轉順序不同的 供應至第二區。 在單色影像顯不的情況中，色 數個光的其中至少一者係連續地供 一區地供應。 進一步地，在本發明之一實施 中單色影像係靜止影像的情況中， 色影像係移動影像的情況中之驅動 在本發明之一實施例中’爲了要抑 及用以控制所施加至該液晶元件之 狀態電流極低的絕緣閘極場效應電 電晶體），係設置於液晶顯示裝置 狀態電流極低的電晶體可使其中施 保持的週期能增加。因而’例如， 影像資訊之影像信號係針對若干連 素部的情況中，與靜止影像的情況 的驅動頻率，換言之，可以以針對 寫入而維持影像顯示。 該電晶體包含半導體材料於通 像素部係畫分成爲複數 地控制。特定地，在本 成爲至少第一區及第二 個光係以第一旋轉順序 彼此互相不同的該複數 第二旋轉順序而依序地 相係彼此互相不同的複 應至整個像素部，或每 例中，驅動頻率係在其 減低成爲比在其中該單 頻率更低。進一步地， 制驅動頻率，液晶元件 電壓的保持之其中截止 晶體（下文中將簡稱爲 中的像素部之中。截止 加至液晶元件之電壓所 在其中各自具有相同的 續像框週期而寫入至像 一樣地，甚至可以以低 一'定週期之少數的影像 道形成區之中，而該半 201220292 導體材料具有比矽半導體之能隙更寬的能隙，且具有比矽 半導體之本徵載子密度更低的本徵載子密度。透過包含具 有上述特徵之半導體材料的該通道形成區。可實現其中截 止電流係極低的電晶體。做爲該半導體材料.的實例，可給 定氧化物半導體，該氧化物半導體具有矽之能隙的約略三 倍大之能隙。具有上述結構之電晶體係使用做爲用以保持 所施加至液晶元件之電壓的開關元件，而當與使用利用諸 如矽或鍺之普通半導體材料的電晶體之情況相比較時，可 藉以進一步防止液晶元件中所累積之電荷的漏洩。 具體而言，依據本發明一實施例之液晶顯示裝置包含 面板和複數個光源，該面板係設置有像素部及用以控制影 像信號對像素區之輸入的驅動器電路，以及該複數個光源 係用以供應色相彼此相互不同的光至像素部。該像素部包 含液晶元件和電晶體，該液晶元件的透射率係依據影像信 號的電壓而控制，以及該電晶體係用以控制電壓的保持。 該電晶體的通道形成區包含例如諸如氧化物半導體之半導 體材料，其能隙係比矽半導體的能隙更寬，且其本徵載子 密度係比矽半導體的本徵載子密度更低》 進一步特定地，在依據本發明一實施例之液晶顯示裝 置的驅動方法中，像素部係畫分成爲至少第一區及第二區 ，在全彩色影像顯示的情況中，色相係彼此互相不同的複 數個光係以第一旋轉順序而依序地供應至第一區，且色相 係彼此互相不同的複數個光亦係以與第一旋轉順序不同的 第二旋轉順序而依序地供應至第二區；在單色影像顯示的S 201220292 In the case of full-color image display, the area is illuminated, and the illumination of the light source is one of the embodiments of the invention. In the embodiment of the invention, the pixel portion is divided into regions, and the hue system is different from each other and sequentially supplied to the first One zone, and the hue system is supplied to the second zone in a different order from the first rotation sequence. In the case where a monochrome image is not displayed, at least one of the chromatic numbers of light is continuously supplied for one area. Further, in the case where the monochrome image is a still image in the implementation of the present invention, the driving in the case of the color image moving image is in the embodiment of the present invention 'in order to suppress the application to the An insulating gate field effect transistor in which the state of the liquid crystal element is extremely low is a transistor in which the current is extremely low in the state of the liquid crystal display device, and the period in which the holding is maintained can be increased. Therefore, for example, in the case where the video signal of the video information is for a plurality of connected parts, the driving frequency of the case of the still picture, in other words, the image display can be maintained for writing. The transistor includes a semiconductor material which is controlled in plural by the pixel portion. Specifically, in the plural second rotation order in which at least the first region and the second light system are different from each other in the first rotation order, the phases are mutually different from each other to the entire pixel portion, or each In the example, the drive frequency is reduced to be lower than the single frequency in it. Further, the driving frequency is set, and the liquid crystal element voltage is held in which the crystal is cut off (hereinafter, it will be simply referred to as the middle of the pixel portion. The voltage applied to the liquid crystal element is turned off, and each has the same sequel period and is written to the image. Similarly, it can even be formed in a small number of image channel formation regions with a lower period of one, and the half 201220292 conductor material has a wider energy gap than the energy gap of the germanium semiconductor, and has an intrinsic carrier than the germanium semiconductor. a lower density intrinsic carrier density. The channel forming region containing the semiconductor material having the above characteristics can be realized. A transistor in which the off current is extremely low can be realized. As an example of the semiconductor material, a given oxide can be given. a semiconductor having an energy gap of about three times the energy gap of the germanium. The electromorphic system having the above structure is used as a switching element for maintaining a voltage applied to the liquid crystal element, and when used with When the crystal of the ordinary semiconductor material of bismuth or bismuth is compared, the charge accumulated in the liquid crystal element can be further prevented Specifically, a liquid crystal display device according to an embodiment of the invention includes a panel and a plurality of light sources, the panel is provided with a pixel portion and a driver circuit for controlling input of the image signal to the pixel region, and the plurality of The light source is configured to supply light having different hue to each other to the pixel portion. The pixel portion includes a liquid crystal element and a transistor, the transmittance of the liquid crystal element is controlled according to a voltage of the image signal, and the electric crystal system is used for controlling the voltage. The channel formation region of the transistor comprises, for example, a semiconductor material such as an oxide semiconductor, the energy gap is wider than that of the germanium semiconductor, and its intrinsic carrier density is more than the intrinsic carrier density of the germanium semiconductor. Further, in a driving method of a liquid crystal display device according to an embodiment of the present invention, the pixel portion is divided into at least a first region and a second region, and in the case of full color image display, the hue systems are mutually mutually a plurality of different light systems are sequentially supplied to the first zone in a first rotation order, and the hue systems are different from each other Also with the optical system different from a first order of rotation and a second rotation sequence sequentially supplied to the second region; displaying a monochromatic image

-8- S 201220292 情況中，具有單一色相的光係連續地供應至整個像素部’ 或每一區地供應。此外，在一定週期中之影像信號的寫入 次數係切換於其中影像信號包含用於第一單色影像之資料 的情況，與其中影像信號包含用於第二單色影像之資料的 情況之間。 注意的是，在接受諸如用作電子施體（施體）之水分 或氫的雜質之降低，及要減低氧缺乏之氧的添加之後的氧 化物半導體（純化的OS)係本徵（i型）半導體或實質i 型半導體。因此，使用該氧化物半導體的電晶體具有極低 的截止狀態電流。具體而言，藉由二次離子質譜測定法（ SIMS )所測量之氧化物半導體中的氫濃度係小於或等於5 xl019/cm3，較佳地係小於或等於5xl018/cm3，進一步較佳 地係小於或等於5x1 017/cm3，仍進一步較佳地係小於或等 於lxl016/cm3。此外，藉由霍爾（Hall )效應測量法所測 量之氧化物半導體膜的載子密度係小於lxl〇14/cm3，較佳 地係小於lxl〇12/cm3，進一步較佳地係小於 lxlO^/cm3** 再者，該氧化物半導體的能隙係2eV或更大，較佳地係 2.5eV或更大，進一步較佳地係3eV或更大。透過接受諸 如水分或氫之雜質濃度的充分降低及氧缺乏的減低之後的 氧化物半導體膜，可降低該電晶體的截止狀態電流。 在此，將敘述該氧化物半導體膜中之氫濃度的分析》 在氧化物半導體膜及導電膜中之氫濃度係藉由S IMS而測 量。已知的是，使用SIMS原則上係難以獲得取樣的表面 附近，或藉由不同材料所形成的堆疊膜之間的介面附近之 -9 - 201220292 資料。因此，在其中於厚度方向中之膜的氫濃度係藉由 SIMS而分析的情況中，係使用其中數値並未重大改變且 係幾乎穩定之膜的區域中之平均値做爲氫濃度。進一步地 ，在其中膜之厚度小的情況中，於某些情況中，由於鄰接 的膜之氫濃度的影響，無法發現其中可獲得幾乎相同之値 的該區域；在該情況中，係使用該膜之區域的氫濃度之最 大値或最小値做爲該膜的氫濃度。再者，在其中具有最大 値之山形尖峰或具有最小値之谷形尖端並不存在於膜的區 域中之情況中，係使用反曲點之値做爲氫濃度。 使用接受諸如氫或水分之雜質的降低及要減低氧缺乏 之氧的添加之後的該氧化物半導體膜做爲主動層，則各式 各樣的實驗可實際證明電晶體之低截止狀態電流。例如， 即使具有具備ΐχΐ〇δ微米之通道寬度及1〇微米之通道長 度的元件，在從1伏特（ν)至ίο伏特（V)之源極電極 與汲極電極間的電壓（汲極電壓）範圍中，截止狀態電流. (當閘極電極與源極電極之間的電壓係〇伏特或更小時之 汲極電流）亦可小於或等於半導體參數分析儀的測量極限 ，亦即，小於或等於ΐχΐ(Γ13安培（Α)。在該情況中，可 發現到的是，對應於藉由電晶體之通道寬度而除截止狀態 電流所獲得的値之截止狀態電流密度係小於或等於 ΙΟΟζΑ/μηι。此外，電容器和電晶體係彼此互相連接，且該 截止狀態電流密度係藉由使用其中流進電容器或自電容器 流出的電荷係由電晶體所控制之電路而予以測量。在該測 量中，上述之氧化物半導體膜係使用做爲電晶體中的通道-8- S 201220292 In the case, a light system having a single hue is continuously supplied to the entire pixel portion' or each of the regions. In addition, the number of writes of the image signal in a certain period is switched between the case where the image signal contains data for the first monochrome image, and the case where the image signal contains data for the second monochrome image. . Note that the oxide semiconductor (purified OS) is intrinsic after receiving the reduction of impurities such as water or hydrogen used as an electron donor (donor), and the addition of oxygen to reduce oxygen deficiency (i Type) semiconductor or substantially i-type semiconductor. Therefore, the transistor using the oxide semiconductor has an extremely low off-state current. Specifically, the concentration of hydrogen in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is less than or equal to 5 x 1 019 / cm 3 , preferably less than or equal to 5 x 1018 / cm 3 , and further preferably Less than or equal to 5x1 017/cm3, still more preferably less than or equal to lxl016/cm3. Further, the carrier density of the oxide semiconductor film measured by the Hall effect measurement method is less than lxl 〇 14 / cm 3 , preferably less than l x l 〇 12 / cm 3 , and further preferably less than l x l O ^ /cm3** Further, the oxide semiconductor has an energy gap of 2 eV or more, preferably 2.5 eV or more, further preferably 3 eV or more. The off-state current of the transistor can be lowered by receiving an oxide semiconductor film having a sufficient reduction in the concentration of impurities such as moisture or hydrogen and a decrease in oxygen deficiency. Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be described. The hydrogen concentration in the oxide semiconductor film and the conductive film is measured by S IMS . It is known that the use of SIMS is in principle difficult to obtain near the surface of the sample, or near the interface between the stacked films formed by different materials -9 - 201220292 data. Therefore, in the case where the hydrogen concentration of the film in the thickness direction is analyzed by SIMS, the average enthalpy in the region in which the number of enthalpy is not significantly changed and which is almost stable is used as the hydrogen concentration. Further, in the case where the thickness of the film is small, in some cases, due to the influence of the hydrogen concentration of the adjacent film, the region in which almost the same flaw can be obtained cannot be found; in this case, the use is The maximum or minimum hydrogen concentration in the region of the membrane is taken as the hydrogen concentration of the membrane. Further, in the case where the mountain-shaped peak having the largest ridge or the valley-shaped tip having the smallest ridge does not exist in the region of the film, the enthalpy of the inflection point is used as the hydrogen concentration. The oxide semiconductor film after the addition of impurities such as hydrogen or moisture and the addition of oxygen to reduce oxygen deficiency is used as the active layer, and various experiments can actually prove the low off-state current of the transistor. For example, even with an element having a channel width of ΐχΐ〇δ micron and a channel length of 1 〇 micron, the voltage between the source electrode and the drain electrode from 1 volt (ν) to ίοV (V) (the drain voltage) In the range, the off-state current. (When the voltage between the gate electrode and the source electrode is 〇V or less, the threshold current is also less than or equal to the measurement limit of the semiconductor parameter analyzer, ie, less than or Is equal to ΐχΐ (Γ13 amps (Α). In this case, it can be found that the off-state current density corresponding to the off-state current obtained by the channel width of the transistor is less than or equal to ΙΟΟζΑ/μηι Further, the capacitor and the electro-crystalline system are connected to each other, and the off-state current density is measured by using a circuit in which the electric charge flowing into or from the capacitor is controlled by the transistor. In the measurement, the above The oxide semiconductor film is used as a channel in the transistor

-10- S 201220292 形成區’且該電晶體的截止狀態電流密度係測量自每 位時間之電容器的電荷量之改變。結果，所發現到的 在其中於電晶體之源極電極與汲極電極間的電壓係3 的情況中，能獲得每一微米數十1〇·24安培（yA/μιη) 低的截止狀態電流密度。因此，在有關本發明之一實 的半導體裝置中，包含氧化物半導體膜做爲主動層之 體的截止狀態電流密度可根據源極電極與汲極電極間 壓而降低至小於或等於100 yA/μιη，較佳地小於或等方 yA/μπι，或進一步較佳地小於或等於1 yA/μιη。因而 含氧化物半導體膜做爲主動層之電晶體的截止狀態電 極低於使用具有晶體性之矽的電晶體之截止狀態電流。 做爲氧化物半導體，可使用以下者：氧化銦；氧 :氧化鋅；諸如In-Zn爲主氧化物半導體，Sn-Zn爲 化物半導體，Al-Zn爲主氧化物半導體，Zn-Mg爲主 物半導體，Sn-Mg主氧化物半導體，In-Mg爲主氧化 導體，或In-Ga爲主氧化物半導體之二元金屬氧化物 如In-Ga-Zn爲主氧化物半導體（亦稱爲IGZO) ，In Ζη爲主氧化物半導體，in_Sn-Zn爲主氧化物半導體， Ga-Zn爲主氧化物半導體，Al-Ga-Zn爲主氧化物半導 Sn-Al-Zn爲主氧化物半導體，In-Hf_Zn爲主氧化物半 ，In-La-Zn爲主氧化物半導體，In-Ce-Zn爲主氧化物 體，Ιη-Pr-Zn爲主氧化物半導體，In-Nd-Zn爲主氧化 導體’ In-Sm-Zn爲主氧化物半導體，In-Eu-Zn爲主氧 半導體，In-Gd-Zn爲主氧化物半導體，In-Tb-Zn爲主 一單 是， 伏特 之更 施例 電晶 之電 令10 ，包 流係 I 化錫 主氧 氧化 物半 :諸 1-A1- Sn- 體， 導體 半導 物半 化物 氧化 -11 - 201220292 物半導體’ In-Dy-Zn爲主氧化物半導體，ιη_Η〇·Ζη爲主氧 化物半導體’ In-Er-Zn爲主氧化物半導體，In_Tm-Zn爲主 氧化物半導體，In-Yb-Zn爲主氧化物半導體，或In_Lu-Zn 爲主氧化物半導體之二兀金屬氧化物；或諸如In-Sn-Ga-Zn爲主氧化物半導體，In-Hf-Ga-Zn爲主氧化物半導體， In-Al-Ga-Zn爲主氧化物半導體，In-Sn-Al-Zn爲主氧化物 半導體，In-Sn-Hf-Zn爲主氧化物半導體，或In_Hf-Al-Zn 爲主氧化物半導體之四元金屬氧化物" 注意的是’在此，例如In-Ga-Zn爲主氧化物意指包 含銦（In)、鎵（Ga)、及鋅（Zn)之氧化物，且在In、 Ga、及Zn的組成比率上並無特殊的限制。進一步地，該 In-Ga-Zn爲主氧化物可包含除了 In、Ga、及Zn之外的金 屬元素。做爲氧化物半導體，可使用藉由化學式 InM03(Zn0)m ( m>0，m無需一定係自然數）所表示之材 料。在此，Μ代表選自 Ga、鐵（Fe)、錳（Μη )、或鈷 (Co)之一或更多個金屬元素。選擇性地，做爲氧化物半 導體，可使用藉由化學式In2Sn05(Zri0)n ( η>0，η係自然 數）所表示之材料。 在依據本發明一實施例的液晶顯示裝置中，像素部係 畫分成爲複數個區域，且色相彼此相互不同的光係每一區 域地被依序供應，藉以顯示彩色影像。因此’在每一時間 ，所供應至彼此相互鄰接之區域的個別光之色相可彼此互 相不同。因而，可防止針對各個彩色之影像而不合成它們 的分離感覺，以致可防止可能發生於顯示移動影像中之彩-10- S 201220292 Forming the region' and the off-state current density of the transistor is a measure of the change in the amount of charge of the capacitor from each time. As a result, in the case where the voltage system 3 between the source electrode and the drain electrode of the transistor is found, an off-state current of tens of 〇24 amps (yA/μιη) per micron can be obtained. density. Therefore, in the semiconductor device according to the present invention, the off-state current density of the body including the oxide semiconductor film as the active layer can be reduced to less than or equal to 100 yA/ depending on the voltage between the source electrode and the drain electrode. Μιη, preferably less than or equal to yA/μπι, or further preferably less than or equal to 1 yA/μιη. Therefore, the off-state electrode of the transistor containing the oxide semiconductor film as the active layer is lower than the off-state current of the transistor using the crystal. As the oxide semiconductor, the following may be used: indium oxide; oxygen: zinc oxide; such as In-Zn as the main oxide semiconductor, Sn-Zn as the compound semiconductor, Al-Zn as the main oxide semiconductor, and Zn-Mg as the main Semiconductor, Sn-Mg main oxide semiconductor, In-Mg is the main oxide conductor, or In-Ga is the main oxide semiconductor binary metal oxide such as In-Ga-Zn main oxide semiconductor (also known as IGZO) ), In Ζη is the main oxide semiconductor, in_Sn-Zn is the main oxide semiconductor, Ga-Zn is the main oxide semiconductor, and Al-Ga-Zn is the main oxide semi-conductive Sn-Al-Zn as the main oxide semiconductor. In-Hf_Zn is a main oxide half, In-La-Zn is a main oxide semiconductor, In-Ce-Zn is a main oxide body, Ιη-Pr-Zn is a main oxide semiconductor, and In-Nd-Zn is a main oxide conductor. 'In-Sm-Zn is the main oxide semiconductor, In-Eu-Zn is the main oxygen semiconductor, In-Gd-Zn is the main oxide semiconductor, and In-Tb-Zn is the main one. Crystal Electric Command 10, Bulk Flow System I Tin Tin Oxygen Oxide Half: All 1-A1-Sn-Body, Conductor Semiconductor Semi-Chemistry Oxide-11 - 201220292 Semiconductor In-Dy-Zn is a main oxide semiconductor, and ιη_Η〇·Ζη is a main oxide semiconductor 'In-Er-Zn is a main oxide semiconductor, In_Tm-Zn is a main oxide semiconductor, and In-Yb-Zn is a main oxide. a semiconductor, or a germanium metal oxide of In_Lu-Zn as a main oxide semiconductor; or a main oxide semiconductor such as In-Sn-Ga-Zn, an In-Hf-Ga-Zn main oxide semiconductor, In-Al- Ga-Zn is a main oxide semiconductor, In-Sn-Al-Zn is a main oxide semiconductor, In-Sn-Hf-Zn is a main oxide semiconductor, or In_Hf-Al-Zn is a ternary metal of a main oxide semiconductor. Oxide " Note that 'herein, for example, In-Ga-Zn as a main oxide means an oxide containing indium (In), gallium (Ga), and zinc (Zn), and is in In, Ga, and There is no particular limitation on the composition ratio of Zn. Further, the In-Ga-Zn main oxide may contain a metal element other than In, Ga, and Zn. As the oxide semiconductor, a material represented by the chemical formula InM03(Zn0)m (m>0, m does not need to be a natural number) can be used. Here, Μ represents one or more metal elements selected from the group consisting of Ga, iron (Fe), manganese (?n), or cobalt (Co). Alternatively, as the oxide semiconductor, a material represented by the chemical formula In2Sn05(Zri0)n ( η > 0, η-system natural number) can be used. In a liquid crystal display device according to an embodiment of the present invention, a pixel portion is divided into a plurality of regions, and light regions different in hue from each other are sequentially supplied for each region to display a color image. Therefore, the hue of the individual lights supplied to the regions adjacent to each other can be different from each other at each time. Therefore, it is possible to prevent images for respective colors without synthesizing their separation feelings, so that color which may occur in displaying moving images can be prevented.

-12- S 201220292 色中斷發生。 在其中彩像影像顯示係透過色相彼此互相不同的複數 個光源而執行的情況中，與透過單一彩色光源及濾光片之 結合的情況不一樣地，複數個光源需依序地被切換而開啓 。進一步地，切換該等光源的頻率需高於使用單一彩色光 源之情況中的像框頻率。例如，假定在使用單一彩色光源 的情況中之像框頻率係60Hz時，則切換該等光源的頻率 係該像框頻率的三倍高，亦即，180Hz於具有紅色、綠色 、及藍色光源的FS驅動法之中。因此，驅動器電路亦係 依據上述該等光源的頻率而操作，此將導致驅動器電路操 作於極高的頻率處。因而，在驅動器電路中的功率消耗易 於高於在透過單一彩色光源及濾色片之結合的情況中之驅 動器電路中的功率消耗。 然而，依據本發明之一實施例，係使用截止狀態電流 極低的電晶體，而可藉以延長所施加至液晶元件之電壓的 保持週期。因此，可將用以顯示靜止影像之驅動頻率減低 至低於用以顯示移動影像之驅動頻率的頻率。因而，可獲 得功率消耗低之液晶顯示裝置。 【實施方式】 在下文中，將參照附圖來詳細敘述本發明之實施例和 實例。然而，本發明並未受限於以下說明，且熟習於本項 技藝之該等人士將易於瞭解的是，可各式各樣地改變模式 和細節而不會背離本發明之範疇及精神。從而，本發明不 -13- 201220292 應被解讀爲受限於下文之實施例和實例的說明。 (實施例1 ) 〈液晶顯示裝置的結構實例〉 第1圖中所描繪的液晶顯示裝置400包含複數個影像 記億體401，影像資料選擇電路402 ’選擇器403 ’ CPU 404，控制器405，面板406，背光407，及背光控制電路 408 « 輸入至液晶顯示裝置400之用於全彩色影像的影像資 料（全彩色影像資料410)係儲存於複數個影像記億體 401之中。該全彩色影像資料410包含應於個別色相之影 像資料。對應於個別色相之影像資料係儲存於個別的影像 記憶體4 0 1之中。 做爲影像記億體401，例如，可使用諸如動態隨機存 取記億體（DRAM)或靜態隨機存取記憶體（SRAM)之記 億體電路。 影像資料選擇電路402依據來自控制器405之命令而 讀取儲存於複數個影像記憶體401中且對應於個別色相的 全彩色影像資料，並傳送該全彩色影像資料至選擇器403 〇 此外，對應於單色影像之影像資料（單色影像資料 411)亦係輸入至液晶顯示裝置400。然後，該單色影像資 料411被輸入至選擇器403。 注意的是，全彩色影像意指以具有不同色相之複數個 -14--12- S 201220292 Color break occurred. In the case where the color image display is performed by a plurality of light sources whose hue is different from each other, a plurality of light sources are sequentially switched and turned on unlike the case of combining a single color light source and a filter. . Further, the frequency of switching the light sources is higher than the frame frequency in the case of using a single color light source. For example, assuming that the frame frequency is 60 Hz in the case of using a single color light source, the frequency of switching the light sources is three times higher than the frame frequency, that is, 180 Hz in FS with red, green, and blue light sources. Driven by the law. Therefore, the driver circuit is also operated in accordance with the frequency of the above-described light sources, which will cause the driver circuit to operate at extremely high frequencies. Thus, the power consumption in the driver circuit tends to be higher than in the driver circuit in the case of a combination of a single color source and a color filter. However, according to an embodiment of the present invention, a transistor having an extremely low off-state current is used, and the sustain period of the voltage applied to the liquid crystal element can be extended. Therefore, the driving frequency for displaying a still image can be reduced to be lower than the frequency for displaying the driving frequency of the moving image. Thus, a liquid crystal display device with low power consumption can be obtained. [Embodiment] Hereinafter, embodiments and examples of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited by the following description, and those skilled in the art will readily appreciate that the modes and details may be varied in various ways without departing from the scope and spirit of the invention. Thus, the present invention is not to be construed as being limited by the description of the embodiments and examples below. (Embodiment 1) <Configuration Example of Liquid Crystal Display Device> The liquid crystal display device 400 depicted in Fig. 1 includes a plurality of image recording units 401, image data selection circuit 402 'selector 403' CPU 404, controller 405, The panel 406, the backlight 407, and the backlight control circuit 408 « The image data (full color image data 410) for the full-color image input to the liquid crystal display device 400 is stored in a plurality of image frames 401. The full color image data 410 contains image data for individual hue. The image data corresponding to the individual hue is stored in the individual image memory 410. As the image, the body 401 can be used, for example, a dynamic memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The image data selection circuit 402 reads the full-color image data stored in the plurality of image memories 401 and corresponding to the individual hue according to the command from the controller 405, and transmits the full-color image data to the selector 403. The image data (monochrome image data 411) of the monochrome image is also input to the liquid crystal display device 400. Then, the monochrome image data 411 is input to the selector 403. Note that full-color images mean multiples with different hues -14-

S 201220292 彩色的層次而顯示的影像。此外，單色影像意指以具有單 一色相之彩色的層次而顯示的影像。 雖然在此實施例中係使用其中將單色影像資料411直 接輸入至選擇器403的結構，但本發明之實施例並未受限 於此結構。該單色影像資料4 1 1亦可以以與全彩色影像資 料4 1 〇相似之方式而儲存於影像記憶體40 1中，且然後， 藉由影像選擇電路402來予以讀取。在該情況中，可使選 擇器403包含於影像資料選擇電路402之中。 選擇性地，單色影像資料411可藉由合成全彩色影像 信號410於液晶顯示裝置400中而形成。 CPU 4〇4控制選擇器403及控制器4〇5，以致使該選 擇器403及該控制器405的操作切換於全彩色影像顯示與 單色影像顯示之間。 具體而言，在全彩色影像顯示的情況中，選擇器403 依據來自CPU 404的命令而選擇全彩色影像資料410，且 供應至面板406。此外，控制器4〇5依據來自CPU 404的 命令而以驅動信號及/或電源供應電位來供應面板406，該 驅動信號係與全彩色影像資料4 1 0同步，以及該電源供應 電位係在當顯示全彩色影像時被使用。 在單色影像顯示的情況中，選擇器4〇3依據來自CPU 404的命令而選擇單色影像資料，且供應至面板406。 此外，控制器405依據來自CPU 404的命令而以驅動信號 及/或電源供應電位來供應面板4 0 6 ’該驅動信號係與單色 影像資料4 1 1同步，以及該電源供應電位係在當顯示單色 -15- 201220292 影像時被使用。 面板4〇6包含：像素部412，其中各個像素包含液晶 元件；以及驅動器電路，諸如信號線驅動器電路413及掃 描線驅動器電路414。來自選擇器403之全彩色影像資料 4 1 0或單色影像資料4 1 1係供應至信號線驅動器電路4 1 3 。此外，來自控制器40〗之驅動信號/或電源供應電位係 供應至信號線驅動器電路413及/或掃描線驅動器電路414 〇 注意的是，驅動信號包含：信號線驅動器電路起動脈 波信號（SSP )及信號線驅動器電路時脈信號（SCK )， 其控制信號線驅動器電路4 1 3的操作；掃描線驅動器電路 起動脈波信號（GSP )及掃描線驅動器電路時脈信號（ GSK)，其控制掃描線驅動器電路414的操作；及其類似 信號。 個別的光之色相彼此互相不同的複數個光源係設置於 背光407中。控制器405透過背光控制電路408而控制背 光40 7之中所包含之光源的驅動。 注意的是，在全彩色影像顯示與單色影像顯示之間的 切換可藉由手動而執行》在該情況中，可將輸入裝置420 設置用於液晶顯示裝置400，以致使CPU 404依據來自輸 入裝置420之信號而控制切換。 在此實施例中之液晶顯示裝置400可包含光度測定電 路42 1。該光度測定電路42 1測量其中使用液晶顯示裝置 400之環境的亮度。CPU 404可依據藉由光度測定電路 -16-S 201220292 Image displayed in color gradation. Further, a monochrome image means an image displayed in a layer having a color of a single hue. Although a structure in which the monochrome image material 411 is directly input to the selector 403 is used in this embodiment, the embodiment of the present invention is not limited to this structure. The monochrome image data 4 1 1 can also be stored in the image memory 40 1 in a manner similar to the full color image data 4 1 , and then read by the image selection circuit 402. In this case, the selector 403 can be included in the image data selection circuit 402. Alternatively, the monochrome image data 411 can be formed by synthesizing the full color image signal 410 in the liquid crystal display device 400. The CPU 4〇4 controls the selector 403 and the controller 4〇5 so that the operations of the selector 403 and the controller 405 are switched between the full color image display and the monochrome image display. Specifically, in the case of full color image display, the selector 403 selects the full color image material 410 in accordance with a command from the CPU 404 and supplies it to the panel 406. In addition, the controller 4〇5 supplies the panel 406 with a driving signal and/or a power supply potential according to a command from the CPU 404, the driving signal is synchronized with the full-color image data 410, and the power supply potential is in the Used when displaying full color images. In the case of monochrome image display, the selector 4〇3 selects monochrome image data in accordance with a command from the CPU 404 and supplies it to the panel 406. In addition, the controller 405 supplies the panel 4 0 6 ' with the driving signal and/or the power supply potential according to the command from the CPU 404. The driving signal is synchronized with the monochrome image data 4 1 1 , and the power supply potential is in the Used when displaying monochrome -15- 201220292 images. The panel 4A includes: a pixel portion 412 in which each pixel includes a liquid crystal element; and a driver circuit such as a signal line driver circuit 413 and a scan line driver circuit 414. The full color image data 4 1 0 or the monochrome image data 4 1 1 from the selector 403 is supplied to the signal line driver circuit 4 1 3 . In addition, the driving signal/or power supply potential from the controller 40 is supplied to the signal line driver circuit 413 and/or the scan line driver circuit 414. Note that the driving signal includes: the signal line driver circuit is an arterial wave signal (SSP) And a signal line driver circuit clock signal (SCK), which controls the operation of the signal line driver circuit 4 1 3; the scan line driver circuit functions as an arterial wave signal (GSP) and a scan line driver circuit clock signal (GSK), which controls The operation of scan line driver circuit 414; and similar signals. A plurality of light sources in which the hue of the individual lights are different from each other are disposed in the backlight 407. The controller 405 controls the driving of the light source included in the backlight 40 7 through the backlight control circuit 408. It is noted that the switching between the full color image display and the monochrome image display can be performed by hand. In this case, the input device 420 can be set for the liquid crystal display device 400 to cause the CPU 404 to follow the input. The signal of device 420 controls the switching. The liquid crystal display device 400 in this embodiment may include a photometric circuit 42 1 . The photometric circuit 42 1 measures the brightness of the environment in which the liquid crystal display device 400 is used. The CPU 404 can be based on the photometric circuit -16-

S 201220292 421所偵測的亮度而控制全彩色影像顯示與單色影像顯示 之間的切換。 例如，在其中此實施例中之液晶顯示裝置400係使用 於陰暗環境之中的情況中，CPU 404可依據來自光度測定 電路421之信號而選全彩色影像顯示；在其中該液晶顯示 裝置400係使用於明亮環境之中的情況中，CPU 404可依 據來自光度測定電路421之信號而選擇單色影像顯示。注 意的是，可設定臨限値於光度測定電路421中，使得背光 407可在當使用環境之亮度變成小於該臨限値時開啓。 〈面板的結構實例〉 其次，將敘述依據本發明一實施例之液晶顯示裝置的 面板之特定結構的實例》 第2A圖描繪液晶顯示裝置之結構的實例。在第2A圖 中所描繪之液晶顯示裝置包含像素部1〇,掃描線驅動器電 路11，及信號線驅動器電路12，在本發明之一實施例中 ，像素部10係畫分成爲複數個區域。特定地，像素部10 係在第2A圖中被畫分成爲三個區域（區域1〇1至103 ) 。各個區域包含以矩陣而配置之複數個像素15。 電位係藉由掃描線驅動器電路11所控制之m個掃描 線GL，以及電位係藉由信號線驅動器電路1 2所控制之η 個掃描線SL係設置用於像素部1 0。該m個掃描線GL係 依據像素部10之區域的數目而被畫分成爲複數個組群。 例如，該m個掃描線GL係畫分成爲三個組群’因爲在第 -17- 201220292 2A圖中之像素部10被畫分成爲三個區域。在每一組群中 的該等掃描線GL係連接至每一對應區域中之複數個像素 15。具體而言，每一掃描線GL係連接至每一對應列中之 η個像素15，而該η個像素15係在以矩陣而配置於應區 域中的複數個像素15之中。 該等信號線SL的每一者係連接至m個像素15，而不 管上述區域。該等m個像素1 5係包含於以m列χη行之矩 陣而配置於像素部10中之複數個像素15中，且係設置於 每一對應的行之中。 注意的是，在此說明書中之“連接”的用語表示電性連 接，且對應於其中可供應或傳送電流、電壓、或電位之狀 態。因此，連接之狀態並未一直意指直接連接的狀態，而 是在其種類中，包含經由諸如佈線、電阻器、二極體、或 電晶體之其中可供應或傳送電流、電壓、或電位的電路元 件之間接連接的狀態。 注意的是，即使當電路圖描繪彼此互相連接之獨立組 件時，一導電膜亦可具有複數個組件的功能，例如其中佈 線的一部分亦作用成爲電極之情況。在此說明書中之“連 接”的用語亦意指其中一導電膜具有複數個組件的功能之 該情況。 電晶體的“源極電極”及“汲極電極”可根據電晶體的極 性，或所施加至個別電極之電位位準間的差異，而彼此互 換。大致地，在η通道電晶體中，供應以較低電位的電極 稱爲源極電極，以及供應以較高電位的電極稱爲汲極電極S 201220292 421 controls the brightness between the full color image display and the monochrome image display. For example, in the case where the liquid crystal display device 400 in this embodiment is used in a dark environment, the CPU 404 can select a full color image display according to a signal from the photometric circuit 421; wherein the liquid crystal display device 400 is In the case of being used in a bright environment, the CPU 404 can select a monochrome image display based on the signal from the photometric circuit 421. It is noted that the threshold can be set in the photometric circuit 421 such that the backlight 407 can be turned on when the brightness of the use environment becomes less than the threshold. <Structure Example of Panel> Next, an example of a specific structure of a panel of a liquid crystal display device according to an embodiment of the present invention will be described. Fig. 2A depicts an example of the structure of a liquid crystal display device. The liquid crystal display device depicted in Fig. 2A includes a pixel portion 1A, a scanning line driver circuit 11, and a signal line driver circuit 12. In one embodiment of the present invention, the pixel portion 10 is divided into a plurality of regions. Specifically, the pixel portion 10 is divided into three regions (regions 1〇1 to 103) in FIG. 2A. Each region contains a plurality of pixels 15 arranged in a matrix. The potential is set by the m scanning lines GL controlled by the scanning line driver circuit 11, and the potential is applied to the pixel portion 10 by the n scanning lines SL controlled by the signal line driver circuit 12. The m scanning lines GL are divided into a plurality of groups according to the number of regions of the pixel portion 10. For example, the m scanning lines GL are divided into three groups as the pixel portion 10 in the figure -17-201220292 2A is divided into three regions. The scan lines GL in each group are connected to a plurality of pixels 15 in each corresponding region. Specifically, each scan line GL is connected to n pixels 15 in each corresponding column, and the n pixels 15 are among a plurality of pixels 15 arranged in a matrix in a region. Each of the signal lines SL is connected to m pixels 15, regardless of the above regions. The m pixels 15 are included in a plurality of pixels 15 arranged in the pixel portion 10 in a matrix of m rows and 行 rows, and are provided in each corresponding row. It is to be noted that the term "connected" in this specification means an electrical connection and corresponds to a state in which a current, a voltage, or a potential can be supplied or transmitted. Therefore, the state of the connection does not always mean the state of the direct connection, but in its kind, including the supply or transmission of current, voltage, or potential via, for example, a wiring, a resistor, a diode, or a transistor. The state in which the circuit components are connected to each other. Note that even when the circuit diagram depicts separate components that are connected to each other, a conductive film may have a function of a plurality of components, for example, a case where a part of the wiring also functions as an electrode. The term "connected" in this specification also means the case where one of the conductive films has the function of a plurality of components. The "source electrode" and "dip electrode" of the transistor can be interchanged with each other depending on the polarity of the transistor or the difference in potential level applied to the individual electrodes. Generally, in an n-channel transistor, an electrode supplied with a lower potential is referred to as a source electrode, and an electrode supplied with a higher potential is referred to as a drain electrode.

S -18- 201220292 。進一步地，在p通道電晶體中，供應以較低電位的電極 稱爲汲極電極，以及供應以較高電位的電極稱爲源極電極 。在此說明書中，源極電極及汲極電極的其中一者係稱爲 第一端子，且另一者係稱爲第二端子，以敘述電晶體的連 接關係》 第2B圖描繪包含於第2A圖中之液晶顯示裝置中的像 素1 5之電路組態的實例。在第2B圖中所描繪的像素1 5 包含電晶體1 6、液晶元件1 8、及電容器1 7，而該電晶體 1 6係作用成爲開關元件，以及該液晶元件1 8的透射率係 依據透過電晶體1 6所供應之影像信號的電位而被控制。 液晶元件18包含像素電極 '相對電極、及液晶層， 該液晶層包含液晶，而在像素電極與相對電極之間的電壓 係施加至該等液晶。電容器1 7具有保持液晶元件1 8的像 素電極與相對電極間之電壓的功能。 液晶層可使用藉由熱向性液晶或液向性液晶所分類之 液晶材料而形成。做爲使用於液晶層之液晶材料的另一實 例’可給定以下者：向列型液晶，層列型液晶，膽甾型液 晶’或盤狀液晶。進一步選擇性地，可使用藉由強誘電性 液晶或反強誘電性液晶所分類之液晶材料。進一步選擇性 地，可使用藉由諸如主鏈高分子液晶、側鏈高分子液晶、 或複合型高分子液晶之高分子液晶，或低分子液晶所分類 之液晶材料。進一步選擇性地，可使用藉由聚合物分散液 晶（PDLC)所分類之液晶材料。 選擇性地’可使用顯示藍色相而配向膜係不必要的液 -19- 201220292 晶。藍色相係液晶相的其中一者，其係正好在當增加 型液晶之溫度時的同時，而在腦甾相改變成爲各向同 之前所產生的。因爲藍色相僅在狹窄的溫度範圍內產生 所以添加對掌性劑或紫外線可硬化樹脂，使得溫度範圍 善。包含顯示藍色相之液晶及對掌性劑的液晶組成物係 佳的，因爲其具有少於或等於1毫秒之小的回應時間， 有光學各向同性而無需配向處理，以及具有小的視角相 性。 此外，可使用以下方法以供驅動液晶之用，例如： (扭轉向列）模式，STN (超扭轉向列）模式，VA (垂 配向）模式，MVA (多域垂直配向）模式，IPS (平面 關）模式，OCB (光學補償雙折射）模式，ECB (電控 雙折射）模式，FLC (強誘電性液晶）模式，AFLC (反 誘電性液晶）模式，PDLC (聚合物分散液晶）模式 PNLC (聚合物網狀液晶）模式，及主客模式》 進一步視需要地，像素1 5可包含諸如電晶體、二 體、電阻器、電容器、或電感器之另一電路元件。 特定地，在第2B圖中，電晶體16的閘極電極係連 至掃描線GL。電晶體16的第一端子係連接至信號線 。電晶體1 6的第二端子係連接至液晶元件1 8的像素電 。電容器17的一電極係連接至液晶元件18的像素電極 電容器17的另一電極係連接至被供應以電位的節點。 意的是，該電位亦供應至液晶元件1 8的相對電極。所 應至相對電極的電位可與所供應至電容器17的另一電 甾 相 9 改 較 具 依 TN 直 開 制 強 極 接 SL 極 〇 注 供 極S -18- 201220292. Further, in the p-channel transistor, an electrode supplied with a lower potential is referred to as a drain electrode, and an electrode supplied with a higher potential is referred to as a source electrode. In this specification, one of the source electrode and the drain electrode is referred to as a first terminal, and the other is referred to as a second terminal to describe the connection relationship of the transistor. FIG. 2B depicts that it is included in the second An example of the circuit configuration of the pixel 15 in the liquid crystal display device in the figure. The pixel 15 depicted in FIG. 2B includes a transistor 16 , a liquid crystal element 18 , and a capacitor 17 , and the transistor 16 functions as a switching element, and the transmittance of the liquid crystal element 18 is based on It is controlled by the potential of the image signal supplied from the transistor 16. The liquid crystal element 18 includes a pixel electrode 'counter electrode and a liquid crystal layer containing liquid crystal, and a voltage between the pixel electrode and the counter electrode is applied to the liquid crystals. The capacitor 17 has a function of maintaining a voltage between the pixel electrode of the liquid crystal element 18 and the opposite electrode. The liquid crystal layer can be formed using a liquid crystal material classified by a thermotropic liquid crystal or a liquid crystal. As another example of the liquid crystal material used for the liquid crystal layer, the following may be given: nematic liquid crystal, smectic liquid crystal, cholesteric liquid crystal or discotic liquid crystal. Further, a liquid crystal material classified by a strong electric liquid crystal or an anti-strength liquid crystal can be used. Further, a liquid crystal material classified by a polymer liquid crystal such as a main chain polymer liquid crystal, a side chain polymer liquid crystal, or a composite polymer liquid crystal, or a low molecular liquid crystal can be used. Further selectively, a liquid crystal material classified by polymer dispersed liquid crystal (PDLC) can be used. Optionally, a liquid -19-201220292 crystal which exhibits a blue phase and which is not necessary for the alignment film can be used. One of the blue phase liquid crystal phases is generated at the same time as the temperature of the liquid crystal is increased, and is generated before the cerebral palsy phase changes to become the same. Since the blue phase is produced only in a narrow temperature range, a palmitic agent or an ultraviolet curable resin is added to make the temperature range good. A liquid crystal composition comprising a liquid crystal exhibiting a blue phase and a palmitic agent is preferred because it has a response time of less than or equal to 1 millisecond, is optically isotropic without alignment treatment, and has a small viewing angle phase. . In addition, the following methods can be used for driving the liquid crystal, for example: (twisted nematic) mode, STN (super twisted nematic) mode, VA (vertical alignment) mode, MVA (multi-domain vertical alignment) mode, IPS (plane) Off mode, OCB (optical compensation birefringence) mode, ECB (electrically controlled birefringence) mode, FLC (strongly induced liquid crystal) mode, AFLC (anti-induced liquid crystal) mode, PDLC (polymer dispersed liquid crystal) mode PNLC ( Polymer Reticulated Liquid Crystal) Mode, and Host and Customer Modes Further, as desired, pixel 15 may comprise another circuit component such as a transistor, a diode, a resistor, a capacitor, or an inductor. Specifically, in Fig. 2B, the gate electrode of the transistor 16 is connected to the scanning line GL. The first terminal of the transistor 16 is connected to the signal line. The second terminal of the transistor 16 is connected to the pixel of the liquid crystal element 18. One electrode of the capacitor 17 is connected to the pixel electrode of the liquid crystal element 18. The other electrode of the capacitor 17 is connected to a node supplied with a potential. It is intended that this potential is also supplied to the opposite electrode of the liquid crystal element 18. The potential to the opposite electrode can be changed to the other phase of the electrode supplied to the capacitor 17. 9 Depending on the TN, the pole is connected to the SL pole.

-20- S 201220292 之電位相同。 在本發明之一實施例中，作用成爲開關元件之電晶體 16的通道形成區可包含能隙比矽半導體的能隙更寬，且本 徵載子密度比矽半導體的本徵載子密度更低之半導體。做 爲該半導體的實例，可給定諸如碳化矽（SiC )或氮化鎵 (GaN )之化合物半導體、包含諸如氧化鋅（Zn〇 )之金 屬氧化物的氧化物半導體、及其類似物。尤其，氧化物半 導體具有高的大規模生產率之優點，因爲該氧化物半導體 可藉由濺鍍法、溼處理（例如，印刷法），或其類似方法 而形成。注意的是，諸如碳化矽或氮化鎵之化合物半導體 需成爲單晶，而需要晶體成長於比氧化物半導體極更高的 處理溫度處，或磊晶成長於特別的基板上，以便實現單晶 材料。相反地，氧化物半導體甚至可形成於室溫；因此， 可將膜之形成執行於可易於獲得的矽晶圓或並不昂貴的玻 璃基板上，且亦可施加於當基板之尺寸增加時；因而，大 規模生產率係高的。此外，可將包含氧化物半導體的半導 體元件堆疊於包含諸如矽或鍺之普通半導體材料的積體電 路上。因而，在具有寬的能隙之半導體中，氧化物半導體 尤其具有高的大規模生產率。進一步地，在其中爲了要增 進電晶體的性質（例如，場效應遷移率）而將獲得具有高 晶體性之氧化物半導體的情況中，具有晶體性之氧化物半 導體可易於藉由2 00°C至8 00°C之熱處理而獲得。 在以下說明中，將給定其中使用具有上述優點之氧化 物半導體來當作具有寬能隙之半導體的情況，做爲實例。 -21 - 201220292 除非另有指明，否則在此說明書中，於η通道電晶體 之情況中的截止狀態電流係當汲極電極的電位高於源極電 極的電位及閘極電極的電位，且同時，相對於源極電極之 閘極電極的電壓小於或等於零時之流動於源極電極與汲極 電極之間的電流。進一步地，在此說明書中，於Ρ通道電 晶體之情況中的截止狀態電流係當汲極電極的電位低於源 極電極的電位或閘極電極的電位，且同時，相對於源極之 閘極電極的電位大於或等於零時之流動於源極電極與汲極 電極之間的電流。 雖然第2Β圖描繪其中使用一電晶體16做爲像素15 中之開關元件的情況，但本發明之一實施例並未受限於此 組態。可使用複數個電晶體做爲開關元件。在其中複數個 電晶體作用成爲開關元件的情況中，該複數個電晶體可以 以並聯、串聯、或並聯連接及串聯連接之結合而彼此互相 連接。 在此說明書中，例如，其中電晶體係以串聯而彼此互 相連接之狀態意指的是，其中僅第一電晶體之第一端子及 第二端子的其中一者係連接至第二電晶體之第一端子及第 二端子的僅其中一者之狀態。進一步地，其中電晶體係以 並聯而彼此互相連接之狀態意指的是，其中第一電晶體的 第一端子係連接至第二電晶體的第一端子，且第一電晶體 的第二端子係連接至第二電晶體的第二端子之狀態。 具有該等特徵的半導體材料係包含於通道形成區之中 ，以致可實現截止狀態電流極低且耐壓高的電晶體1 6。進 -22- 201220292 一步地，具有上述結構的電晶體16係使用做 ，以致當與使用諸如矽或鍺之普通半導體材料 使用情況相較時，可有效防止液晶元件1 8中 荷的漏洩。 因爲使用截止狀態電流極低的電晶體1 6， 延長其中所供應至液晶元件1 8之電壓被保持 而，例如，在其中各自具有相同的影像資訊之 寫入至像素部10，數個連續像框週期的情況中 像的情況中一樣地，即使當驅動頻率低時，亦 顯示，換言之，可降低一定週期中之影像信號: 的寫入次數。例如，使用上述之電晶體16，其 且氧缺乏減低之氧化物半導體膜被使用作爲主 藉以增加影像信號之寫入間的時距爲1 0秒或 地爲30秒或更多，更佳地爲1分鐘或更多。 號之寫入操作間的時距成爲更長時，則可降低] 當看到藉由複數個次數之影像信號的寫入 像時，人的眼睛會感覺到開關複數次的影像， 疲勞。透過如此實施例中所述之其中可降低影 入之次數的結構，可減輕眼睛疲勞。 此外，因爲可將影像信號之電位保持更長 以即使當用以保持影像信號之電位的電容器1 至液晶元件1 8時，亦可防止顯示之影像的品 此，可藉由降低電容器17的尺寸或藉由省略霄 增加孔徑比’此將獲得液晶顯示裝置之功率消g 爲開關元件 的電晶體之 所累積之電 所以可藉以 的週期。從 影像信號係 ，與靜止影 可維持影像 討像素部1 〇 中高度純化 動層，則可 更多，較佳 當使影像信 力率消耗。 所形成之影 而引起眼腈 像信號的寫 之週期，所 7並未連接 質減低。因 ί容器17而 毛的降低。 -23- 201220292 此外，藉由其中使影像信號之電位極性相對於相對電 極的電位而反相之反相驅動，可防止所謂燒屏之液晶的劣 化。然而，在該反相驅動中，所供應至信號線之電位的改 變會在改變影像信號的極性時增加；因此，在作用成爲開 關兀件之電晶體16的源極電極與汲極電極間之電位差會 增加。因而，易於造成諸如臨限電壓偏移之電晶體16特 徵的劣化。此外，爲了要維持液晶元件1 8之中所保持的 電壓，即使當源極電極與汲極電極之間的電位差變大時， 低的截止狀態電流亦係必要的。在本發明之一實施例中， 係使用諸如氧化物半導體之能隙比矽或鍺的能隙更寬且本 徵載子密度比矽或鍺的本徵載子密度更低之半導體於電晶 體16;因此，可增加電晶體16的耐壓，且可使截止狀態 電流成爲相當地低。因而，當與使用諸如矽或鍺之普通半 導體材料的電晶體之使用情況相較時，可防止電晶體16 的劣化且可維持液晶元件1 8之中所保持的電壓。 〈面板及背光的操作實例〉 其次，將一起敘述面板之操作和背光之操作的實例。 第3圖槪略顯示液晶顯示裝置之操作及背光之操作。如第 3圖中所示地，依據本發明一實施例之液晶顯示裝置的操 作係大致地畫分成爲以下之週期：其中顯示全彩色影像之 週期（全彩色影像顯示週期301);其中顯示單色移動影 像之週期（單色移動影像顯示週期3 02 );以及其中顯示 單色靜止影像之週期（單色靜止影像顯示週期303 ) ° -24--20- S 201220292 The potential is the same. In an embodiment of the invention, the channel formation region of the transistor 16 acting as a switching element may comprise a wider energy gap than the energy gap of the germanium semiconductor, and the intrinsic carrier density is greater than the intrinsic carrier density of the germanium semiconductor. Low semiconductor. As an example of the semiconductor, a compound semiconductor such as tantalum carbide (SiC) or gallium nitride (GaN), an oxide semiconductor containing a metal oxide such as zinc oxide (Zn〇), and the like can be given. In particular, the oxide semiconductor has an advantage of high mass productivity because the oxide semiconductor can be formed by sputtering, wet processing (e.g., printing), or the like. Note that a compound semiconductor such as tantalum carbide or gallium nitride needs to be a single crystal, and it is required that the crystal grows at a higher processing temperature than the oxide semiconductor, or epitaxial growth on a special substrate in order to realize single crystal. material. Conversely, the oxide semiconductor can be formed even at room temperature; therefore, the formation of the film can be performed on a commercially available tantalum wafer or an inexpensive glass substrate, and can also be applied when the size of the substrate is increased; Therefore, mass productivity is high. Further, a semiconductor element including an oxide semiconductor may be stacked on an integrated circuit including a general semiconductor material such as germanium or germanium. Thus, in a semiconductor having a wide energy gap, an oxide semiconductor particularly has high mass productivity. Further, in the case where an oxide semiconductor having high crystallinity is to be obtained in order to enhance the properties of the transistor (for example, field-effect mobility), the oxide semiconductor having crystallinity can be easily used by 200 ° C Obtained by heat treatment at 800 °C. In the following description, a case in which an oxide semiconductor having the above advantages is used as a semiconductor having a wide energy gap will be given as an example. -21 - 201220292 Unless otherwise specified, in this specification, the off-state current in the case of an n-channel transistor is when the potential of the drain electrode is higher than the potential of the source electrode and the potential of the gate electrode, and at the same time The current flowing between the source electrode and the drain electrode with respect to the voltage of the gate electrode of the source electrode being less than or equal to zero. Further, in this specification, the off-state current in the case of the channel transistor is when the potential of the gate electrode is lower than the potential of the source electrode or the potential of the gate electrode, and at the same time, the gate with respect to the source The current flowing between the source electrode and the drain electrode when the potential of the electrode is greater than or equal to zero. Although the second drawing depicts the case where a transistor 16 is used as the switching element in the pixel 15, an embodiment of the present invention is not limited to this configuration. A plurality of transistors can be used as the switching elements. In the case where a plurality of transistors act as switching elements, the plurality of transistors may be connected to each other in parallel, series, or a combination of parallel connection and series connection. In this specification, for example, a state in which the electro-crystal systems are connected to each other in series means that only one of the first terminal and the second terminal of the first transistor is connected to the second transistor. The state of only one of the first terminal and the second terminal. Further, a state in which the electromorphic systems are connected to each other in parallel means that the first terminal of the first transistor is connected to the first terminal of the second transistor, and the second terminal of the first transistor Is connected to the state of the second terminal of the second transistor. The semiconductor material having such characteristics is included in the channel formation region, so that the transistor 16 having an extremely low off-state current and a high withstand voltage can be realized. Further, in the step -22-2012, the transistor 16 having the above structure is used so that the leakage of the liquid crystal element 18 can be effectively prevented when compared with the use of a general semiconductor material such as ruthenium or iridium. Since the transistor 16 having an extremely low off-state current is used to extend the voltage supplied thereto to the liquid crystal element 18, for example, writing to the pixel portion 10 in which each has the same image information, a plurality of consecutive image frames In the case of the cycle, as in the case of the case, even when the drive frequency is low, it is displayed, in other words, the number of writes of the image signal in a certain period can be reduced. For example, the above-described transistor 16 is used, and an oxide semiconductor film having a reduced oxygen deficiency is used as a main source to increase the time interval between writing of image signals of 10 seconds or 30 seconds or more, more preferably For 1 minute or more. When the time interval between the writing operations becomes longer, it can be lowered.] When the image of the image signal by a plurality of times is seen, the human eye feels the image of the switching multiple times and is fatigued. Eye fatigue can be alleviated by the structure described in the embodiment in which the number of times of insertion can be reduced. In addition, since the potential of the image signal can be kept longer to prevent the appearance of the displayed image even when the capacitor 1 for holding the potential of the image signal is applied to the liquid crystal element 18, the size of the capacitor 17 can be reduced. Or by increasing the aperture ratio by omitting ', this will result in a period in which the power of the liquid crystal display device is reduced to the electric power accumulated by the transistor of the switching element. From the image signal system and the still image, it is possible to maintain the high-purity moving layer in the pixel portion 1 ,, which is more preferable, and it is better to consume the image credit rate. The resulting shadow causes a period of writing of the eye nitrile image signal, and 7 does not have a reduced quality. The hair is lowered due to the container 17 of ί. -23- 201220292 In addition, by inverting the polarity of the potential of the image signal with respect to the potential of the opposite electrode, deterioration of the so-called burn-in liquid crystal can be prevented. However, in the inverting driving, the change in the potential supplied to the signal line is increased when the polarity of the image signal is changed; therefore, between the source electrode and the drain electrode of the transistor 16 functioning as the switching element The potential difference will increase. Thus, it is easy to cause deterioration of the characteristics of the transistor 16 such as a threshold voltage shift. Further, in order to maintain the voltage held in the liquid crystal element 18, even when the potential difference between the source electrode and the drain electrode becomes large, a low off-state current is necessary. In one embodiment of the present invention, a semiconductor such as an oxide semiconductor having a wider energy gap than 矽 or 锗 and a lower intrinsic carrier density than 本 or 锗 is used. 16; therefore, the withstand voltage of the transistor 16 can be increased, and the off-state current can be made relatively low. Thus, when compared with the use of a transistor using a common semiconductor material such as tantalum or niobium, deterioration of the transistor 16 can be prevented and the voltage held in the liquid crystal element 18 can be maintained. <Operation Example of Panel and Backlight> Next, an example of the operation of the panel and the operation of the backlight will be described together. Figure 3 shows the operation of the liquid crystal display device and the operation of the backlight. As shown in FIG. 3, the operation of the liquid crystal display device according to an embodiment of the present invention is roughly divided into a cycle in which a full color image is displayed (full color image display period 301); The period of the color moving image (monochrome moving image display period 3 02 ); and the period in which the monochrome still image is displayed (monochrome still image display period 303 ) ° -24-

S 201220292 在全彩色影像顯示週期301中，一像框週期係由複數 個子像框週期所構成。在每一子像框週期中，係執行對象 素部之影像信號的寫入。當正在顯示影像時’驅動信號係 連續供應至諸如掃描線驅動器電路及信號線驅動器電路之 驅動器電路。因此，該等驅動器電路係操作於全彩色影像 顯示週期3 0 1中。此外，由背光所供應至像素部之光的色 相係每個子像框週期地切換。對應於個別色相之影像信號 係順序地寫入至像素部。然後，對應於所有該等色相之該 等影像信號係以一像框週期而寫入。從而，在全彩色影像 顯示週期301中，對像素部之影像信號的寫入次數係超過 一，且係藉由來自背光所供應之光的色相數目而予以決定 〇 在單色移動影像顯示週期302中，對像素部之影像信 號的寫入係每個像框週期地執行。當正在顯示影像時，驅 動信號係連續地供應至諸如掃描線驅動器電路及信號線驅 .動器電路之驅動器電路。因此’該等驅動器電路係操作於 單色移動影像顯示週期3 02中。此外，在該單色移動影像 顯示週期302中，由背光所供應至像素部之光的色相並未 每一像框週期地切換，而是將具有相同色相的光連續供應 至像素部。然後’一影像可在一像框週期中透過對應於該 一色相之影像信號對像素部的寫入而予以形成。從而，在 單色移動影像顯示週期3 〇2中’於一像框週期中之對像素 部之影像信號的寫入次數係一。 在單色靜止影像顯示週期303中，對像素部之影像信 -25- 201220292 號的寫入係每個像框週期地執行。注意的是’與全彩色影 像顯示週期301及單色移動影像顯示週期302不同地’驅 動信號係在對像素部之影像信號的寫入期間被供應至驅動 器電路，且在寫入完成之後，停止對驅動器電路供應驅動 信號。因此，除了在影像信號的寫入期間之外’驅動器電 路並未在單色靜止影像顯示週期303中操作。進一步地’ 在該單色靜止影像顯示週期303中’由背光所供應至像素 部之光的色相並未每一像框週期地切換，而是將具有相同 色相的光連續供應至像素部。然後，一影像可在一像框週 期中透過對應於該一色相之影像信號對像素部的寫入而予 以完成。從而，在單色靜止影像顯示週期303中，於一像 框週期中之對像素部之影像信號的寫入次數係一。 爲了要防止影像的閃爍或其類似者受到感覺，較佳的 是，在單色移動影像顯示週期302中，於一秒之中應提供 60琪更多的像框週期。在單色靜止影像顯示週期3 03中， 可將一像框週期極度延長爲例如，一分鐘或更長。當一像 框週期變長時，則其中不操作驅動器電路的週期會變長， 以致可降低液晶顯示裝置的功率消耗。 依據本發明一實施例之液晶顯示裝置並不包含濾色片 。因此，在全彩色影像.顯示週期301、單色移動影像顯示 週期3 02、及單色靜止影像顯示週期3 03的各自及每個週 期中，可使背光之功率消耗降低至使用濾色片的液晶顯示 裝置之功率消耗的三分之一。 色相彼此互相不同的複數個光係在全彩色影像顯示週S 201220292 In the full-color image display period 301, an image frame period is composed of a plurality of sub-frame periods. In each sub-frame cycle, the writing of the image signal of the pixel portion is performed. The drive signal is continuously supplied to a driver circuit such as a scan line driver circuit and a signal line driver circuit while the image is being displayed. Therefore, the driver circuits operate in the full color image display period 301. Further, the hue of the light supplied from the backlight to the pixel portion is periodically switched for each sub-frame. The image signals corresponding to the individual hue are sequentially written to the pixel portion. Then, the image signals corresponding to all of the hue are written in a frame period. Therefore, in the full-color image display period 301, the number of writes to the image signal of the pixel portion is more than one, and is determined by the number of hue of light supplied from the backlight, and is displayed in the monochrome moving image display period 302. The writing of the image signal to the pixel portion is performed periodically for each image frame. When an image is being displayed, the drive signal is continuously supplied to a driver circuit such as a scan line driver circuit and a signal line driver circuit. Thus, the driver circuits operate in a monochrome moving image display period 302. Further, in the monochrome moving image display period 302, the hue of the light supplied from the backlight to the pixel portion is not periodically switched every frame, but light having the same hue is continuously supplied to the pixel portion. Then, an image can be formed by writing to the pixel portion through the image signal corresponding to the one color phase in a frame period. Therefore, the number of writes to the image signal of the pixel portion in one frame period in the monochrome moving image display period 3 〇 2 is one. In the monochrome still image display period 303, the writing of the image information of the pixel portion -25 - 201220292 is periodically performed for each image frame. Note that 'the drive signal is supplied to the driver circuit during the writing of the image signal to the pixel portion, unlike the full-color image display period 301 and the monochrome moving image display period 302, and is stopped after the writing is completed. A drive signal is supplied to the driver circuit. Therefore, the driver circuit is not operated in the monochrome still image display period 303 except during the writing period of the image signal. Further, in the monochrome still image display period 303, the hue of the light supplied from the backlight to the pixel portion is not periodically switched every frame, but light having the same hue is continuously supplied to the pixel portion. Then, an image can be completed by writing the pixel portion through the image signal corresponding to the one color phase in one frame period. Therefore, in the monochrome still image display period 303, the number of times of writing the image signal to the pixel portion in one frame period is one. In order to prevent the flicker of the image or the like from being perceived, it is preferred that in the monochrome moving image display period 302, more of the frame period should be provided in one second. In the monochrome still image display period 303, an image frame period can be extremely extended to, for example, one minute or longer. When the period of one frame becomes long, the period in which the driver circuit is not operated becomes long, so that the power consumption of the liquid crystal display device can be reduced. A liquid crystal display device according to an embodiment of the present invention does not include a color filter. Therefore, in each and every period of the full-color image display period 301, the monochrome moving image display period 312, and the monochrome still image display period 303, the power consumption of the backlight can be reduced to the use of the color filter. One-third of the power consumption of a liquid crystal display device. a plurality of light systems in which the hue is different from each other in the full color image display week

26- S 201220292 期301中的一像框週期中，被順序地供應至像素部的每一 區域。第4A至4C圖槪略地描繪所供應至該等區域之光的 色相之實例。第4A至4C圖描繪其中如第2A圖中似地將 像素部畫分成爲三個區域的情況。進一步地’第4A至4C 圖描繪其中背光供應紅色（R)、藍色（B)及綠色（G) 之個別的光至像素部之情況。 首先，第4A圖顯示第一子像框週期’其中紅色（R) 的光係供應至區域101、綠色（G)的光係供應至區域102 、以及藍色（B )的光係供應至區域103。第4B圖顯示第 二子像框週期，其中綠色（G)的光係供應至區域101、 藍色（B)的光係供應至區域102'以及紅色（R)的光係 供應至區域103。第4C圖顯示第三子像框週期，其中藍 色（B)的光係供應至區域1 〇 1、紅色（R )的光係供應至 區域102，以及綠色（G )的光係供應至區域103。 上述該等子像框週期的完成對應於一像框週期的完成 。在一像框週期中，所供應至該等區域之每一色相的光環 繞該等區域一圈，而全彩色影像可藉以顯示。在該等區域 中，所供應至區域1 〇 1之光的色相係以紅色（R )、綠色 (G)、及藍色（B)的順序而改變；所供應至區域1〇2之 光的色相係以綠色（G)、藍色（B)、及紅色（R),的順 序而改變；以及所供應至區域1 〇 3之光的色相係以藍色（ B )、紅色（R)、及綠色（G )的順序而改變。在此方式 中，具有不同色相之複數個光係依據不同於該等區域之間 的順序，而依序地供應至該等區域的每一者。 -27- 201220292 第4A至4C圖描繪其中具有一色相的光係供應至各個 子像框中之一區域的實例；然而，本發明之一實施例並未 受限於此結構。例如，所供應至該等區域之該等光的色相 可以以影像信號的寫入之完成的順序而改變。在該情況中 ，供應有色相之光的區域無需一定要對應於藉由畫分像素 部所形成的區域。 在單色移動影像顯示週期3 02及單色靜止影像顯示週 期303中，色相彼此互相不同之複數個光的其中至少一者 係以整個像素部或以每個區域而連續地供應。第5A及5B 圖槪略地描繪所供應至每一區域之色相的實例。第5A及 5B圖描繪其中像素部係如第2A圖中所示地畫分成爲三個 區域的情況。 、 第5A圖描繪其中紅色（R)、藍色（B) '及綠色（ G )之個別光係自背光而並聯地供應至像素部之狀態°紅 色（R)、藍色（B)、及綠色（G)係混合供應白色（W )的光至該等區域1〇1、1〇2及103的每一者。因而’具 有白色光之層次的影像係顯示於像素部中。 雖然第5A圖描繪其中具有一色相的光係藉由混合具 有不同色相之複數個光而供應至像素部的實例’但具有一 色相的光可無需混合地被供應至像素部。第5B圖描繪其 中綠色（G )的光係自背光而供應至像素部之狀態。因而 ，在該情況中，具有綠色光之層次的影像係顯示於像素部 中〇In a picture frame period in the period 26-S 201220292, 301 is sequentially supplied to each area of the pixel portion. Figures 4A through 4C schematically depict examples of the hue of light supplied to the regions. 4A to 4C are diagrams in which the pixel portion is divided into three regions as in Fig. 2A. Further, the 4A to 4C drawings depict the case where the backlight supplies individual light of red (R), blue (B), and green (G) to the pixel portion. First, FIG. 4A shows a first sub-frame period 'where a light system of red (R) is supplied to the area 101, a light system of green (G) is supplied to the area 102, and a light system of blue (B) is supplied to the area 103. . Fig. 4B shows a second sub-frame period in which a green (G) light system is supplied to the area 101, a blue (B) light system is supplied to the area 102', and a red (R) light system is supplied to the area 103. 4C shows a third sub-frame period in which a light system of blue (B) is supplied to the regions 1 〇1, a red (R) light system is supplied to the region 102, and a green (G) light system is supplied to the region 103. . The completion of the above-described sub-frame periods corresponds to the completion of a picture frame period. In a frame cycle, the halo of each hue supplied to the regions is circled around the regions, and the full color image can be displayed. In these regions, the hue of the light supplied to the region 1 〇 1 is changed in the order of red (R ), green (G), and blue (B); the light supplied to the region 1 〇 2 The hue system changes in the order of green (G), blue (B), and red (R); and the hue of light supplied to the region 1 〇3 is blue (B), red (R), And the order of green (G) changes. In this manner, a plurality of light systems having different hues are sequentially supplied to each of the regions in accordance with an order different from the regions. -27-201220292 Figures 4A to 4C depict an example in which a light system having one hue is supplied to one region of each sub-frame; however, an embodiment of the present invention is not limited to this structure. For example, the hue of the light supplied to the regions can be changed in the order in which the writing of the image signals is completed. In this case, the area where the light of the hue is supplied does not necessarily have to correspond to the area formed by the sub-pixel portion. In the monochrome moving image display period 032 and the monochrome still image display period 303, at least one of a plurality of lights different in hue from each other is continuously supplied in the entire pixel portion or in each region. Figures 5A and 5B schematically depict examples of the hue supplied to each region. Figs. 5A and 5B depict a case in which the pixel portion is divided into three regions as shown in Fig. 2A. 5A depicts a state in which individual light systems of red (R), blue (B) ', and green (G) are supplied in parallel to the pixel portion from the backlight. Red (R), blue (B), and The green (G) is mixed to supply white (W) light to each of the areas 1〇1, 1〇2, and 103. Thus, an image having a level of white light is displayed in the pixel portion. Although Fig. 5A depicts an example in which a light system having one hue is supplied to a pixel portion by mixing a plurality of lights having different hue, light having one hue can be supplied to the pixel portion without mixing. Fig. 5B depicts a state in which the light of green (G) is supplied from the backlight to the pixel portion. Therefore, in this case, an image having a layer of green light is displayed in the pixel portion.

-28- S 201220292 〈掃描線驅動器電路11之組態實例〉 第6圖描繪第2A圖中所描繪之掃描線驅動器電路11 的組態實例。第6圖中之掃描線驅動器電路11包含第一 至第m脈波輸出電路20_1至20_m。選擇信號係自第一至 第m脈波輸出電路2 0_1至20_m而輸出，且供應至第m 掃描線（掃描線GL1至GLm)。 第一至第四掃描線驅動器電路時脈信號（GCK1至 GCK4 )，第一至第六脈波寬度控制信號（PWC1至PWC6 )，及掃描線驅動器電路起動脈波信號（GSP )係供應至 掃描線驅動器電路11 ’做爲驅動信號。 注意的是，第6圖描繪其中第一至第k脈波輸出電路 2 0_1至20_k ( k係4的倍數且小於m/2)係分別連接至區 域101中之掃描線GL1至GLk。進一步地，第（k + Ι )至 第2k脈波輸出電路20_k+l至20_2k係分別連接至區域 102中之掃描線GLk+Ι至GL2k。進一步地，第（2k+l ) 至第m脈波輸出電路2 0_2k+l至20_m係分別連接至區域 103中之掃描線GL2k+l至GLm。 第一至第m脈波輸出電路20_1至20_m開始操作以 回應於輸入至第一脈波輸出電路20_1的掃描線驅動器電 路起動脈波信號（GSP) ’且輸出選擇信號’該等選擇信 號的脈波係順序地移位。 可將具有相同組態之電路施加至第一至第m脈波輸出 電路20_1至20_m。第一至第m脈波輸出電路20_1至 20 m的特定連接關係將參照第7圖而予以敘述。 -29 - 201220292 第7圖槪略地描繪第χ脈波輸出電路20_χ(χ係小於 或等於m之自然數）。第一至第m脈波輸出電路20_1至 2 〇_m各自具有端子21至27。端子21至24及端子26係 輸入端子，以及端子25及27係輸出端子。 首先，將敘述端子21。第一脈波輸出電路20_1之端 子2 1係連接至用以供應掃描線驅動器電路起動脈波信號 (GSP)的佈線。第二至第m脈波輸出電路20_2至2 0一m 之每一者的端子21係連接至各自對應之前一級的脈波輸 出電路之端子27。 其次，將敘述端子22。第（4a-3 )脈波輸出電路20_ (4a-3 ) ( a係小於或等於m/4之自然數）之端子22係連 接至用以供應第一掃描線驅動器電路時脈信號（GCK1 ) 的佈線。第（4a-2)脈波輸出電路20_(4a-2)之端子22 係連接至用以供應第二掃描線驅動器電路時脈信號（ GCK2)的佈線。第（4a-l)脈波輸出電路20_(4a-l)之 端子2 2係連接至用以供應第三掃描線驅動器電路時脈信 號（GCK3)的佈線。第4a脈波輸出電路20_4a之端子22 係連接至用以供應第四掃描線驅動器電路時脈信號（ GCK4 )的佈線。 接著，將敘述端子23。第（4a_3)脈波輸出電路2〇_ (4a-3)之端子23係連接至用以供應第二掃描線驅動器 電路時脈信號（GCK2 )的佈線。第（4a_2 )脈波輸出電路 20_(4a-2)之端子23係連接至用以供應第三掃描線驅動 器電路時脈信號（GCK3 )的佈線。第（4a-i )脈波輸出電 -30--28-S 201220292 <Configuration Example of Scan Line Driver Circuit 11> Fig. 6 depicts a configuration example of the scan line driver circuit 11 depicted in Fig. 2A. The scanning line driver circuit 11 in Fig. 6 includes first to m-th pulse wave output circuits 20_1 to 20_m. The selection signal is output from the first to mth pulse wave output circuits 2 0_1 to 20_m and supplied to the mth scan line (scan lines GL1 to GLm). First to fourth scan line driver circuit clock signals (GCK1 to GCK4), first to sixth pulse width control signals (PWC1 to PWC6), and scan line driver circuit from arterial wave signals (GSP) are supplied to the scan The line driver circuit 11' acts as a drive signal. Note that Fig. 6 depicts that the first to kth pulse wave output circuits 2 0_1 to 20_k (multiple of k series 4 and smaller than m/2) are respectively connected to the scanning lines GL1 to GLk in the area 101. Further, the (k + Ι ) to 2kth pulse wave output circuits 20_k+1 to 20_2k are respectively connected to the scanning lines GLk+Ι to GL2k in the area 102. Further, the (2k+1)th to mth pulse wave output circuits 2 0_2k+1 to 20_m are respectively connected to the scanning lines GL2k+1 to GLm in the region 103. The first to mth pulse wave output circuits 20_1 to 20_m start to operate in response to the scan line driver circuit input to the first pulse wave output circuit 20_1 from the arterial wave signal (GSP)' and output the selection signal 'the pulse of the selection signals' The wave system is shifted sequentially. Circuits having the same configuration can be applied to the first to mth pulse wave output circuits 20_1 to 20_m. The specific connection relationship of the first to mth pulse wave output circuits 20_1 to 20m will be described with reference to Fig. 7. -29 - 201220292 Figure 7 sketches the second pulse output circuit 20_χ (the natural number is less than or equal to m). The first to mth pulse wave output circuits 20_1 to 2 〇_m each have terminals 21 to 27. Terminals 21 to 24 and terminal 26 are input terminals, and terminals 25 and 27 are output terminals. First, the terminal 21 will be described. The terminal 21 of the first pulse wave output circuit 20_1 is connected to a wiring for supplying the scan line driver circuit an arterial wave signal (GSP). The terminals 21 of each of the second to m-th pulse wave output circuits 20_2 to 20-m are connected to the terminals 27 of the pulse wave output circuits of the respective previous stages. Next, the terminal 22 will be described. The terminal 22 of the (4a-3)th pulse wave output circuit 20_(4a-3) (a is a natural number less than or equal to m/4) is connected to a clock signal (GCK1) for supplying the first scan line driver circuit. Wiring. The terminal 22 of the (4a-2)th pulse wave outputting circuit 20_(4a-2) is connected to a wiring for supplying the second scanning line driver circuit clock signal (GCK2). The terminal 2 2 of the (4a-1)th pulse wave outputting circuit 20_(4a-1) is connected to the wiring for supplying the third scanning line driver circuit clock signal (GCK3). The terminal 22 of the 4a pulse wave output circuit 20_4a is connected to the wiring for supplying the fourth scan line driver circuit clock signal (GCK4). Next, the terminal 23 will be described. The terminal 23 of the (4a-3)th pulse wave output circuit 2〇_(4a-3) is connected to the wiring for supplying the second scan line driver circuit clock signal (GCK2). The terminal 23 of the (4a_2)th pulse wave outputting circuit 20_(4a-2) is connected to the wiring for supplying the third scanning line driver circuit clock signal (GCK3). (4a-i) pulse wave output power -30-

S 201220292 路2 0_ ( 4a-l )之端子23係連接至用以供應第四掃描線驅 動器電路時脈信號（GCK4 )的佈線。第4a脈波輸出電路 2〇_4a之端子23係連接至用以供應第一掃描線驅動器電路 時脈信號（G C K 1 )的佈線。 接著，將敘述端子24。在第（2b-l )脈波輸出電路 20_ ( 2b-l ) ( b係小於或等於k/2之自然數）中之端子24 係連接至用以供應第一脈波寬度控制信號（PWC 1 )的佈 線。在第2b脈波輸出電路20_2b中之端子24係連接至用 以供應第四脈波寬度控制信號（PWC4 )的佈線。在第（ 2c-l )脈波輸出電路20_ ( 2c-l ) ( c係大於或等於（ k/2 + l )且小於或等於k之自然數）中之端子24係連接至 用以供應第二脈波寬度控制信號（PWC2 )的佈線。在第 2c脈波輸出電路20_2c中之端子24係連接至用以供應第 五脈波寬度控制信號（PWC5 )的佈線。在第（2d-l )脈 波輸出電路20_ ( 2d-l ) ( d係大於或等於（k+Ι )且小於 或等於m/2之自然數）中之端子24係連接至用以供應第 三脈波寬度控制信號（PWC3 )的佈線。在第2d脈波輸出 電路20_2d中之端子24係連接至用以供應第六脈波寬度 控制信號（P W C 6 )的佈線。 接著，將敘述端子25。第X脈波輸出電路20_x之端 子25係連接至第X列中之掃描線GLx。 接著，將敘述端子26。第y脈波輸出電路20_y ( y係 小於或等於（m-1 )之自然數）之端子26係連接至第（ PI)脈波輸出電路20_ ( y+Ι)的端子27。第m脈波輸出 -31 - 201220292 電路20_m之端子26係連接至用以供應用於第m脈波輸 出電路之停止信號（STP )的佈線。在其中設置第（m+l )脈波輸出電路的情況中，用於第m脈波輸出電路之停止 信號（STP)對應於自第（m+l)脈波輸出電路20_(m+l )之端子27所輸出的信號。特定地，該等信號可自設置 做爲虛擬電路之第（m+l)脈波輸出電路20_(m+l)，或 藉由自外部直接輸入，而供應至第m脈波輸出電路20_m 〇 在各自的脈波輸出電路中之端子27的連接關係係如 上文所敘述。因此，可參考上述之說明。 〈脈波輸出電路之組態實例1〉 其次，第8A圖將描繪第7圖中所描繪之第X脈波輸 出電路20_x之特定組態的實例。第8A圖中所描繪之脈波 輸出電路包含電晶體31至39。 電晶體3 1的閘極電極係連接至端子2 1。電晶體3 1之 第一端子係連接至供應有高的電源供應電位（Vdd )之節 點。電晶體31之第二端子係連接至電晶體3 3的閘極電極 及電晶體3 8的閘極電極。 電晶體3 2之閘極電極係連接至電晶體3 4的閘極電極 及電晶體39的閘極電極。電晶體32之第一端子係連接至 供應有低的電源供應電位（Vss )之節點。電晶體32之第 二端子係連接至電晶體3 3的閘極電極及電晶體3 8的閘極 電極。 -32-The terminal 23 of the S 201220292 way 2 0_ ( 4a - l ) is connected to the wiring for supplying the fourth scan line driver circuit clock signal (GCK4 ). The terminal 23 of the 4a-pulse output circuit 2〇_4a is connected to the wiring for supplying the first scan line driver circuit clock signal (G C K 1 ). Next, the terminal 24 will be described. The terminal 24 is connected to the first pulse width control signal (PWC 1) in the (2b-1)th pulse wave output circuit 20_(2b-1) (b is a natural number less than or equal to k/2) ) wiring. The terminal 24 in the 2b pulse wave output circuit 20_2b is connected to a wiring for supplying the fourth pulse width control signal (PWC4). In the (2c-1)th pulse wave output circuit 20_(2c-l) (c is greater than or equal to (k/2 + l) and less than or equal to the natural number of k), the terminal 24 is connected to the supply Wiring of the two-pulse width control signal (PWC2). The terminal 24 in the 2c pulse wave output circuit 20_2c is connected to the wiring for supplying the fifth pulse width control signal (PWC5). The terminal 24 is connected to the supply terminal in the (2d-1)th pulse wave output circuit 20_(2d-1) (d is a natural number greater than or equal to (k+Ι) and less than or equal to m/2) Wiring of the three-pulse width control signal (PWC3). The terminal 24 in the 2d pulse wave output circuit 20_2d is connected to the wiring for supplying the sixth pulse width control signal (P W C 6 ). Next, the terminal 25 will be described. The terminal 25 of the X-th pulse output circuit 20_x is connected to the scanning line GLx in the Xth column. Next, the terminal 26 will be described. The terminal 26 of the y-th pulse output circuit 20_y (y is a natural number less than or equal to (m-1)) is connected to the terminal 27 of the (PI) pulse wave output circuit 20_(y+Ι). The mth pulse wave output -31 - 201220292 The terminal 26 of the circuit 20_m is connected to the wiring for supplying the stop signal (STP) for the mth pulse wave output circuit. In the case where the (m+1)th pulse wave output circuit is provided, the stop signal (STP) for the mth pulse wave output circuit corresponds to the (m+1)th pulse wave output circuit 20_(m+l) The signal output by terminal 27. Specifically, the signals may be self-configured as the (m+1)th pulse wave output circuit 20_(m+1) of the virtual circuit, or may be supplied to the mth pulse wave output circuit 20_m by direct input from the outside. The connection relationship of the terminals 27 in the respective pulse wave output circuits is as described above. Therefore, reference can be made to the above description. <Configuration Example 1 of Pulse Wave Output Circuit> Next, Fig. 8A will depict an example of a specific configuration of the X-th pulse output circuit 20_x depicted in Fig. 7. The pulse wave output circuit depicted in Fig. 8A includes transistors 31 to 39. The gate electrode of the transistor 31 is connected to the terminal 21. The first terminal of the transistor 3 1 is connected to a node supplied with a high power supply potential (Vdd). The second terminal of the transistor 31 is connected to the gate electrode of the transistor 33 and the gate electrode of the transistor 38. The gate electrode of the transistor 32 is connected to the gate electrode of the transistor 34 and the gate electrode of the transistor 39. The first terminal of the transistor 32 is connected to a node supplied with a low power supply potential (Vss). The second terminal of the transistor 32 is connected to the gate electrode of the transistor 33 and the gate electrode of the transistor 38. -32-

S 201220292 電晶體3 3之第一端子係連接至端子22。電晶體3 3之 第二端子係連接至端子27。 電晶體3 4之第一端子係連接至供應有低的電源供應 電位（Vss)之節點。電晶體34之第二端子係連接至端子 27 〇 電晶體3 5的閘極電極係連接至端子2 1。電晶體3 5之 第一端子係連接至供應有低的電源供應電位（Vss )之節 點。電晶體35之第二端子係連接至電晶體34的閘極電極 及電晶體3 9的閘極電極。 電晶體36的閘極電極係連接至端子26。電晶體36之 第一端子係連接至供應有高的電源供應電位（Vdd )之節 點。電晶體36之第二端子係連接至電晶體34的閘極電極 及電晶體39的閘極電極。注意的是，可使用其中電晶體 36之第一端子係連接至供應有電源供應電位（Vcc)之節 點，而該電源供應電位（Vcc )係高於該低的電源供應電 位（Vss)且低於高的電源供應電位（Vdd)之結構。 電晶體3 7的閘極電極係連接至端子23。電晶體3 7之 第一端子係連接至供應有高的電源供應電位（Vdd )之節 點。電晶體3 7之第二端子係連接至電晶體3 4的閘極電極 及電晶體3 9的閘極電極。該電晶體3 7之第一端子係連接 至供應有電源供應電位（Vcc )之節點。 電晶體3 8之第一端子係連接至端子24。電晶體3 8之 第二端子係連接至端子25。 電晶體3 9之第一端子係連接至供應有低的電源供應 -33- 201220292 電位（Vss)之節點。電晶體39之第二端子係連接至 25 〇 其次，第8B圖顯示第8A圖中所描繪的脈波輸出電 之時序圖的實例。在第8B圖中所示之週期tl至t7具 相同長度的時間。週期tl至t7之各自的長度對應於第 至第四掃描線.驅動器電路時脈信號（GCK1至GCK4) 每一者之脈波寬度的三分之一，且對應於第一至第六脈 寬度控制信號（PWC1至PWC6)的每一者之脈波寬度 二分之一。 在第8A圖中所描繪的脈波輸出電路中，於週期tl t2中，所輸入至端子21的電位係在高位準，且所輸入 端子22、端子23、端子24、及端子26的電位係在低位 。因而，低位準的電位係自端子25及端子27而輸出。 接著，在週期t3中，所輸入至端子21及端子24 電位係在高位準，且所輸入至端子22、端子23、及端 26的電位係在低位準。因而，高位準的電位係自端子 而輸出，且低位準的電位係自端子27而輸出。 接著，在週期t4中，所輸入至端子22及端子24 電位係在高位準，且所輸入至端子21、端子23、及端 2 6的電位係在低位準。因而，局位準的電位係自端子 及端子27而輸出。 在週期t5及t6，所輸入至端子22的電位係在高位 ，且所輸入至端子21、端子23、端子24、及端子26的 位係在低.位準。因而，低位準的電位係自端子2 5而輸 子 路 有 的 波 的 及 至 準 的 子 25 的 子 25 準 電 出S 201220292 The first terminal of the transistor 3 3 is connected to the terminal 22. The second terminal of the transistor 3 3 is connected to the terminal 27. The first terminal of the transistor 34 is connected to a node supplied with a low power supply potential (Vss). The second terminal of the transistor 34 is connected to the terminal 27 〇 The gate electrode of the transistor 35 is connected to the terminal 21. The first terminal of the transistor 35 is connected to a node supplied with a low power supply potential (Vss). The second terminal of the transistor 35 is connected to the gate electrode of the transistor 34 and the gate electrode of the transistor 39. The gate electrode of transistor 36 is connected to terminal 26. The first terminal of the transistor 36 is connected to a node to which a high power supply potential (Vdd) is supplied. The second terminal of the transistor 36 is connected to the gate electrode of the transistor 34 and the gate electrode of the transistor 39. Note that a first terminal in which the transistor 36 is connected may be connected to a node to which a power supply potential (Vcc) is supplied, and the power supply potential (Vcc) is higher than the low power supply potential (Vss) and low. The structure of the high power supply potential (Vdd). The gate electrode of the transistor 37 is connected to the terminal 23. The first terminal of the transistor 37 is connected to a node supplied with a high power supply potential (Vdd). The second terminal of the transistor 37 is connected to the gate electrode of the transistor 34 and the gate electrode of the transistor 39. The first terminal of the transistor 37 is connected to a node to which a power supply potential (Vcc) is supplied. The first terminal of the transistor 38 is connected to the terminal 24. The second terminal of the transistor 38 is connected to the terminal 25. The first terminal of the transistor 39 is connected to a node that supplies a low power supply -33 - 201220292 potential (Vss). The second terminal of the transistor 39 is connected to 25 〇. Next, Fig. 8B shows an example of a timing chart of the pulse wave output power depicted in Fig. 8A. The periods t1 to t7 shown in Fig. 8B have the same length of time. The respective lengths of the periods t1 to t7 correspond to the third to the fourth scan line. One third of the pulse width of each of the driver circuit clock signals (GCK1 to GCK4), and corresponds to the first to sixth pulse widths. The pulse width of each of the degree control signals (PWC1 to PWC6) is one-half. In the pulse wave output circuit depicted in FIG. 8A, in the period t1 to t2, the potential input to the terminal 21 is at a high level, and the potentials of the input terminal 22, the terminal 23, the terminal 24, and the terminal 26 are In the low post. Therefore, the low level potential is output from the terminal 25 and the terminal 27. Next, in the period t3, the potentials input to the terminals 21 and 24 are at a high level, and the potentials input to the terminals 22, 23, and 26 are at a low level. Therefore, the potential of the high level is output from the terminal, and the potential of the low level is output from the terminal 27. Next, in the period t4, the potentials input to the terminal 22 and the terminal 24 are at a high level, and the potentials input to the terminal 21, the terminal 23, and the terminal 26 are at a low level. Therefore, the potential of the local level is output from the terminal and the terminal 27. In the periods t5 and t6, the potential input to the terminal 22 is at a high level, and the positions input to the terminal 21, the terminal 23, the terminal 24, and the terminal 26 are at a low level. Therefore, the low level potential is derived from the terminal 25 and the wave of the input and the sub-25 of the sub-25

S -34- 201220292 ’且高位準的電位係自端子27而輸出。 在週期t7中，所輸入至端子23及端子26的電位係 在高位準，且所輸入至端子21、端子22、及端子24的電 位係在低位準。因而，低位準的電位係自端子2 5及端子 27而輸出。 其次’第8C圖顯示第8A圖中所描繪的脈波輸出電路 之時序圖的另一實例。在第8C圖中所示之週期tl至t7 具有相同長度的時間。週期tl至t7之各自的長度對應於 第一至第四掃描線驅動器電路時脈信號（GCK1至GCK4 )的每一者之脈波寬度的三分之一，且對應於第一至第六 脈波寬度控制信號（PWC1至PWC6)的每一者之脈波寬 度的三分之一。 在第8A圖中所描繪的脈波輸出電路中，於週期tl至 t3中’所輸入至端子21的電位係在高位準，且所輸入至 端子22、端子23、端子24、及端子26的電位係在低位準 。因而，在週期tl至t3中，低位準的電位係自端子25及 端子27而輸出。 然後，在其中所輸入至端子22及端子24的電位係在 高位準，且所輸入至端子21、端子23、及端子26的電位 係在低位準的週期t4至t6中，高位準的電位係自端子2 5 及端子27而輸出。 〈全彩色影像顯示週期301中之掃描線驅動器電路的操作 實例〉 -35- 201220292 其次’例如，將使用參照第6圖、第7圖、及第8A 圖所描述之掃描線驅動器電路11來說明第3圖中所示的 全彩色影像顯示週期301中之掃描線驅動器電路11的操 作。 第9圖顯示在全彩色影像顯示週期301中之掃描線驅 動器電路11的時序圖之實例。子像框週期SF1，子像框 週期SF2，及子像框週期SF3係設置於第9圖中之一像框 週期中。在第9圖中，係使用子像框週期SF1的時序圖做 爲典型之實例。注意的是，在第9圖中，m係3j。 在第9圖中，掃描線GL1至掃描線GLk係連接至區 域101中之像素，掃描線GLk+Ι至掃描線GL2k係連接至 區域102中之像素，掃描線GL2k+l至掃描線GL3k係連 接至區域103中之像素。 第一掃描線驅動器電路時脈信號（GCK1 )週期性地 重複高位準電位（高電源供應電位（Vdd ))及低位準電 位（低電源供應電位（Vss ))，且具有1/4的責務比。 進一步地，第二掃描線驅動器電路時脈信號（GCK2 )係 相位以第一掃描線驅動器電路時脈信號（GCK1 )的四分 之一循環而落後在該信號的相位之後的信號，第三掃描線 驅動器電路時脈信號（GCK3 )係相位以第一掃描線驅動 器電路時脈信號（GCK1 )的二分之一循環而落後在該信 號的相位之後的信號，以及第四掃描線驅動器電路時脈信 號（GCK4 )係相位以第一掃描線驅動器電路時脈信號（ GCK1 )的四分之三循環而落後在該信號的相位之後的信S -34 - 201220292 ' and the high level potential is output from the terminal 27. In the period t7, the potentials input to the terminals 23 and 26 are at a high level, and the potentials input to the terminals 21, 22, and 24 are at a low level. Therefore, the low level potential is output from the terminal 25 and the terminal 27. Next, Fig. 8C shows another example of the timing chart of the pulse wave output circuit depicted in Fig. 8A. The periods t1 to t7 shown in Fig. 8C have the same length of time. The respective lengths of the periods t1 to t7 correspond to one-third of the pulse width of each of the first to fourth scan line driver circuit clock signals (GCK1 to GCK4), and correspond to the first to sixth pulses One-third of the pulse width of each of the wave width control signals (PWC1 to PWC6). In the pulse wave output circuit depicted in FIG. 8A, the potential input to the terminal 21 in the period t1 to t3 is at a high level, and is input to the terminal 22, the terminal 23, the terminal 24, and the terminal 26. The potential is at a low level. Therefore, in the period t1 to t3, the low level potential is output from the terminal 25 and the terminal 27. Then, the potentials input to the terminals 22 and 24 are at a high level, and the potentials input to the terminals 21, 23, and 26 are in a low level period t4 to t6, and the high level is It is output from the terminal 2 5 and the terminal 27. <Operation Example of Scan Line Driver Circuit in Full Color Image Display Period 301> -35- 201220292 Next 'For example, the scanning line driver circuit 11 described with reference to FIGS. 6, 7, and 8A will be explained. The full color image shown in FIG. 3 shows the operation of the scan line driver circuit 11 in the period 301. Fig. 9 shows an example of a timing chart of the scanning line driver circuit 11 in the full-color image display period 301. The sub-frame period SF1, the sub-picture frame period SF2, and the sub-frame period SF3 are set in one of the picture frame periods in Fig. 9. In Fig. 9, a timing chart using the sub-frame period SF1 is taken as a typical example. Note that in Fig. 9, m is 3j. In FIG. 9, the scan lines GL1 to GLk are connected to the pixels in the area 101, the scan lines GLk+Ι to the scan line GL2k are connected to the pixels in the area 102, and the scan lines GL2k+1 to GL3k are connected. Connected to the pixels in area 103. The first scan line driver circuit clock signal (GCK1) periodically repeats the high level potential (high power supply potential (Vdd)) and the low level potential (low power supply potential (Vss)), and has a duty ratio of 1/4. . Further, the second scan line driver circuit clock signal (GCK2) is phased by a quarter of the first scan line driver circuit clock signal (GCK1) and falls behind the phase of the signal, the third scan The line driver circuit clock signal (GCK3) is a phase that lags behind the phase of the signal by one-half of the first scan line driver circuit clock signal (GCK1), and the fourth scan line driver circuit clock The signal (GCK4) is a phase that lags behind the phase of the signal by a three-quarter cycle of the first scan line driver circuit clock signal (GCK1)

S -36- 201220292S -36- 201220292

Drfe 硫。 第一脈波寬度控制信號（PWC 1 )週期性地重複 準電位（高電源供應電位（Vdd ))及低位準電位（ 源供應電位（Vss ))，且具有1/3的責務比。第二 寬度控制信號（PWC2 )係相位以第一脈波寬度控制 (PWC1 )的六分之一循環而落後在該信號之後的信 第三脈波寬度控制信號（PWC3 )係相位以第一脈波 控制信號（PWC 1 )的三分之一循環而落後在該信號 的信號，第四脈波寬度控制信號（PWC4 )係相位以 脈波寬度控制信號（PWC1 )的二分之一循環而落後 信號之後的信號，第五脈波寬度控制信號（PWC5 ) 位以第一脈波寬度控制信號（PWC1 )的三分之二循 落後在該信號之後的信號，以及第六脈波寬度控制信 PWC6 )係相位以第一脈波寬度控制信號(PWC1 )的 之五循環而落後在該信號之後的信號。 在第9圖中，第一至第四掃描線驅動器電路時脈 (GCK1至GCK4)之每一者的脈波寬度對第一至第 波寬.度控制信號（PWC1至PWC6)之每一者的脈波 之比率係3 : 2。 子像框週期SF各自起動，以回應於掃描線驅動 路起動脈波信號（GSP )之脈波電位的下降。掃描線 器電路起動脈波信號（GSP )的脈波寬度係與第一至 掃描線驅動器電路時脈信號（GCK1至GCK4)之每 的脈波寬度實質地相同。掃描線驅動器電路起動脈波 高位 低電 脈波 信號 號， 寬度 之後 第一 在該 係相 環而 號（ 六分 信號 六脈 寬度 器電 驅動 第四 —者 信號 -37- 201220292 (GSP )之脈波電位的下降係與第一掃描線驅動器電路時 脈信號（GCK1 )之脈波電位的上升實質地同步。掃描線 驅動器電路起動脈波信號（GSP )之脈波電位的下降以第 —脈波寬度控制信號（PWC1)的六分之一循環而落後在 第一脈波寬度控制信號（PWC 1 )之脈波電位的上升之後 〇 在第8A圖中所描繪的脈波輸出電路係依據第8B圖中 之時序圖，而藉由上述信號所操作。因而，如第9圖中所 描繪地，脈波係順序移位之選擇信號被供應到區域1 〇 1中 的掃描線GL1至GLk »進一步地，所供應到掃描線GL1 至GLk之選擇信號的脈波係各自移位對應於二分之三之脈 波寬度的週期。所供應到掃描線GL1至GLk之選擇信號 的各自之脈波寬度係與第一至第六脈波寬度控制信號（ PWC1至PWC6)的每一者之脈波寬度幾乎相同。 如在區域1 〇〗的情況中似地，脈波係順序移位之選擇 信號被供應到區域102中的掃描線GLk + Ι至GL2k。進一 步地，所供應到掃描線GLk+Ι至GL2k之選擇信號的脈波 相位，係各自移位對應於二分之三脈波寬度的週期。所供 應到掃描線GLk+Ι至GL2k之選擇信號的各自之脈波寬度 ，係與第一至第六脈波寬度控制信號（PWC1至PWC6 ) 的每一者之脈波寬度幾乎相同。 如在區域1 〇 1的情況中似地，脈波係順序移位之選擇 信號被供應到區域103中的掃描線GL2k+l至GL3k。進一 步地，所供應到掃描線GL2k+l至GL3k之選擇信號的脈Drfe sulfur. The first pulse width control signal (PWC 1 ) periodically repeats the quasi-potential (high power supply potential (Vdd)) and the low level potential (source supply potential (Vss)) with a 1/3 duty ratio. The second width control signal (PWC2) is phased by one-sixth of a first pulse width control (PWC1) and the third pulse width control signal (PWC3) behind the signal is phase-first with a first pulse One third of the wave control signal (PWC 1 ) lags behind the signal of the signal, and the fourth pulse width control signal (PWC4 ) is phased by one-half of the pulse width control signal (PWC1). The signal after the signal, the fifth pulse width control signal (PWC5) bit follows the signal after the signal by two-thirds of the first pulse width control signal (PWC1), and the sixth pulse width control signal PWC6 The phase is lag behind the signal by the fifth cycle of the first pulse width control signal (PWC1). In FIG. 9, the pulse width of each of the first to fourth scan line driver circuit clocks (GCK1 to GCK4) is opposite to each of the first to first wave width control signals (PWC1 to PWC6). The ratio of pulse waves is 3: 2. The sub-frame periods SF are each activated in response to a drop in the pulse wave potential of the arterial wave signal (GSP) driven by the scan line. The pulse width of the arterial wave signal (GSP) of the scan line circuit is substantially the same as the pulse width of each of the first to scan line driver circuit clock signals (GCK1 to GCK4). The scan line driver circuit starts from the high-frequency low-voltage pulse signal number of the arterial wave, and the first is the number in the phase loop after the width (six-segment signal six-pulse width electric drive fourth--signal-37-201220292 (GSP) The drop of the pulse wave potential is substantially synchronized with the rise of the pulse wave potential of the clock signal (GCK1) of the first scan line driver circuit. The scan line driver circuit causes the pulse wave potential of the arterial wave signal (GSP) to decrease by the first pulse One-half cycle of the wave width control signal (PWC1) lags behind the rise of the pulse potential of the first pulse width control signal (PWC 1 ). The pulse output circuit depicted in FIG. 8A is based on the The timing chart in Fig. 8B is operated by the above signal. Thus, as depicted in Fig. 9, the selection signal of the pulse wave sequential shift is supplied to the scanning lines GL1 to GLk in the region 1 〇1 » Further, the pulse trains of the selection signals supplied to the scanning lines GL1 to GLk are each shifted by a period corresponding to a pulse width of three-thirds. The respective pulse waves of the selection signals supplied to the scanning lines GL1 to GLk width The pulse width of each of the first to sixth pulse width control signals (PWC1 to PWC6) is almost the same. As in the case of the region 1 〇, the selection signal of the pulse wave sequential shift is supplied. The scanning lines GLk + Ι to GL2k in the region 102. Further, the pulse wave phases of the selection signals supplied to the scanning lines GLk + Ι to GL2k are each shifted by a period corresponding to a width of three-thirds of the pulse width. The respective pulse widths of the selection signals supplied to the scanning lines GLk+Ι to GL2k are almost the same as the pulse widths of each of the first to sixth pulse width control signals (PWC1 to PWC6). In the case of the region 1 〇1, the selection signals of the pulse wave system sequentially shifted are supplied to the scanning lines GL2k+1 to GL3k in the region 103. Further, the selection signals supplied to the scanning lines GL2k+1 to GL3k are selected. Pulse

S -38- 201220292 波相位，係各自移位對應於二分之三之脈波寬度的週期。 所供應到掃描線GL2k+l至GL3k之選擇信號的各自之脈 波寬度，係與第一至第六脈波寬度控制信號（PWC1至 PWC6 )的每一者之脈波寬度幾乎相同。 所供應至掃描線GL1，GLk+Ι，及GL2k+l之選擇信 號的相位係順序地移位對應於二分之一之脈波寬度的週期 〈在單色靜止影像顯示週期303中之掃描線驅動器電路的 操作實例〉 接著，例如，將使用參照第6圖、第7圖、及第8A 圖所描述之掃描線驅動器電路1 1來說明第3圖中所示的 單色靜止影像顯示週期303中之掃描線驅動器電路11的 操作。 第10圖顯示在單色靜止影像顯示週期3 03中之掃描 線驅動器電路11的時序圖之實例。在第1〇圖中，其中執 行對像素之影像信號的寫入之寫入週期，及其中保持影像 之保持週期係設置於一像框週期中。 第一至第四掃描線驅動器電路時脈信號（GCK1至 GCK4)係與第9圖中之該等信號相同的信號。 第一脈波寬度控制信號（PWC1)及第四脈波寬度控 制信號（P W C4 )週期性地重複高位準電位（高電源供應 電位（Vdd))及低位準電位（低電源供應電位（Vss)) ，且具有1/2的責務比於寫入週期中之第一個三分之一週 -39- 201220292 期中。進一步地，在寫入週期的其他週期中，第一脈波寬 度控制信號（PWC1)及第四脈波寬度控制信號（PWC4) 具有低位準電位。第四脈波寬度控制信號（PWC4 )係相 位以第一脈波寬度控制信號（PWC 1 )的二分之一循環而 落後在該信號之後的信號。 第二脈波寬度控制信號（PWC 2 )及第五脈波寬度控 制信號（PWC5 )週期性地重複高位準電位（高電源供應 電位（Vdd))及低位準電位（低電源供應電位（Vss)) ，且具有1/2的責務比於寫入週期中之中間三分之一週期 中。在寫入週期的其他週期中，第二脈波寬度控制信號（ PWC2 )及第五脈波寬度控制信號（PWC5 )具有低位準電 位。第五脈波寬度控制信號（PWC5 )係相位以第二脈波 寬度控制信號（PWC 2 )的二分之一循環而落後在該信號 之後的信號。 第三脈波寬度控制信號（PWC3 )及第六脈波寬度控 制信號（PWC6 )週期性地重複高位準電位（高電源供應 電位（Vdd))及低位準電位（低電源供應電位（Vss)) ，且具有1/2的責務比於寫入週期中之最後三分之一週期 中。在寫入週期的其他週期中，第三脈波寬度控制信號（ PWC3 )及第六脈波寬度控制信號（PWC6 )具有低位準電 位。第六脈波寬度控制信號（PWC6 )係相位以第三脈波 寬度控制信號（PWC 3 )的二分之一循環而落後在該信號 之後的信號。 在第1 0圖中，第一至第四掃描線驅動器電路時脈信 -40-S -38- 201220292 Wave phase, each shifting the period corresponding to the pulse width of three-thirds. The respective pulse widths of the selection signals supplied to the scanning lines GL2k+1 to GL3k are almost the same as the pulse widths of each of the first to sixth pulse width control signals (PWC1 to PWC6). The phase of the selection signal supplied to the scanning lines GL1, GLk+Ι, and GL2k+1 is sequentially shifted by a period corresponding to one-half of the pulse width (scanning line in the monochrome still image display period 303) Operation Example of Driver Circuit> Next, for example, the monochrome line still image display period 303 shown in FIG. 3 will be described using the scan line driver circuit 1 1 described with reference to FIGS. 6, 7, and 8A. The operation of the scan line driver circuit 11 is in progress. Fig. 10 shows an example of a timing chart of the scan line driver circuit 11 in the monochrome still image display period 303. In the first diagram, the writing period in which the writing of the image signal of the pixel is performed, and the holding period in which the image is held is set in a frame period. The first to fourth scan line driver circuit clock signals (GCK1 to GCK4) are the same signals as the signals in FIG. The first pulse width control signal (PWC1) and the fourth pulse width control signal (PW C4) periodically repeat the high level potential (high power supply potential (Vdd)) and the low level potential (low power supply potential (Vss) ), and has 1/2 of the responsibilities than the first one-third of the write cycle -39-201220292. Further, in other periods of the write cycle, the first pulse width control signal (PWC1) and the fourth pulse width control signal (PWC4) have a low level potential. The fourth pulse width control signal (PWC4) is a signal that lags behind the signal by one-half of the first pulse width control signal (PWC 1 ). The second pulse width control signal (PWC 2 ) and the fifth pulse width control signal (PWC5) periodically repeat the high level potential (high power supply potential (Vdd)) and the low level potential (low power supply potential (Vss) ) and has a 1/2 duty than the middle third of the write cycle. In the other periods of the write cycle, the second pulse width control signal (PWC2) and the fifth pulse width control signal (PWC5) have low level potentials. The fifth pulse width control signal (PWC5) is a signal that lags behind the signal by one-half of the second pulse width control signal (PWC 2 ). The third pulse width control signal (PWC3) and the sixth pulse width control signal (PWC6) periodically repeat the high level potential (high power supply potential (Vdd)) and the low level potential (low power supply potential (Vss)) And have a 1/2 duty than the last third of the write cycle. In the other periods of the write cycle, the third pulse width control signal (PWC3) and the sixth pulse width control signal (PWC6) have low level potentials. The sixth pulse width control signal (PWC6) is a signal that lags behind the signal by one-half of the third pulse width control signal (PWC3). In Fig. 10, the first to fourth scan line driver circuit clock signals -40-

S 201220292 號（GCK1至GCK4)之每一者的脈波寬度對第一至第六 脈波寬度控制信號（PWC1至PWC6)之每一者的脈波寬 度之比率例1 : 1。 像框週期F起動以回應於掃描線驅動器電路起動脈波 信號（GSP )之脈波電位的下降。掃描線驅動器電路起動 脈波信號（GSP )的脈波寬度係與第一至第四掃描線驅動 器電路時脈信號（GCK1至GCK4)之每一者的脈波寬度 幾乎相同。掃描線驅動器電路起動脈波信號（GSP )之脈 波電位的下降係與第一掃描線驅動器電路時脈信號（ GCK1 )之脈波電位的上升同步。此外，掃描線驅動器電 路起動脈波信號（GSP )之脈波電位的下降係與第一脈波 寬度控制信號（PWC 1 )之脈波電位的上升同步。 在第8A圖中所描繪的脈波輸出電路係依據第8C圖中 之時序圖，而藉由上述信號所操作。因而’如第1〇圖中 所描繪地，脈波係順序移位之選擇信號被供應到區域1 〇 1 中的掃描線GL1至GLk。進一步地’所供應到掃描線GL1 至GLk之選擇信號的相位係各自移位對應於脈波寬度的週 期。所供應到掃描線GL1至GLk之選擇信號的各自之脈 波寬度係與第一至第六脈波寬度控制信號（PWC1至 PWC6 )的每一者之脈波寬度幾乎相同。 在對區域1 〇 1中之掃描線GL1至GLk供應脈波係順 序移位的選擇信號之後’係跟著供應脈波順序移位的選擇 信號至區域1 02中之掃描線GLk + Ι至GL2k。所供應到掃 描線GLk+Ι至GL2k之選擇信號的相位’係各自移位對應 -41 - 201220292 於脈波寬度的週期。所供應到掃描線GLk+l至GL2k之選 擇信號的各自之脈波寬度，係與第一至第六脈波寬度控制 信號（PWC1至PWC6)的每一者之脈波寬度幾乎相同。 在對區域102中之掃描線GLk+l至GL2k供應脈波係 順序移位的選擇信號之後，係跟著供應脈波順序移位的選 擇信號至區域103中之掃描線GL2k+l至GL3k。進一步地 ，所供應到掃描線GL2k+l至GL3k之選擇信號的相位係 各自移位對應於脈波寬度的週期。所供應到掃描線 GL2k+l至GL3k之選擇信號的各自之脈波寬度，係與第一 至第六脈波寬度控制信號（PWC1至PWC6)的每一者之 脈波寬度幾乎相同。 接著，在保持週期中，停止對於掃描線驅動器電路11 之驅動信號及電源供應電位的供應。具體而言，首先，停 止掃描線驅動器電路起動脈波信號（GSP )的供應，藉以 在掃描線驅動器電路11中停止來自脈波輸出電路之選擇 信號的輸出，且終止藉由該脈波而在所有掃描線中之選擇 。之後，停止對於掃描線驅動器電路11之電源供應電位 Vdd的供應。注意的是，例如，停止輸入或停止供應意指 要使其中輸入信號或電位之佈線在浮動狀態中’或要施加 低位準的電位至其中輸入信號或電位之佈線。依據上述方 法，可在停止操作中防止掃描線驅動器電路11之故障。 除了上述結構之外，可停止對於掃描線驅動器電路11供 應第一至第四掃描線驅動器電路時脈信號（GCK1至 GCK4 )，及第一至第六脈波寬度控制信號（PWC1至 • 42-The ratio of the pulse width of each of S 201220292 (GCK1 to GCK4) to the pulse width of each of the first to sixth pulse width control signals (PWC1 to PWC6) is 1:1. The frame period F is initiated in response to a drop in the pulse wave potential of the arterial wave signal (GSP) of the scan line driver circuit. The scanning line driver circuit starts the pulse wave width of the pulse signal (GSP) to be almost the same as the pulse width of each of the first to fourth scanning line driver circuit clock signals (GCK1 to GCK4). The decrease in the pulse potential of the arterial wave signal (GSP) of the scanning line driver circuit is synchronized with the rise of the pulse wave potential of the clock signal (GCK1) of the first scanning line driver circuit. Further, the drop of the pulse wave potential of the arterial wave signal (GSP) of the scanning line driver circuit is synchronized with the rise of the pulse wave potential of the first pulse width control signal (PWC 1 ). The pulse wave output circuit depicted in Fig. 8A is operated by the above signal in accordance with the timing chart in Fig. 8C. Thus, as depicted in Fig. 1, the selection signal of the sequential shift of the pulse wave system is supplied to the scanning lines GL1 to GLk in the region 1 〇 1 . Further, the phase of the selection signals supplied to the scanning lines GL1 to GLk are each shifted by a period corresponding to the pulse width. The respective pulse widths of the selection signals supplied to the scanning lines GL1 to GLk are almost the same as the pulse widths of each of the first to sixth pulse width control signals (PWC1 to PWC6). After the scan lines GL1 to GLk in the area 1 供应 1 are supplied with the selection signals of the pulse train sequentially shifted, the selection signals sequentially shifted by the supply pulse are supplied to the scanning lines GLk + Ι to GL2k in the area 102. The phase ' of the selection signals supplied to the scanning lines GLk+Ι to GL2k is shifted by a period corresponding to -41 - 201220292 in the pulse width. The respective pulse widths of the selection signals supplied to the scanning lines GLk+1 to GL2k are almost the same as the pulse widths of each of the first to sixth pulse width control signals (PWC1 to PWC6). After the scanning lines GLk+1 to GL2k in the region 102 are supplied with the selection signals sequentially shifted by the pulse train, the selection signals sequentially shifted by the supply pulses are supplied to the scanning lines GL2k+1 to GL3k in the region 103. Further, the phases of the selection signals supplied to the scanning lines GL2k+1 to GL3k are each shifted by a period corresponding to the pulse width. The respective pulse widths of the selection signals supplied to the scanning lines GL2k+1 to GL3k are almost the same as the pulse widths of each of the first to sixth pulse width control signals (PWC1 to PWC6). Next, in the sustain period, the supply of the drive signal and the power supply potential to the scanning line driver circuit 11 is stopped. Specifically, first, the supply of the arterial wave signal (GSP) by the scan line driver circuit is stopped, whereby the output of the selection signal from the pulse wave output circuit is stopped in the scan line driver circuit 11, and the pulse wave is terminated by the pulse wave The choice of all scan lines. Thereafter, the supply of the power supply potential Vdd to the scanning line driver circuit 11 is stopped. Note that, for example, the stop input or the stop supply means that the wiring in which the input signal or potential is placed in a floating state or the potential of the low level is applied to the wiring in which the signal or potential is input. According to the above method, the failure of the scanning line driver circuit 11 can be prevented in the stop operation. In addition to the above structure, the supply of the first to fourth scan line driver circuit clock signals (GCK1 to GCK4) and the first to sixth pulse width control signals (PWC1 to • 42-) for the scan line driver circuit 11 can be stopped.

S 201220292 PWC6 )。 藉由停止對於掃描線驅動器電路！ 源供應電位的供應，低位準之電位會被 線 GL1 至 GLk、掃描線 GLk+Ι 至 GL2k+l 至 GL3k。 注意的是，在單色移動影像顯示週 週期中之掃描線驅動器電路11的操作 顯示週期303中之操作相同。 依據本發明之一實施例，係使用截 電晶體，而可藉以延長所施加至液晶元 期。因此，可確保如第10圖中所示之 週期，且可減低掃描線驅動器電路1 1 . 第9圖中所示之操作的驅動頻率更低。 消耗低的液晶顯示裝置。 〈信號線驅動器電路1 2的組態實例〉 第11圖描繪包含於第2A圖中所示 的信號線驅動器電路1 2之組態實例。名 信號線驅動器電路1 2包含移位暫存器 群123，該移位暫存器120具有第一至 及該開關元件組群1 23控制影像信號 SL1至SLn之供應。 具體而言，開關元件組群1 23包1 121 η。電晶體121_1至121 η的第一 1之驅動信號及電 供應到所有的掃描 GL2k、及掃描線 期302中，於寫入 係與單色靜止影像 止狀態電流極低之 件之電壓的保持週 保持週期一樣長的 的驅動頻率成爲比 因而，可獲得功率 之液晶顯示裝置中 £第1 1圖中所示之 120及開關元件組 第η輸出端子，以 (DATA)對信號線 爹電晶體121_1至 端子連接至用以供 -43- 201220292 應影像信號（DATA)之佈線。電晶體121_1至121_n的 第二端子係分別連接到信號線SL1至SLri。電晶體121_1 至121_!1的閘極電極係分別連接到移位暫存器12〇的第一 至第η輸出端子。 移位暫存器1 20依據諸如信號線驅動器電路起動脈波 信號（SSP )及信號線驅動器電路時脈信號（SCK )之驅 動信號而操作，且自第一至第η輸出端子而輸出其中脈波 係順序移位之信號。該等信號係輸入至電晶體的閘極電極 ，而使該等電晶體121_1至121_η順序地導通。 第12Α圖顯示全彩色影像顯示週期301中之所供應至 信號線的影像信號（DATA)之時序的實例。如第12Α圖 中所示地，在其中所輸入至二掃描線之選擇信號的脈波彼 此互相重疊的週期中，係取樣用於脈波首先出現之掃描線 的影像信號（DATA)，且將其輸入至第11圖中所描繪之 信號線驅動器電路1 2中的該等信號線。特定地，所輸入 至掃描線GL1之選擇信號的脈波及所輸入至掃描線GLk+1 之選擇信號的脈波彼此互相重疊於對應至脈波寬度之二分 之一的週期t4中。掃描線GL1的脈波出現在掃描線 GLk+Ι的脈波之前。在其中該等脈波彼此互相重疊的週期 中，係取樣包含於掃描線GL1之影像信號（DATA)中的 影像信號（資料1 )，且將其輸入至信號線SL1至SLn。 以相似之方式’在週期Μ中，係取樣用於掃描線 GLk + Ι之影像信號（資料k+Ι)，且將其輸入至信號線 SL1至SLn。在週期t6中，係取樣用於掃描線GL2k+l之S 201220292 PWC6 ). By stopping the scan line driver circuit! The supply of the source supply potential, the low level potential will be from line GL1 to GLk, scan line GLk+Ι to GL2k+l to GL3k. Note that the operations in the operation display period 303 of the scanning line driver circuit 11 in the monochrome moving image display cycle are the same. In accordance with an embodiment of the present invention, a cut-off transistor is used to extend the application to the liquid crystal cell. Therefore, the period as shown in Fig. 10 can be secured, and the scanning line driver circuit 1 1 can be reduced. The driving frequency of the operation shown in Fig. 9 is lower. Low consumption of liquid crystal display devices. <Configuration Example of Signal Line Driver Circuit 12> Fig. 11 depicts a configuration example of the signal line driver circuit 12 shown in Fig. 2A. The name signal line driver circuit 12 includes a shift register group 123 having a supply of the first to and the switching element group 1 23 to control the image signals SL1 to SLn. Specifically, the switching element group 1 23 includes 1 121 η. The driving signals of the first one of the transistors 121_1 to 121 η and the electric power are supplied to all of the scanning GL2k and the scanning line period 302, and the voltages of the writing unit and the monochromatic still image stop state are extremely low. The drive frequency which maintains the same period of time is a ratio of the 120 shown in FIG. 11 and the nth output terminal of the switching element group in the liquid crystal display device which can obtain power, and the (DATA) pair signal line 爹 transistor 121_1 Connect the terminal to the wiring for the -43-201220292 image signal (DATA). The second terminals of the transistors 121_1 to 121_n are connected to the signal lines SL1 to SLri, respectively. The gate electrodes of the transistors 121_1 to 121_!1 are connected to the first to nth output terminals of the shift register 12A, respectively. The shift register 1 20 operates in accordance with a driving signal such as a signal line driver circuit originating arterial wave signal (SSP) and a signal line driver circuit clock signal (SCK), and outputs a pulse from the first to the nth output terminals. The signal of the sequence shift of the wave system. The signals are input to the gate electrodes of the transistors, and the transistors 121_1 to 121_n are sequentially turned on. Fig. 12 is a diagram showing an example of the timing of the image signal (DATA) supplied to the signal line in the full-color image display period 301. As shown in FIG. 12, in a period in which the pulse waves of the selection signals input to the two scanning lines overlap each other, the image signal (DATA) for the scanning line in which the pulse wave first appears is sampled, and It is input to the signal lines in the signal line driver circuit 12 depicted in FIG. Specifically, the pulse waves of the selection signal input to the scanning line GL1 and the pulse waves of the selection signal input to the scanning line GLk+1 overlap each other in the period t4 corresponding to one-half of the pulse width. The pulse wave of the scanning line GL1 appears before the pulse wave of the scanning line GLk+Ι. In a period in which the pulse waves overlap each other, the image signal (data 1) included in the image signal (DATA) of the scanning line GL1 is sampled and input to the signal lines SL1 to SLn. In a similar manner, in the period ,, the image signal for the scanning line GLk + ( (data k + Ι) is sampled and input to the signal lines SL1 to SLn. In the period t6, the sampling is for the scanning line GL2k+l

S -44- 201220292 影像信號（資料2k+l )，且將其輸入至信號線SL1至SLn 。在週期t7中，係取樣用於掃描線GL2之影像信號（資 料2 )，且將其輸入至信號線SL1至SLn。而且，在隨著 週期t7之後的每一週期中，係重複相同的操作，且輸入 影像信號（DATA )至像素部。 換言之，對於信號線S L 1至S Ln之影像信號的輸入係 以以下順序而執行：所連接至掃描線GLs之像素（s係小 於k之自然數）；所連接至掃描線GL2k + s之像素；以及 所連接至掃描線GLs+ 1之像素。 第12B圖顯示在單色移動影像顯示週期302及單色靜 止影像顯示週期303之中所設置的寫入週期中’所供應至 信號線的影像信號（DATA)之時序的實例。如第12B圖 中所示地，在其中出現選擇信號的脈波被輸入至掃描線的 週期中，係取樣用於掃描線的影像信號（DATA ) ’且將 其輸入至第11圖中所描繪之信號線驅動器電路12中的信 號線。具體而言，在其中出現選擇信號的脈波被輸入至掃 描線GL1的週期中，係取樣包含在用於掃描線GL1之影 像信號（DATA)中的影像信號（資料丨）’且將其輸入至 信號線SL1至SLn。 相同的操作係重複於跟在掃描線G L 1之後的各自及每 個掃描線中，藉以寫入影像信號（data )於像素部之中 〇 在單色靜止影像顯示週期303中的保持週期中’係停 止對於移位暫存器120之信號線驅動器電路起動脈波信號 -45- 201220292 (SSP)的供應，以及對於信號線驅動器電路1 2之影像信 號（DATA )的供應。特定地，例如首先，停止信號線·驅 動器電路起動脈波信號（SSP )的供應，以停止影像信號 的取樣於信號線驅動器電路1 2中。然後，停止對於信號 線驅動器電路1 2之影像信號的供應及電源供應電位的供 應。依據該方法，可防止在停止信號線驅動器電路12的 操作中之信號線驅動器電路1 2發生故障。此外，可停止 對於信號線驅動器電路1 2之信號線驅動器電路時脈信號 (SCK)的供應。 〈液晶顯示裝置的操作實例〉 第13圖顯示上述液晶顯示裝置中之全彩色影像顯示 週期301中的選擇信號之掃描時序及背光之照明時序。在 第13圖中，垂直軸表示像素部的列，以及水平軸表示時 間。 如第1 3圖中所示地，在此實施例中所敘述的液晶顯 示裝置中，可使用其中選擇信號係供應至掃描線GL1，且 然後，選擇信號係供應至距離掃描線GL 1第k列的掃描線 GLk+Ι之驅動方法於全彩色影像顯示週期301中。因此， 可在一子像框週期SF中以此方式來供應影像信號之像素 ，亦即，順序選擇所連接到掃描線GL1之η個像素至所連 接到掃描線GLk之η個像素，順序選擇所連接到掃描線 GLk+Ι之η個像素至所連接到掃描線GL2k之η個像素， 以及順序選擇所連接到掃描線GL2k+l之η個像素至所連S -44- 201220292 Image signal (data 2k+l) and input it to signal lines SL1 to SLn. In the period t7, the image signal for the scanning line GL2 (sampling 2) is sampled and input to the signal lines SL1 to SLn. Moreover, in each cycle following the period t7, the same operation is repeated, and an image signal (DATA) is input to the pixel portion. In other words, the input of the image signals for the signal lines SL 1 to S Ln is performed in the following order: pixels connected to the scanning line GLs (s are less than the natural number of k); pixels connected to the scanning line GL2k + s And the pixel connected to the scan line GLs+1. Fig. 12B shows an example of the timing of the image signal (DATA) supplied to the signal line in the writing period set in the monochrome moving image display period 302 and the monochrome still image display period 303. As shown in FIG. 12B, in the period in which the pulse wave in which the selection signal appears is input to the scanning line, the image signal (DATA) for the scanning line is sampled and input to the image depicted in FIG. The signal line in the signal line driver circuit 12. Specifically, in the period in which the pulse wave in which the selection signal appears is input to the scanning line GL1, the image signal (data 丨) contained in the image signal (DATA) for the scanning line GL1 is sampled and input. To the signal lines SL1 to SLn. The same operation is repeated in each and every scan line following the scan line GL1, thereby writing a video signal (data) in the pixel portion in the hold period in the monochrome still image display period 303' The supply of the arterial wave signal -45-201220292 (SSP) to the signal line driver circuit of the shift register 120 and the supply of the image signal (DATA) to the signal line driver circuit 12 are stopped. Specifically, for example, first, the supply of the arterial wave signal (SSP) by the signal line driver circuit is stopped to stop sampling of the image signal in the signal line driver circuit 12. Then, the supply of the image signal to the signal line driver circuit 12 and the supply of the power supply potential are stopped. According to this method, the failure of the signal line driver circuit 12 in the operation of the stop signal line driver circuit 12 can be prevented. Further, the supply of the signal line driver circuit clock signal (SCK) to the signal line driver circuit 12 can be stopped. <Operation Example of Liquid Crystal Display Device> Fig. 13 shows the scanning timing of the selection signal and the illumination timing of the backlight in the full-color image display period 301 in the above liquid crystal display device. In Fig. 13, the vertical axis represents the column of the pixel portion, and the horizontal axis represents the time. As shown in FIG. 3, in the liquid crystal display device described in this embodiment, a selection signal is supplied to the scanning line GL1, and then the selection signal is supplied to the distance scanning line GL1. The driving method of the scanning line GLk+Ι of the column is in the full color image display period 301. Therefore, the pixels of the image signal can be supplied in this manner in a sub-frame period SF, that is, sequentially select n pixels connected to the scan line GL1 to n pixels connected to the scan line GLk, and sequentially select the pixels. Connecting n pixels of the scan line GLk+Ι to n pixels connected to the scan line GL2k, and sequentially selecting n pixels connected to the scan line GL2k+1 to be connected

S -46- 201220292 接到掃描線GL3k之η個像素。 具體而言，在第13圖中之第一子像框週期SF1中’ 用於紅色（R )的影像信號係寫入於所連接到掃描線G L1 至GLk之該等像素’且然後’紅色（R)的光係供應至所 連接掃描線GL1至GLk之該等像素。透過上述結構’可 將用於紅色（R )之影像顯示於對應到掃描線GL 1至GLk 之像素部的區域101中。 進一步地，在該第一子像框週期SF1中’用於綠色（ G )的影像信號係寫入於所連接到掃描線G L k + 1至G L 2 k 之該等像素，且然後’綠色（G )的光係供應至所連接到 掃描線GLk+Ι至GL2k之該等像素。透過上述結構’可將 用於綠色（G)之影像顯示於對應到掃描線GLk+Ι至 GL2k之像素部的區域1〇2中。 進一步地，在該第一子像框週期SF1中，用於藍色（ B)的影像信號係寫入於所連接到掃描線GL2k+l至GL3k 之該等像素，且然後’藍色（B )的光係供應至所連接到 掃描線GL2k+l至GL：3k之該等像素。透過上述結構’可 將用於藍色（B)之影像顯示於對應到掃描線GL2k+l至 GL3k之像素部的區域中。 與第一子像框週期SF1之操作相同的操作係重複於第 二子像框週期SF2及第三子像框週期SF3之中。惟，在第 二子像框週期SF2之中’用於藍色（B)之影像係顯示於 對應到掃描線GL1至GLk之像素部的區域101中；用於 紅色（R)之影像係顯示於對應到掃描線GLk+Ι至GL2k -47- 201220292 之之像素部的區域102中；以及用於綠色（G)之影像係 顯示於對應到掃描線GL2k+l至GL3k之像素部的區域103 中。進一步地，在第三子像框週期SF3之中，用於綠色（ G )之影像係顯示於對應到掃描線GL 1至GLk之像素部的 區域1 0 1中；用於藍色（B )之影像係顯示於對應到掃描 線GLk+Ι至GL2k之像素部的區域102中；以及用於紅色 (R)之影像係顯示於對應到掃描線GL2k+l至GL3k之像 素部的區域103中。 在此方式中，第一至第三子像框週期SF1至SF3係終 止於掃描線GL之各自.及每個掃描線中，亦即，完成一像 框週期，而全彩色影像可藉以顯示於像素部之中。 注意的是，在本發明之一實施例中，可將該等區域之 每一者畫分成爲區域，且在所畫分的區域中，當影像信號 之寫入終止時，背光之照明可順序地起動。例如，可使用 以下：在區域101中，用於紅色（R)之影像信號係寫入 於連接到掃描線GL1至GLh ( h係小於或等於k/4之自然 數）的像素中；且然後，當用於紅色（R )之影像信號係 寫入於連接到掃描線GLh+Ι至GL2h的像素之中時的同時 ，紅色（R)之光係供應至連接到掃描線GL1至GLh的像 素。 第14圖顯示上述液晶顯示裝置中之單色靜止影像顯 示週期3 03中的選擇信號之掃描時序及背光之照明時序。 在第14圖中，垂直軸表示像素部中的列，以及水平軸表 示時間。S -46- 201220292 Receives n pixels of the scan line GL3k. Specifically, in the first sub-frame period SF1 in FIG. 13, the image signal for red (R) is written to the pixels connected to the scanning lines G L1 to GLk 'and then 'red' ( The light system of R) is supplied to the pixels of the connected scanning lines GL1 to GLk. The image for red (R) can be displayed in the area 101 corresponding to the pixel portion of the scanning lines GL 1 to GLk through the above structure '. Further, in the first sub-frame period SF1, the image signal for green (G) is written to the pixels connected to the scan lines GL k + 1 to GL 2 k , and then 'green (G The light system is supplied to the pixels connected to the scanning lines GLk+Ι to GL2k. The image for green (G) can be displayed in the area 1〇2 corresponding to the pixel portion of the scanning lines GLk+ to GL2k through the above structure'. Further, in the first sub-frame period SF1, image signals for blue (B) are written to the pixels connected to the scan lines GL2k+1 to GL3k, and then 'blue (B) The light system is supplied to the pixels connected to the scanning lines GL2k+1 to GL: 3k. The image for blue (B) can be displayed in the area corresponding to the pixel portion of the scanning lines GL2k+1 to GL3k through the above structure'. The same operation as the operation of the first sub-frame period SF1 is repeated in the second sub-frame period SF2 and the third sub-frame period SF3. However, in the second sub-frame period SF2, the image for blue (B) is displayed in the region 101 corresponding to the pixel portion of the scanning lines GL1 to GLk; the image for red (R) is displayed in Corresponding to the area 102 of the pixel portion of the scanning line GLk+Ι to GL2k -47-201220292; and the image for green (G) is displayed in the area 103 corresponding to the pixel portion of the scanning lines GL2k+1 to GL3k . Further, among the third sub-frame period SF3, the image for green (G) is displayed in the area 1 0 1 corresponding to the pixel portion of the scanning lines GL 1 to GLk; for the blue (B) The image is displayed in the area 102 corresponding to the pixel portion of the scanning lines GLk+Ι to GL2k; and the image for red (R) is displayed in the area 103 corresponding to the pixel portion of the scanning lines GL2k+1 to GL3k. In this manner, the first to third sub-frame periods SF1 to SF3 are terminated in the respective scan lines GL and in each of the scan lines, that is, a frame period is completed, and the full-color image can be displayed on the pixel portion. Among them. It is noted that, in an embodiment of the present invention, each of the regions may be divided into regions, and in the region of the divided regions, when the writing of the image signal is terminated, the illumination of the backlight may be sequentially Ground start. For example, the following may be used: in the area 101, the image signal for red (R) is written in pixels connected to the scan lines GL1 to GLh (h is a natural number less than or equal to k/4); and then When the image signal for red (R) is written in the pixels connected to the scanning lines GLh+Ι to GL2h, the red (R) light is supplied to the pixels connected to the scanning lines GL1 to GLh. . Fig. 14 is a view showing the scanning timing of the selection signal and the illumination timing of the backlight in the monochrome still image display period 303 in the above liquid crystal display device. In Fig. 14, the vertical axis represents the column in the pixel portion, and the horizontal axis represents the time.

S -48- 201220292 如第〗4圖中所示地，選擇信號係在此實施例中所述 之液晶顯示裝置中的單色靜止影像顯示週期303中’被順 序地供應到掃描線GL1至GL3k。 具體而言，在第14圖中，例如，在區域1〇1中’影 像信號係寫入於連接到掃描線GL1至GLh的像素中；且 然後，當影像信號係寫入於連接到掃描線GLh + Ι至GL2h 的像素之中時的同時，紅色（R)、綠色（G)、及藍色（ B )之混合的白色（W )光係供應至連接到掃描線GL 1至 GLh的像素。然後，相同的操作係執行於各自及每個掃描 線中的像素中，而單色影像可藉以顯示於像素部中。 注意的是，在單色移動影像顯示週期302中，在執行 上述操作於各自及每個掃描線中的像素中之後，可重複該 操作，藉以連續顯示單色影像於像素部之上。 雖然使用其中係利用紅色（R)、綠色（G)、及藍色 (B )之三彩色的光源做爲背光之結構以供依據本發明一 實施例的液晶顯示裝置之用，但本發明之一實施例的液晶 顯示裝置之結構並未受限於此結構。換言之，可組合地使 用顯現各式各樣個別彩色的光源於本發明一實施例之液晶 顯示的背光中。例如，可使用紅色（R)、綠色（G)、藍 色（B)、及白色（W)之四彩色的組合；紅色（R)、綠 或合 ;組 合的 組色 的彩 色三 彩之 四 } 之Y /IV Y色 C黃 色及 黃、 及 } 、Μ /IV \)y B 色 C紅 色紫 藍、 ， ) )C G ( C 色 色青 0 此外’進一步地’可將發射出白色（W)光之光源設 -49- 201220292 置於背光中，以取代藉由混合彩色而形成白色（w) 。發射出白色（W)光之光源具有高發射效率；因此 過利用該光源所形成之背光的使用，可降低功率消耗 其中使用可發射出二互補彩色光源之情況中（例如， 色（B)及黃色（Y)之二彩色光的情況中），可將該 色的光混合，而藉以形成白色（W)的光。選擇性地 組合地使用可發射出淺紅色（R )、淺綠色（G )、淺 (B )、深紅色（R)、深綠色（G)、及深藍色（B 六個彩色的光之光源，或可組合地使用可發射出紅启 )、綠色（G)、藍色（B)、青色（C)、紫紅色（ 、及黃色（Y)之六個彩色的光之光源。 注意的是，例如，可使用紅色（R )、綠色（G ) 藍色（B)之光源所顯現的彩色係受限於，藉由色度 之對應於個別光源的發射彩色之三點所作成的三角形 存在之彩色。因此，藉由進一步增加存在於色度圖上 角形外部的彩色之光源，則可擴展可顯現於液晶顯示 之彩色的範圍，以致可增強彩色再生性。 例如，除了紅色（R )、綠色（G )、及藍色（B 光源之外，可使用顯現以下彩色之任一者的光源於背 中：深藍色（DB)，其存在於實質定位在該三角形之 的點之中，而在從色度圖的中心朝向色度圖上之對應 色光源B的點之方向中；或深紅色（DR)，其存在 質定位在該三角形之外部的點之中，而在從色度圖的 朝向色度圖上之對應於紅色光源R的點之方向中》 的光 ，透 。在 在藍 二彩 ，可 藍色 )之 1 ( R Μ ) 、及 圖上 中所 之三 裝置 )的 光之 外部 於藍 於實 中心S-48-201220292 As shown in Fig. 4, the selection signal is sequentially supplied to the scanning lines GL1 to GL3k in the monochrome still image display period 303 in the liquid crystal display device described in this embodiment. . Specifically, in FIG. 14, for example, in the area 1〇1, the image signal is written in the pixels connected to the scanning lines GL1 to GLh; and then, when the image signal is written in the connection to the scanning line While GLh + is among the pixels of GL2h, a mixture of red (R), green (G), and blue (B) is supplied to the pixels connected to the scanning lines GL 1 to GLh. . Then, the same operation is performed in the pixels in the respective and each scan line, and the monochrome image can be displayed in the pixel portion. Note that in the monochrome moving image display period 302, after the above operations are performed on the pixels in the respective and each scanning line, the operation can be repeated to continuously display the monochrome image on the pixel portion. Although a structure in which a light source of three colors of red (R), green (G), and blue (B) is used as a backlight is used for the liquid crystal display device according to an embodiment of the present invention, the present invention The structure of the liquid crystal display device of an embodiment is not limited to this structure. In other words, a light source exhibiting a wide variety of individual colors can be used in combination in the backlight of the liquid crystal display of one embodiment of the present invention. For example, a combination of four colors of red (R), green (G), blue (B), and white (W); red (R), green, or combination; } Y / IV Y color C yellow and yellow, and }, Μ /IV \)y B color C red purple blue, , ) ) CG ( C color blue 0 and 'further' can emit white (W) The light source is set to -49- 201220292 to be placed in the backlight instead of forming a white color (w) by mixing colors. The light source emitting white (W) light has high emission efficiency; therefore, the backlight formed by the light source is used. Use, can reduce power consumption, in the case of using two complementary color light sources (for example, in the case of two color lights of color (B) and yellow (Y)), the light of the color can be mixed, thereby forming White (W) light. Selectively combined to emit light red (R), light green (G), light (B), deep red (R), dark green (G), and dark blue (B) Six colored light sources, or can be used in combination to emit red start, green (G), blue (B), cyan (C) A source of six colored lights of magenta (and yellow (Y). Note that, for example, the color that can be seen using a red (R), green (G) blue (B) source is limited by The color of the triangle formed by the chromaticity corresponding to the three points of the emission color of the individual light source. Therefore, by further increasing the color light source existing outside the angular shape on the chromaticity diagram, the expandable color can be expressed on the liquid crystal. The range of colors displayed so that color reproducibility can be enhanced. For example, in addition to red (R), green (G), and blue (B light source, a light source that exhibits any of the following colors can be used in the back: dark blue a color (DB) that exists substantially in the point of the triangle, in the direction from the center of the chromaticity diagram toward the point of the corresponding color source B on the chromaticity diagram; or deep red (DR), The presence of light is located in a point outside the triangle, and in the direction from the point of the chromaticity diagram on the chromaticity diagram corresponding to the red light source R, the light is transparent. Blue) 1 ( R Μ ), and on the map It means ter external light) in the blue to the real center of the

S -50- 201220292 做爲背光之光源，較佳地使用複數個發光二極體（ LED )，當與冷陰極螢光燈相較時，可藉以降低功率消耗 且可調整光之強度。光之強度係藉由使用LED於背光中 而被部分地調整，以致可以以高的對比及高的彩色可見度 來執行影像顯示。 此外，在其中形成一影像於像素部中的週期之前及/ 或之後，可提供其中並不執行選擇信號之掃描及背光單元 之照明的週期（非照明週期）。 此外，藉由以背光之彩色的照明順序而提供彼此互相 不同之複數個像框週期，可進一步防止彩色中斷的產生。 〈脈波輸出電路之組態實例2〉 第1 9 A圖描繪脈波輸出電路之組態的另一實例。第 19A圖中所描繪之脈波輸出電路包含除了第8A圖中所描 繪之脈波輸出電路的組態之外的電晶體50»電晶體50之 第一端子係連接至供應有高的電源供應電位之節點。電晶 體50之第二端子係連接至電晶體32的閘極電極，電晶體 34的閘極電極’以及電晶體39的閘極電極。電晶體50之 閘極電極係連接至重設端子（Reset)。 高位準的電位係在跟隨像素部中之背光的色相切換循 環之週期中’被輸入至重設端子；低位準的電位係在其他 週期中被輸入。電晶體50係藉由高位準電位的輸入而導 通。因此’可將每一節點的電位初始化於開啓背光之後的 週期中，使得可防止故障。 -51 - 201220292 注意的是，在其中執行初始化的情況中，提供 週期於其中形成一影像於像素部中之週期的每一週 係必要的。此外，在其中背光係在形成一影像於像 之後而關閉的情況中，可將初始.化執行於其中背光 的週期中。 第19B圖描繪脈波輸出電路之另一組態實例。 圖中所描繪之脈波輸出電路包含除了第8A圖中所 脈波輸出電路的組態之外的電晶體5 1。電晶體5 1 端子係連接至電晶體31的第二端子及電晶體32的 子。電晶體51之第二端子係連接至電晶體3 3的閘 及電晶體3 8的閘極電極。電晶體5 1之閘極電極係 供應有高的電源供應電位之節點。 注意的是，電晶體51係在第8B及8C圖中所 期11至t6中關閉。因此，透過包含電晶體5 1之組 晶體33的閘極電極及電晶體38的閘極電極可在兒 至t6中，與電晶體31之第二端子及電晶體32之 子斷接。因而，可在週期tl至t6中降低脈波輸出 之自舉時的負載。 第20A圖描繪脈波輸出電路之組態的另一實' 20A圖中所描繪之脈波輸出電路包含除了第19B圖 繪之脈波輸出電路的組態之外的電晶體52。電晶體 第一端子係連接至電晶體3 3的閘極電極及電晶體5 二端子。電晶體52之第二端子係連接至電晶體38 電極。電晶體5 2之閘極電極係連接至供應有高的' 初始化 期之間 素部中 係關閉 第19B 描繪之 之第一 第二端 極電極 連接至 示的週 態，電 期tl 第二端 電路中 例。第 中所描 52之 1的第 的閘極 源供S -50- 201220292 As a light source for backlighting, a plurality of light-emitting diodes (LEDs) are preferably used, which can reduce power consumption and adjust the intensity of light when compared with cold cathode fluorescent lamps. The intensity of light is partially adjusted by using LEDs in the backlight so that image display can be performed with high contrast and high color visibility. Further, before and/or after the period in which an image is formed in the pixel portion, a period (non-illumination period) in which the scanning of the selection signal and the illumination of the backlight unit are not performed may be provided. Further, by providing a plurality of image frame periods different from each other in the illumination order of the color of the backlight, the generation of color interruption can be further prevented. <Configuration Example 2 of Pulse Wave Output Circuit> Fig. 19A depicts another example of the configuration of the pulse wave output circuit. The pulse wave output circuit depicted in FIG. 19A includes a transistor 50»the first terminal of the transistor 50 other than the configuration of the pulse wave output circuit depicted in FIG. 8A is connected to the supply of a high power supply. The node of the potential. The second terminal of the transistor 50 is connected to the gate electrode of the transistor 32, the gate electrode ' of the transistor 34, and the gate electrode of the transistor 39. The gate electrode of the transistor 50 is connected to a reset terminal (Reset). The high level potential is input to the reset terminal in the period following the hue switching cycle of the backlight in the pixel portion; the low level potential is input in other periods. The transistor 50 is turned on by the input of a high level potential. Therefore, the potential of each node can be initialized in a period after the backlight is turned on, so that malfunction can be prevented. -51 - 201220292 Note that in the case where initialization is performed, it is necessary to provide a period in which a period in which an image is formed in the pixel portion is provided. Further, in the case where the backlight is turned off after forming an image after the image, the initialization can be performed in the period in which the backlight is present. Fig. 19B depicts another configuration example of the pulse wave output circuit. The pulse wave output circuit depicted in the figure contains a transistor 51 in addition to the configuration of the pulse wave output circuit in Fig. 8A. The transistor 5 1 terminal is connected to the second terminal of the transistor 31 and the transistor 32. The second terminal of the transistor 51 is connected to the gate of the transistor 3 3 and the gate electrode of the transistor 38. The gate electrode of the transistor 51 is supplied with a node having a high power supply potential. Note that the transistor 51 is turned off in the periods 11 to t6 in the Figs. 8B and 8C. Therefore, the gate electrode that passes through the crystal 33 of the transistor 51 and the gate electrode of the transistor 38 can be disconnected from the second terminal of the transistor 31 and the transistor 32 in the case of t6. Therefore, the load at the bootstrap of the pulse wave output can be reduced in the period t1 to t6. Fig. 20A depicts another embodiment of the configuration of the pulse wave output circuit. The pulse wave output circuit depicted in Fig. 20A includes a transistor 52 in addition to the configuration of the pulse wave output circuit depicted in Fig. 19B. The first terminal of the transistor is connected to the gate electrode of the transistor 33 and the two terminals of the transistor 5. The second terminal of transistor 52 is coupled to the transistor 38 electrode. The gate electrode of the transistor 52 is connected to the state in which the first second terminal electrode depicted in the middle portion of the transistor is supplied with a high 'initialization period' is turned off, and the first second terminal electrode is connected to the illustrated state. In the circuit example. The first gate of the first one described in the first paragraph 52

S -52- 201220292 應電位之節點。 電晶體52係如上述地設置，而在脈波輸出電路中之 自舉中的負載可藉以降低。尤其，在其中所連接至電晶體 33的閘極電極之節點的電位係僅藉由電容性耦接電晶體 33之源極電極與閘極電極於脈波輸出電路中而增加的情況 中，可增強負載降低之功效。 第20B圖描繪脈波輸出電路之組態的另一實例。第 2〇B圖中所描繪之脈波輸出電路包含除了第20A圖中所描 繪之脈波輸出電路的組態之外的電晶體5 3，且並不包含電 晶體5 1。電晶體5 3之第一端子係連接至電晶體3 1的第二 端子、電晶體32的第二端子、及電晶體52的第一端子。 電晶體53之第二端子係連接至電晶體33的閘極電極。電. 晶體5 3之閘極電極係連接至供應有高的電源供應電位之 節點。 電晶體53被設置，而在脈波輸出電路中之自舉時的 負載可藉以降低。進一步地，在電晶體33及電晶體38的 切換上之脈波輸出電路中所產生的不規則脈波之不利效應 可予以降低。 如此實施例中所描述地，依據本發明一實施例之液晶 顯示裝置係以此方式而執行彩色影像顯示，亦即，像素部 係畫分成爲複數個區域，且具有不同色相的光係以每一區 域而被順序供應之方式。在每一時間，所供應至鄰接區域 之光的色相可彼此互相不同。從而，可防止不同彩色的個 別影像被分離地而不被合成地感覺，且可防止當顯示移動 -53- 201220292 影像時之可能發生的彩色中斷。 在其中彩色影像顯示係以色相彼此互相不同的複數個 光源而執行的情況中，與結合單一彩色之光源及濾色片的 情況不一樣地，該複數個光源需順序地切換而開啓。進一 步地，切換該等光源的頻率需高於使用單一彩色之光源的 情況中之像框頻率。例如，假定在使用單一彩色之光源的 情況中之像框頻率係60Hz時，則切換該等光源的頻率大 約高三倍，亦即，180Hz於具有紅色、綠色、及藍色之光 源的FS驅動中。因此，驅動器電路亦係依據上述光源之 頻率而操作，此將導致驅動器電路在極高頻率處之操作。 因而，在驅動器電路中的功率消耗易於比在結合單一彩色 之光源及濾色片的情況中之驅動器電路中的功率消耗更高 〇 然而，依據本發明之一實施例，用以保持所施加至液 晶元件之電壓的週期可藉由使用截止狀態電流極低的電晶 體而予以延長。因此，用以顯示靜止影像的驅動頻率可減 低至比用以顯示移動影像的驅動頻率更低之頻率。因而， 可獲得低功率消耗的液晶顯示裝置。 (實施例2) 在實施例2中，將敘述其中面板結構係與實施例1中 的面板結構不同之本發明一實施例的液晶顯示裝置之一實 例。S -52- 201220292 The node of the potential. The transistor 52 is arranged as described above, and the load in the bootstrap in the pulse wave output circuit can be lowered. In particular, in the case where the potential of the node connected to the gate electrode of the transistor 33 is increased only by capacitively coupling the source electrode of the transistor 33 and the gate electrode to the pulse wave output circuit, Enhance the effect of load reduction. Figure 20B depicts another example of the configuration of the pulse wave output circuit. The pulse wave output circuit depicted in Fig. 2B contains a transistor 53 other than the configuration of the pulse wave output circuit depicted in Fig. 20A, and does not include the transistor 51. The first terminal of the transistor 53 is connected to the second terminal of the transistor 31, the second terminal of the transistor 32, and the first terminal of the transistor 52. The second terminal of the transistor 53 is connected to the gate electrode of the transistor 33. The gate electrode of the crystal 53 is connected to a node that supplies a high power supply potential. The transistor 53 is set, and the load at the bootstrap in the pulse wave output circuit can be lowered. Further, the adverse effect of the irregular pulse wave generated in the pulse wave output circuit on the switching of the transistor 33 and the transistor 38 can be reduced. As described in the embodiment, the liquid crystal display device according to an embodiment of the present invention performs color image display in this manner, that is, the pixel portion is divided into a plurality of regions, and the light systems having different hue are each The way a region is supplied sequentially. At each time, the hue of the light supplied to the adjacent region may be different from each other. Thereby, it is possible to prevent individual images of different colors from being separately separated without being synthesized, and to prevent color interruption which may occur when displaying a moving image. In the case where the color image display is performed by a plurality of light sources whose hue is different from each other, unlike the case of combining a single color light source and a color filter, the plurality of light sources are sequentially switched to be turned on. Further, the frequency of switching the light sources is higher than the frame frequency in the case of using a single color light source. For example, assuming that the frame frequency is 60 Hz in the case of using a single color light source, the frequency of switching the light sources is approximately three times higher, i.e., 180 Hz in the FS drive with red, green, and blue light sources. Therefore, the driver circuit is also operated in accordance with the frequency of the above-described light source, which will cause the driver circuit to operate at extremely high frequencies. Thus, the power consumption in the driver circuit is easier to consume than in a driver circuit in the case of a single color source and color filter. However, in accordance with an embodiment of the present invention, The period of the voltage of the liquid crystal element can be extended by using a transistor having an extremely low off-state current. Therefore, the driving frequency for displaying still images can be reduced to a lower frequency than the driving frequency for displaying moving images. Thus, a liquid crystal display device with low power consumption can be obtained. (Embodiment 2) In Embodiment 2, an example of a liquid crystal display device of an embodiment of the present invention in which the panel structure is different from that of Embodiment 1 will be described.

S -54- 201220292 〈面板的結構實例〉 本發明一實施例之面板的特定結構將使用其實例表加 以敘述。 第15A圖描繪液晶顯示裝置的結構實例。第15A圖中 所描繪之液晶顯示裝置包含像素部60，掃描線驅動器電路 6 1，及信號線驅動器電路62。在本發明之一實施例中，像 素部60係畫分成爲複數個區域。具體而言，像素部60係 畫分成爲三個區域（區域601至603)於第15A圖之中。 各個區域包含以矩陣而配置之複數個像素615。 電位係藉由掃描線驅動器電路61所控制之m個掃描 線GL，及電位係藉由信號線驅動器電路62所控制之3 χη 個信號線S L係設置用於像素部6 0。該m個掃描線G L係 依據像素部60之區域的數目而畫分成爲複數個組群。例 如，該m個掃描線GL係畫分成爲三個組群，因爲像素部 60係畫分成爲三個區域於第15A圖之中。在每一組群中 之該等掃描線GL係連接至各自對應區域中之複數個像素 615。特定地，每一掃描線GL係連接至以矩陣而配置於每 —區域中之複數個像素615中之各自對應列中的η個像素 615° 此外，該等信號線SL係依據像素部60之區域的數目 而畫分成爲複數個組群。例如’該3Χη個信號線SL係畫 分成爲三個組群’因爲像素部60係畫分成爲三個區域於 第15Α圖之中。在每一組群中之該等信號線31^係連接至 各自對應區域中之複數個像素615。 -55- 201220292 具體而言，在第15A圖之中’該3xn個信號線SL係 由η個信號線SLa、η個信號線SLb、及η個信號線SLc 所構成。進一步地，在第15A圖之中’該η個信號線SLa 的每一者係連接至以矩陣而配置於區域601中之複數個像 素615中之各自對應行中的該等像素615;該η個信號線 5 Lb的每一者係連接至以矩陣而配置於區域602中之複數 個像素615中之各自對應行中的該等像素615;以及該η 個信號線SLc的每一者係連接至以矩陣而配置於區域603 中之複數個像素615中之各自對應行中的該等像素615。 第15B、15C及15D圖分別係區域601、602、及603 中之該等像素615的電路圖。在該等區域中之像素615的 組態係相同的。具體而言，像素6 1 5包含：電晶體6 1 6， 作用爲開關元件；液晶元件6 1 8，其透射率係依據透過電 晶體6 1 6所供應之影像信號的電位所控制；以及電容器 6 1 7，用以保持液晶元件6 1 8的像素電極與相對電極之間 的電壓。 如第1 5B圖中所示地，在區域601中，信號線SLa、 SLb、及SLc係設置鄰接於像素615。進一步地，在區域 601中的像素615之中，電晶體616的閘極電極係連接至 掃描線GL，其第一端子係連接至信號線SLa，以及其第 二端子係連接至液晶元件618的像素電極。電容器617之 —電極係連接至液晶元件618的像素電極，以及其另一電 極係連接至施加有電位之節點。 如第1 5 C圖中所示地，在區域6 0 2中，信號線S L b及S - 54 - 201220292 <Structure Example of Panel> The specific structure of the panel of an embodiment of the present invention will be described using an example table thereof. Fig. 15A depicts a structural example of a liquid crystal display device. The liquid crystal display device depicted in Fig. 15A includes a pixel portion 60, a scanning line driver circuit 161, and a signal line driver circuit 62. In one embodiment of the invention, the pixel portion 60 is divided into a plurality of regions. Specifically, the pixel portion 60 is divided into three regions (regions 601 to 603) in Fig. 15A. Each region includes a plurality of pixels 615 arranged in a matrix. The potential is set by the m scanning lines GL controlled by the scanning line driver circuit 61, and the potential is set by the 3 χn signal lines SL controlled by the signal line driver circuit 62 for the pixel portion 60. The m scanning lines GL are divided into a plurality of groups according to the number of regions of the pixel portion 60. For example, the m scanning lines GL are divided into three groups because the pixel portion 60 is divided into three regions in the 15A map. The scan lines GL in each group are connected to a plurality of pixels 615 in respective corresponding regions. Specifically, each of the scan lines GL is connected to n pixels 615 in respective ones of the plurality of pixels 615 arranged in a matrix, and the signal lines SL are in accordance with the pixel portion 60. The number of regions is divided into a plurality of groups. For example, 'the 3Χn signal lines SL are divided into three groups' because the pixel portion 60 is divided into three regions in the fifteenth map. The signal lines 31 in each group are connected to a plurality of pixels 615 in respective corresponding regions. -55-201220292 Specifically, in Fig. 15A, the 3xn signal lines SL are composed of n signal lines SLa, n signal lines SLb, and n signal lines SLc. Further, in FIG. 15A, each of the n signal lines SLa is connected to the pixels 615 in respective rows of the plurality of pixels 615 arranged in a matrix 601 in a matrix; Each of the signal lines 5 Lb is connected to the pixels 615 in respective rows of the plurality of pixels 615 arranged in a matrix 602 in a matrix; and each of the n signal lines SLc is connected The pixels 615 in respective ones of the plurality of pixels 615 in the region 603 are arranged in a matrix. Figures 15B, 15C, and 15D are circuit diagrams of the pixels 615 in regions 601, 602, and 603, respectively. The configuration of pixels 615 in these regions is the same. Specifically, the pixel 6 15 includes: the transistor 6 1 6 functions as a switching element; and the transmittance of the liquid crystal element 6 1 8 is controlled according to the potential of the image signal supplied through the transistor 6 16 ; 6 1 7 is used to maintain the voltage between the pixel electrode and the opposite electrode of the liquid crystal element 618. As shown in FIG. 15B, in the region 601, the signal lines SLa, SLb, and SLc are disposed adjacent to the pixel 615. Further, among the pixels 615 in the region 601, the gate electrode of the transistor 616 is connected to the scan line GL, the first terminal thereof is connected to the signal line SLa, and the second terminal thereof is connected to the liquid crystal element 618. Pixel electrode. The electrode of the capacitor 617 is connected to the pixel electrode of the liquid crystal element 618, and the other electrode thereof is connected to the node to which the potential is applied. As shown in Fig. 15C, in the region 602, the signal line S L b and

S -56- 201220292 SLc係設置鄰接於像素615。進一步地，在區域602中的 像素615之中’電晶體616的閘極電極係連接至掃描線 GL ’其第一端子係連接至信號線SLb，以及其第二端子係 連接至液晶元件618的像素電極。電容器617之一電極係 連接至液晶元件618的像素電極，以及其另一電極係連接 至施加有電位之節點。 如第15D圖中所示地，在區域603中，信號線SLc係 設置鄰接於像素615。進一步地，在區域603中的像素 615之中’電晶體616的閘極電極係連接至掃描線GL，其 第一端子係連接至信號線SLc，以及其第二端子係連接至 液晶元件618的像素電極。電容器617之一電極係連接至 液晶元件ό 1 8的像素電極，以及其另—電極係連接至施加 有電位之節點。 電位亦施加至每一像素6 1 5中之液晶元件6 1 8的相對 電極。所施加至相對電極的電位可與施加至電容器617之 另一電極的電位相同。 進一步地，像素6 1 5可視需要地包含諸如電晶體、二 極體、電阻器、電容器、或電感器。 在本發明之一實施例中，作用成爲開關元件之電晶體 6 1 6的通道形成區可包含能隙比的半導體之能隙更寬，且 本徵載子密度比矽半導體之本徵載子密度更低的半導體》 透過包含於通道形成區中之具有上述特徵的該半導體材料 ，可極度地減少電晶體6 1 6的截止狀態電流，且可增加其 耐壓。進一步地，透過使用做爲開關元件之具有上述結構 -57- 201220292 的電晶體616，當與使用包含諸如矽或鍺之普通半導體的 電晶體之情況相較時，可進一步防止液晶元件6 1 8中所累 積之電荷的漏洩。 截止狀態電流極低之電晶體6 1 6 .使其中保持所施加至 液晶元件6 1 8之電壓的週期能增加。因而，例如，在其中 將類似於靜止影像之影像資料彼此互相相同的影像資料寫 入至像素部60以供複數個連續像框週期之用的情況中， 即使當驅動頻率低時，亦可維持影像的顯示，亦即，可降 低一定週期之對於像素部60的影像信號之寫入操作的次 數。例如，使用其中利用高度純化、氧缺陷降低的氧化物 半導體膜做爲主動層之上述電晶體做爲電晶體616，則可 藉以將影像信號的寫入間之時矩延長至1 〇秒或更長，較 佳地3 0秒或更長，更佳地一分鐘或更長。當使影像信號 的寫入間之時矩成爲更長時，則可進一步降低功率消耗。 此外，因爲可將影像信號的電位保持更長的週期，所 以即使當用以保持影像信號之電位的電容器617並不連接 至液晶元件6 1 8時，亦可防止所顯示之影像的品質遭受減 低。因此，可藉由減少電容器617的尺寸或藉由不提供電 容器6 1 7而增加孔徑比，以導致液晶顯示裝置之功率消耗 的降低。 此外，藉由其中影像信號之電位的極性係相對於相對 電極之電位而反相的反相驅動法，可防止所謂燒屏之液晶 的劣化。然而，依據該反相驅動法，所施加至信號線之電 位的改變會在改變影像信號之極性時增加：因此’在作用 -58-The S-56-201220292 SLc system is disposed adjacent to the pixel 615. Further, among the pixels 615 in the region 602, the gate electrode of the transistor 616 is connected to the scan line GL', the first terminal thereof is connected to the signal line SLb, and the second terminal thereof is connected to the liquid crystal element 618. Pixel electrode. One of the electrodes of the capacitor 617 is connected to the pixel electrode of the liquid crystal element 618, and the other electrode thereof is connected to a node to which a potential is applied. As shown in Fig. 15D, in the region 603, the signal line SLc is disposed adjacent to the pixel 615. Further, among the pixels 615 in the region 603, the gate electrode of the transistor 616 is connected to the scan line GL, the first terminal thereof is connected to the signal line SLc, and the second terminal thereof is connected to the liquid crystal element 618. Pixel electrode. One of the electrodes of the capacitor 617 is connected to the pixel electrode of the liquid crystal element ό 18, and the other electrode is connected to the node to which the potential is applied. A potential is also applied to the opposite electrode of the liquid crystal cell 618 in each of the pixels 61. The potential applied to the opposite electrode may be the same as the potential applied to the other electrode of the capacitor 617. Further, pixel 61 may optionally include a transistor, a diode, a resistor, a capacitor, or an inductor, as desired. In an embodiment of the invention, the channel formation region of the transistor 616 functioning as the switching element may comprise a wider energy gap of the semiconductor having an energy gap ratio, and the intrinsic carrier density is greater than the intrinsic carrier of the semiconductor. Lower Density Semiconductor The dielectric material having the above characteristics included in the channel formation region can extremely reduce the off-state current of the transistor 61 and can increase its withstand voltage. Further, by using the transistor 616 having the above-described structure -57-201220292 as a switching element, the liquid crystal element 6 1 8 can be further prevented when compared with the case of using a transistor including a general semiconductor such as germanium or germanium. Leakage of the charge accumulated in the battery. The transistor 6 16 in which the off-state current is extremely low can increase the period in which the voltage applied to the liquid crystal element 6 18 is maintained. Thus, for example, in the case where image data similar to the image data of still images are mutually written to the pixel portion 60 for a plurality of consecutive frame periods, the image can be maintained even when the driving frequency is low. The display, that is, the number of write operations for the image signal of the pixel portion 60 in a certain period can be reduced. For example, by using the above-described transistor in which an oxide semiconductor film having a high degree of purification and reduction in oxygen deficiency is used as an active layer as the transistor 616, the time between writing of the image signal can be extended to 1 sec or more. Long, preferably 30 seconds or longer, more preferably one minute or longer. When the moment between the writing of the video signal is made longer, the power consumption can be further reduced. In addition, since the potential of the image signal can be maintained for a longer period, even when the capacitor 617 for maintaining the potential of the image signal is not connected to the liquid crystal element 618, the quality of the displayed image can be prevented from being degraded. . Therefore, the aperture ratio can be increased by reducing the size of the capacitor 617 or by not providing the capacitor 61 to cause a decrease in power consumption of the liquid crystal display device. Further, by the inversion driving method in which the polarity of the potential of the image signal is inverted with respect to the potential of the counter electrode, deterioration of the so-called burn-in liquid crystal can be prevented. However, according to the inversion driving method, the change in the potential applied to the signal line is increased when the polarity of the image signal is changed: therefore, the effect is -58-

S 201220292 成爲開關元件之電晶體6 1 6的源極電極與汲極電極之間的 電位差會增加。因而，在電晶體616中易於造成諸如臨限 電壓偏移之特徵的劣化。再者，爲了要維持所保持在液晶 元件618中之電壓，即使當源極電極與汲極電極之間的電 位差變大時，亦需使電晶體6 1 6之截止狀態電流減低。在 本發明之一實施例中，係使用諸如氧化物半導體之能隙比 矽或鍺的能隙更寬且本徵載子密度比矽或鍺的本徵載子密 度更低之半導體以供電晶體616之用：因此，可增加電晶 體616的耐壓且可使截止狀態電流成爲相當地低。因而， 當與使用包含諸如矽或鍺之普通半導體材料的電晶體之情 況相較時，可防止電晶體6 1 6的劣化，且可維持所保持於 液晶元件6 1 8中之電壓。 雖然第15B至15D圖描繪其中使用一電晶體616做爲 像素6 1 5中之開關元件的情況，但本發明並未受限於此結 構。複數個電晶體可被使用做爲一開關元件。在其中複數 個電晶體係作用成爲一開關元件的情況中，該複數個電晶 體可彼此互相並聯地、串聯地、並聯及串聯結合地連接。 〈掃描線驅動器電路6 1之組態.實例〉 第16圖描繪包含於第15A圖至15D圖中之液晶顯示 裝置中之掃描線驅動器電路61的組態實例。第1 6圖中所 描繪之掃描線驅動器電路61包含各自包括k個輸出端子 的移位暫存器611至613。移位暫存器611之每一輸出端 子係連接至區域601中所設置之k個掃描線GL的各自對 -59- 201220292 應者：移位暫存器612之每一輸出端子係連接至區域6 02 中所設置之k個掃描線GL的各自對應者；以及移位暫存 器613之每一輸出端子係連接至區域603中所設置之k個 掃描線GL的各自對應者。也就是說，選擇信號係藉由移 位暫存器61 1而掃描於區域601中，選擇信號係藉由移位 暫存器612而掃描於區域6 02中；以及選擇信號係藉由移 位暫存器613而掃描於區域603中。 具體而言，掃描線驅動器電路起動脈波信號（GSP ) 的脈波係輸入至移位暫存器611，該移位暫存器611回應 於此而供應其中脈波係順序移位1/2週期的選擇信號到掃 描線GL1至GLk»回應於掃描線驅動器電路起動脈波信號 (GSP )的脈波之輸入，移位暫存器612供應其中脈波係 順序移位1/2週期的選擇信號到掃描線GLk+Ι至GL2k。 回應於掃描線驅動器電路起動脈波信號（GSP )的脈波， 移位暫存器6 1 3供應其中脈波係順序移位1 /2週期的選擇 信號到掃描線GL2k+l至GL3k。 將使用第17圖來敘述全彩色影像顯週期3〇1及單 色靜止影像顯示週期303中之掃描線驅動器電路61的操 作實例於下文。 第17圖係掃描線驅動器電路時脈信號（GCK)，所 輸入到掃描線GL 1至GLk之選擇信號，所輸入到掃描線 GLk+Ι至GL2k之選擇信號，及所輸入到掃描線GL2k+l 至GL3k之選擇信號的時序圖。 首先，將敘述全彩色影像顯示週期301中之掃描線驅S 201220292 The potential difference between the source electrode and the drain electrode of the transistor 6 16 which becomes the switching element increases. Thus, deterioration of characteristics such as threshold voltage shift is apt to occur in the transistor 616. Further, in order to maintain the voltage held in the liquid crystal element 618, even when the potential difference between the source electrode and the drain electrode becomes large, it is necessary to reduce the off-state current of the transistor 61. In one embodiment of the present invention, a semiconductor such as an oxide semiconductor having a wider energy gap than 矽 or 锗 and having a lower intrinsic carrier density than 本 or 锗 is used to supply a crystal. 616 is used: Therefore, the withstand voltage of the transistor 616 can be increased and the off-state current can be made relatively low. Thus, when compared with the case of using a transistor including a general semiconductor material such as ruthenium or iridium, deterioration of the transistor 616 can be prevented, and the voltage held in the liquid crystal element 618 can be maintained. Although the 15B to 15D drawings depict the case where a transistor 616 is used as the switching element in the pixel 615, the present invention is not limited to this structure. A plurality of transistors can be used as a switching element. In the case where a plurality of electromorphic systems function as a switching element, the plurality of electromorphs may be connected to each other in parallel, in series, in parallel, and in series. <Configuration of Scan Line Driver Circuit 61. Example> Fig. 16 depicts a configuration example of the scan line driver circuit 61 included in the liquid crystal display device of Figs. 15A to 15D. The scan line driver circuit 61 depicted in Fig. 16 includes shift registers 611 to 613 each including k output terminals. Each output terminal of the shift register 611 is connected to a respective pair of k scan lines GL set in the area 601 - 59 - 201220292. Each output terminal of the shift register 612 is connected to the area. Each of the k scan lines GL set in 6 02; and each output terminal of the shift register 613 is connected to a respective counterpart of the k scan lines GL set in the area 603. That is, the selection signal is scanned in the region 601 by the shift register 61 1 , the selection signal is scanned in the region 206 by the shift register 612; and the selection signal is shifted by The register 613 is scanned in the area 603. Specifically, the pulse line system of the arterial wave signal (GSP) of the scan line driver circuit is input to the shift register 611, and the shift register 611 is supplied with the pulse wave system sequentially shifted by 1/2. The selection signal of the period to the scan lines GL1 to GLk» is responsive to the input of the pulse wave of the arterial wave signal (GSP) of the scan line driver circuit, and the shift register 612 supplies the selection in which the pulse wave system is sequentially shifted by 1/2 cycle. The signal is sent to the scan line GLk+Ι to GL2k. In response to the pulse line of the arterial wave signal (GSP) of the scan line driver circuit, the shift register 6 1 3 supplies a selection signal in which the pulse wave system is sequentially shifted by 1 /2 cycles to the scan lines GL2k+1 to GL3k. An example of the operation of the scanning line driver circuit 61 in the full-color image display period 3〇1 and the single-color still image display period 303 will be described using FIG. Figure 17 is a scanning line driver circuit clock signal (GCK), a selection signal input to the scanning lines GL 1 to GLk, a selection signal input to the scanning lines GLk + Ι to GL2k, and input to the scanning line GL2k+ l Timing diagram of the selection signal to GL3k. First, the scanning line drive in the full color image display period 301 will be described.

-60- S 201220292 動器電路61的操作如下。在全彩色影像顯示週期301中 ，第一子像框週期SF1起動以回應於掃描線驅動器電路起 動脈波信號（GSP)的脈波。在第一子像框週期SF1中’ 係供應其中脈波順序移位1 /2週期的選擇信號到掃描線 GL1至GLk ;係供應其中脈波順序移位1/2週期的選擇信 號到掃描線GLk+Ι至GL2k;且係供應其中脈波順序移位 1/2週期的選擇信號到掃描線GL2k+l至GL3k。 然後，第二子像框週期SF2起動以回應於再輸入至掃 描線驅動器電路61之掃描線驅動器電路起動脈波信號（ GSP )的脈波。在該第二子像框週期SF2中，係以與第一 子像框週期SF 1相似的方式而輸入脈波順序移位的選擇信 號到掃描線GL1至GLk ;到掃描線GLk+Ι至GL2k ;以及 到掃描線GL2k+l至GL3k。 然後，第三子像框週期SF3起動以回應於再輸入至掃 描線驅動器電路61之掃描線驅動器電路起動脈波信號（ GSP )的脈波。在該第三子像框週期SF3中，係以與第一 子像框週期SF 1相似的方式而輸入脈波順序移位的選擇信 號到掃描線GL1至GLk ;到掃描線GLk+Ι至GL2k :以及 到掃描線GL2k+l至GL3k。 使第一至第三子像框週期SF1至SF3完結以完成一像 框週期’而影像可藉以顯示於像素部之上。 接著’將敘述單色靜止影像顯示週期303中之掃描線 驅動器電路61的操作如下。在單色靜止影像顯示週期3〇3 201220292 中，與全彩色影像顯示週期301中之該等子像框週期的任 一者之操作相似的操作係執行於掃描線驅動器電路61中 之影像信號寫入週期中。 其次，在保持週期中，停止對於掃描線驅動器電路61 之驅動信號及電源供應電位的供應。具體而言，首先，停 止掃描線驅動器電路起動脈波信號（GSP )的供應，以停 止選擇信號自掃描線驅動器電路61之輸出，藉以終止在 所有掃描線GL中之藉由脈波的選擇，且然後，停止對於 掃描線驅動器電路61之電源供應電位的供應。依據該方 法，可防止在停止掃描線驅動器電路61的操作中之掃描 線驅動器電路61的故障。此外，可停止對於掃描線驅動 器電路61之第一至第四掃描線驅動器電路時脈信號（ GCK1至GCK4 )的供應。 停止對於掃描線驅動器電路6 1之驅動信號及電源供 應電位的供應，因而，將低位準電位供應到掃描線GL1至 GLk;掃描線 GLk+Ι至 GL2k;以及掃描線GL2k+l至 GL3k。 在單色移動影像顯示週期302中，於寫入週期中，掃 描線驅動器電路61的操作係與單色靜止影像顯示週期303 中之操作相似。 在本發明之一實施例中，係使用截止狀態電流極低的 電晶體於像素中，而可藉以增加其中保持所施加至液晶元 件之電壓的週期。因此，在單色靜止影像顯示週期303中 ，可延長第17圖中所示之保持週期，而使將被減低之掃The operation of the -60-S 201220292 actuator circuit 61 is as follows. In the full-color image display period 301, the first sub-frame period SF1 is activated in response to the pulse wave of the arterial wave signal (GSP) of the scan line driver circuit. In the first sub-frame period SF1, a selection signal in which the pulse wave is sequentially shifted by 1 /2 cycles is supplied to the scanning lines GL1 to GLk; a selection signal in which the pulse wave is sequentially shifted by 1/2 cycle is supplied to the scanning line GLk + Ι to GL2k; and a selection signal in which the pulse wave is sequentially shifted by 1/2 period is supplied to the scanning lines GL2k+1 to GL3k. Then, the second sub-frame period SF2 is activated in response to the pulse wave of the arterial wave signal (GSP) re-inputted to the scan line driver circuit of the scan line driver circuit 61. In the second sub-frame period SF2, the pulse-sequentially shifted selection signals are input to the scan lines GL1 to GLk in the same manner as the first sub-frame period SF1; to the scan lines GLk+Ι to GL2k; Go to scan lines GL2k+1 to GL3k. Then, the third sub-frame period SF3 is started in response to the pulse wave of the arterial wave signal (GSP) which is re-inputted to the scanning line driver circuit of the scan line driver circuit 61. In the third sub-frame period SF3, the pulse-sequentially shifted selection signals are input to the scanning lines GL1 to GLk in the same manner as the first sub-frame period SF1; to the scanning lines GLk+Ι to GL2k: Go to scan lines GL2k+1 to GL3k. The first to third sub-frame periods SF1 to SF3 are completed to complete a frame period ' and the image can be displayed above the pixel portion. Next, the operation of the scanning line driver circuit 61 in the monochrome still image display period 303 will be described as follows. In the monochrome still image display period 3〇3 201220292, an operation similar to the operation of any of the sub-frame periods in the full-color image display period 301 is performed by the image signal writing in the scan line driver circuit 61. In the cycle. Next, in the sustain period, the supply of the drive signal and the power supply potential to the scanning line driver circuit 61 is stopped. Specifically, first, the supply of the arterial wave signal (GSP) by the scan line driver circuit is stopped to stop the output of the selection signal from the scan line driver circuit 61, thereby terminating the selection of the pulse wave in all the scan lines GL, And then, the supply of the power supply potential to the scanning line driver circuit 61 is stopped. According to this method, the failure of the scanning line driver circuit 61 in the operation of stopping the scanning line driver circuit 61 can be prevented. Further, the supply of the first to fourth scan line driver circuit clock signals (GCK1 to GCK4) to the scan line driver circuit 61 can be stopped. The supply of the driving signal and the power supply potential to the scanning line driver circuit 61 is stopped, and thus, the low level potential is supplied to the scanning lines GL1 to GLk; the scanning lines GLk+ to GL2k; and the scanning lines GL2k+1 to GL3k. In the monochrome moving image display period 302, the operation of the scan line driver circuit 61 is similar to that in the monochrome still image display period 303 in the write period. In one embodiment of the invention, a transistor having an extremely low off-state current is used in the pixel, thereby increasing the period in which the voltage applied to the liquid crystal cell is maintained. Therefore, in the monochrome still image display period 303, the hold period shown in FIG. 17 can be extended, so that the scan will be reduced.

-62- S 201220292 描線驅動器電路61的驅動頻率能低於全彩色影像顯示週 期301中的驅動頻率。從而，可提供低的功率消耗之液晶 顯示裝置。 〈信號線驅動器電路62之組態實例〉 第18圖描繪第15A圖中所示之信號線驅動器電路62 的組態實例。第1 8圖中所示之信號線驅動器電路62包含 :移位暫存器62 0’具有第一至第η輸出端子；以及開關 元件組群623 ’其控制用於區域601之影像信號（DATA1 )、用於區域602之影像信號（DATA2 )、及用於區域 603之影像信號（DATA3 )對信號線SLa至SLc的供應。 特定地，開關元件組群623包含電晶體65al至65an 、電晶體65bl至65bn、及電晶體65cl至65cn。 電晶體65al至65an的第一端子係連接至用以供應影 像信號（DAT A 1 )之佈線，其第二端子係分別連接至信號 線S Lai至SLan，以及其閘極電極係分別連接至移位暫存 器620之第一至第η輸出端子。 電晶體65b 1至65bn的第一端子係連接至用以供應影 像信號（DATA2 )之佈線，其第二端子係分別連接至信號 線SLbl至SLbn，以及其閘極電極係分別連接至移位暫存 器62 0之第一至第η輸出端子。 電晶體65c 1至65cn的第一端子係連接至用以供應影 像信號（DAT A3 )之佈線，其第二端子係分別連接至信號 線SLcl至SLcn，以及其閘極電極係分別連接至移位暫存 -63- 201220292 器620之第一·至第η輸出端子。 移位暫存器620依據諸如信號線驅動器電路起動脈波 信號（SSP )及信號線驅動器電路時脈信號（SCK )之驅 動信號而操作，且自第一至第η輸出端子而輸出其中脈波 係順序移位之信號。該等信號係輸入至該等電晶體的閘極 電極，而使電晶體65al至65an順序地導通、使電晶體 65bl至65bn順序地導通、且使電晶體65cl至65cn順序 地導通。然後，影像信號（DATA1 )被輸入到信號線 SLal至SLan，影像信號（DATA2 )被輸入到信號線SLbl 至SLbn，以及影像信號（DATA3 )被輸入到信號線SLcl 至SLcn，以致使影像顯示。 在保持週期中，於單色靜止影像顯不週期303中，停 止對於移位暫存器620之信號線驅動器電路起動脈波信號 (SSP )的供應，以及對於信號線驅動器電路62之影像信 號（DATA1 )至（DATA3 )的供應。具體而言，首先，信 號線驅動器電路起動脈波信號（SSP )的供應，以停止信 號線驅動器電路62中之影像信號的取樣’且然後’停止 對於信號線驅動器電路62之影像信號的供應及電源供應 電位的供應。依據該方法，可防止在停止信號線驅動器電 路62的操作中之信號線驅動器電路62的故障。此外’可 停止對於信號線驅動器電路62之信號線驅動器電路時脈 信號（SCK)的供應。 此實施例可與上述實施例之任一者適當地結合。 -64 --62- S 201220292 The drive frequency of the trace driver circuit 61 can be lower than the drive frequency in the full-color image display period 301. Thereby, a liquid crystal display device with low power consumption can be provided. <Configuration Example of Signal Line Driver Circuit 62> Fig. 18 depicts a configuration example of the signal line driver circuit 62 shown in Fig. 15A. The signal line driver circuit 62 shown in FIG. 18 includes: the shift register 62 0' has first to nth output terminals; and the switching element group 623' controls the image signal for the area 601 (DATA1) The image signal (DATA2) for the region 602 and the image signal (DATA3) for the region 603 are supplied to the signal lines SLa to SLc. Specifically, the switching element group 623 includes transistors 65a1 to 65an, transistors 65b1 to 65bn, and transistors 65cl to 65cn. The first terminals of the transistors 65a1 to 65an are connected to the wiring for supplying the image signal (DAT A 1 ), the second terminals are respectively connected to the signal lines S Lai to SLan , and the gate electrodes thereof are respectively connected to the shift The first to nth output terminals of the bit buffer 620. The first terminals of the transistors 65b 1 to 65bn are connected to the wiring for supplying the image signal (DATA2), the second terminals thereof are respectively connected to the signal lines SLb1 to SLbn, and the gate electrodes thereof are respectively connected to the shifting temporary The first to nth output terminals of the register 62 0. The first terminals of the transistors 65c 1 to 65cn are connected to the wiring for supplying the image signal (DAT A3 ), the second terminals thereof are respectively connected to the signal lines SLcl to SLcn, and the gate electrodes thereof are respectively connected to the shift Temporary storage -63- 201220292 620 first to nth output terminal. The shift register 620 operates in accordance with a driving signal such as a signal line driver circuit an arterial wave signal (SSP) and a signal line driver circuit clock signal (SCK), and outputs a pulse wave from the first to the nth output terminals. A signal that is sequentially shifted. The signals are input to the gate electrodes of the transistors, and the transistors 65a1 to 65an are sequentially turned on, the transistors 65b1 to 65bn are sequentially turned on, and the transistors 65cl to 65cn are sequentially turned on. Then, the image signal (DATA1) is input to the signal lines SLal to SLan, the image signal (DATA2) is input to the signal lines SLb1 to SLbn, and the image signal (DATA3) is input to the signal lines SLcl to SLcn to cause the image to be displayed. In the sustain period, in the monochrome still image display period 303, the supply of the arterial wave signal (SSP) to the signal line driver circuit of the shift register 620, and the image signal for the signal line driver circuit 62 are stopped ( DATA1) to (DATA3) supply. Specifically, first, the signal line driver circuit supplies the arterial wave signal (SSP) to stop sampling of the image signal in the signal line driver circuit 62 and then 'stops' the supply of the image signal to the signal line driver circuit 62 and Supply of power supply potential. According to this method, the failure of the signal line driver circuit 62 in the operation of the stop signal line driver circuit 62 can be prevented. Further, the supply of the signal line driver circuit clock signal (SCK) to the signal line driver circuit 62 can be stopped. This embodiment can be combined as appropriate with any of the above embodiments. -64 -

S 201220292 (實施例3) 在實施例3中，將敘述使用氧化物半導 製造方法。 首先，如第2 1A圖中所描繪地，絕緣膜 基板700的絕緣表面上，以及閘極電極702 膜701之上。S 201220292 (Embodiment 3) In Embodiment 3, a method of manufacturing an oxide semiconductor will be described. First, as depicted in Fig. 2A, the insulating film substrate 700 is on the insulating surface, and the gate electrode 702 is over the film 701.

雖然在可使用做爲基板7〇〇而只要其具 可的基板上並無特殊之限制，但相對於稍後 理，該基板至少必須具有足夠的熱阻。例如 熔合法或浮製法所製造之玻璃基板；石英基 ;或其類似物做爲基板700。在其中使用玻 行之熱處理的溫度係高的情況中，較佳地使 或等於73 0°C之玻璃基板。雖然由諸如塑膠 脂所形成的基板具有比上述基板更低的熱阻 可抵抗製造過程期間之處理溫度，則亦可加J 絕緣膜70 1係使用可耐受在稍後製造步 溫度的材料所形成。特定地，使用氧化矽、 氮化砂、氮氧化矽、氮化鋁、氧化鋁、或其 緣膜7〇1之用係較佳的。 在此說明書中，氮氧化物表示其中氧的 量更大之材料，且氧化氮化物表示其中氮的 量更大之材料。 閘極電極702可以以使用一或更多個導 或堆疊層來予以形成，而該一或更多個導電 體之電晶體的 701係形成於 係形成於絕緣 有透光性質即 所執行之熱處 ，可使用藉由 板；陶質基板 璃基板且所執 用應變點高於 之撓性合成樹 溫度，但只要 U使用。 驟中之熱處理 氮化砂、氧化 類似物以供絕 數量比氮的數 數量比氧的數 電膜之單一層 膜可使用諸如 -65- 201220292 鉬、駄、絡、鉬、鎢、銳、或航之金屬材料，或包含該等 金屬材料的任一者做爲主要成分之合金材料，或該等金屬 之氮化物。鋁或銅亦可被使用做爲該金屬材料，只要其可 耐受將於稍後步驟中所執行之熱處理的溫度即可。爲了要 防止熱阻問題及銹鈾問題，較佳地，使鋁或銅與耐火金屬 材料結合。做爲該耐火金屬材料，可使用鉬、鈦、鉻、鉬 、鎢、銨、銃、或其類似物。 例如，做爲閘極電極702之二層結構，以下結構係較 佳的：其中鉬膜係堆疊於鋁膜之上的二層結構，其中組膜 係堆疊於銅膜之上的二層結構，其中氮化鈦膜或氮化鉬膜 係堆疊於銅膜之上的二層結構，以及其中堆疊氮化鈦膜及 鉬膜的二層結構。做爲閘極電極702之三層結構，以下結 構係較佳的：其中使用鋁膜、鋁及矽之合金膜、鋁及鈦之 合金膜、或鋁及銨之合金膜做爲中間層，且插入於選自鎢 膜、氮化鎢膜、氮化鈦膜、或鈦膜之做爲上方層及下方層 的二膜之間的堆疊層結構。 進一步地，可使用氧化銦、氧化銦及氧化錫的合金、 氧化銦及氧化鋅的合金、氧化鋅、氧化鋅鋁、氮氧化辞鋁 、氧化鋅鎵、或其類似物之透光氧化物導電膜做爲閘極電 極 702。 閘極電極702的厚度係在10奈米至400奈米，較佳 地，100奈米至200奈米的範圍中。在此實施例中，用於 閘極電極之具有150奈米厚度的導電膜係藉由使用鎢靶極 之濺鍍法所形成，且係藉由蝕刻而被處理（圖案化）爲所Although there is no particular limitation on the substrate which can be used as the substrate 7 as long as it is possible, the substrate must have at least sufficient thermal resistance with respect to the latter. For example, a glass substrate manufactured by a fusion method or a float method; a quartz base; or the like is used as the substrate 700. In the case where the temperature of the heat treatment using the glass is high, a glass substrate of 73 ° C or higher is preferably used. Although the substrate formed of, for example, a plastic grease has a lower thermal resistance than the above substrate to withstand the processing temperature during the manufacturing process, the J insulating film 70 1 may be used to use a material that can withstand the temperature at a later manufacturing step. form. Specifically, it is preferred to use cerium oxide, cerium nitride, cerium oxynitride, aluminum nitride, aluminum oxide, or a film thereof. In this specification, the oxynitride means a material in which the amount of oxygen is larger, and the oxynitride represents a material in which the amount of nitrogen is larger. The gate electrode 702 may be formed using one or more conductive or stacked layers, and the 701 of the transistor of the one or more electrical conductors is formed by forming a light transmissive property, ie, performing heat Where, the use of a plate; a ceramic substrate glass substrate and the applied strain point is higher than the temperature of the flexible synthetic tree, but only U is used. The heat treatment of the nitriding sand, the oxidized analog is used for a single film of the number of oxygen than the number of nitrogen, and a single film can be used, such as -65-201220292 molybdenum, niobium, tantalum, molybdenum, tungsten, sharp, or A metal material of aeronautical material, or an alloy material containing either of the metal materials as a main component, or a nitride of the metal. Aluminum or copper may also be used as the metal material as long as it can withstand the temperature of the heat treatment to be performed in a later step. In order to prevent thermal resistance problems and rust uranium problems, it is preferred to combine aluminum or copper with a refractory metal material. As the refractory metal material, molybdenum, titanium, chromium, molybdenum, tungsten, ammonium, cerium, or the like can be used. For example, as the two-layer structure of the gate electrode 702, the following structure is preferred: a two-layer structure in which a molybdenum film is stacked on an aluminum film, wherein the film is stacked in a two-layer structure over the copper film, A two-layer structure in which a titanium nitride film or a molybdenum nitride film is stacked on a copper film, and a two-layer structure in which a titanium nitride film and a molybdenum film are stacked. As the three-layer structure of the gate electrode 702, the following structure is preferable: an aluminum film, an alloy film of aluminum and tantalum, an alloy film of aluminum and titanium, or an alloy film of aluminum and ammonium is used as an intermediate layer, and A stacked layer structure interposed between two films selected from the group consisting of a tungsten film, a tungsten nitride film, a titanium nitride film, or a titanium film as an upper layer and a lower layer. Further, an indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, a transparent oxide conductive of zinc oxide, zinc aluminum oxide, aluminum oxynitride, zinc gallium oxide, or the like may be used. The film serves as a gate electrode 702. The thickness of the gate electrode 702 is in the range of 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a conductive film having a thickness of 150 nm for a gate electrode is formed by a sputtering method using a tungsten target, and is processed (patterned) by etching.

-66- S 201220292 欲的形狀，以致使閘極電極702形成。注意的是，所 之閘極電極的末端部分係較佳地成錐形，因爲可改善 閘極絕緣膜堆疊於其上之作用範圍。阻體罩幕可藉由 法而形成。藉由噴墨法之阻體罩幕的形成並不需要光 因而，可降低製造成本。 接著，如第2 1B圖中所描繪地，閘極絕緣膜703 成於閘極電極702之上，且然後，島狀之氧化物半導 704係形成於閘極絕緣膜703之上，以便與閘極電極 重疊。 閘極絕緣膜703可藉由電漿CVD法、濺鍍法、 類似方法而以單層結構或堆疊層結構來予以形成，該 結構或堆疊層結構可包含氧化矽膜、氮化矽膜、氮氧 膜、氧化氮化矽膜、氧化鋁膜、氮化鋁膜、氮氧化鋁 氧化氮化鋁膜、氧化給膜、或氧化鉬膜之任一者。較 ，閘極絕緣膜703盡量多地不包含諸如水分、氫、或 雜質。在藉由濺鍍法而形成氧化矽膜的情況中，係使 靶材或石英靶材做爲靶極，且使用氧或氧和氬的混合 做爲濺鍍氣體。 藉由雜質之去除而高度純化之氧化物半導體係非 敏於介面狀態密度或介面電荷；因此，高度純化之氧 半導體與閘極絕緣膜703之間的介面係重要的。因此 高度純化之氧化物半導體接觸的閘極絕緣膜（GI )需 高的品質。 例如，較佳地使用利用微波（頻率：2.4 5 G Η z ) 形成 具有 噴墨 罩； 係形 體膜 702 或其 單層 化矽 膜、 佳地 氧之 用矽 氣體 常靈 化物 ，與 具有 局 -67- 201220292 密度電漿增強型CVD，而絕緣膜可透過該CVD而形成爲 密質、具有高的耐壓、且爲高品質》此係因爲當高度純化 之氧化物半導體與高品質之閘極絕緣膜密接時，可降低介 面狀態密度，且可使介面性質有利。 不用多說地，可施加諸如濺鍍法或電漿CVD法之任 何其他的膜形成方法，只要可形成高品質的絕緣膜做爲閘 極絕緣膜703即可。同樣地，可使用在沈積後可藉由熱處 理而增進品質及/或與氧化物半導體之介面特徵的絕緣膜 。無論如何，可使用具有降低之介面狀態密度於閘極絕緣 膜與氧化物半導體之間，且可形成有利之介面，以及具有 有利之膜品質的任何絕緣膜，做爲閘極絕緣膜。 閘極絕緣膜7 03可形成爲具有其中堆疊包含具有高障 壁性質之材料的絕緣膜，及諸如氧化矽膜或氮氧化矽膜之 具有低比例之氮的絕緣膜之結構。在該情況中，諸如氧化 矽膜或氮氧化矽膜之絕緣膜係設置於具有高障壁性質的絕 緣膜與氧化物半導體膜之間。做爲具有高障壁性質的絕緣 膜，例如，可給定氮化矽膜、氧化氮化矽膜、氮化鋁膜、 氧化氮化鋁膜、或其類似物。具有高障壁性質之絕緣膜可 防止氛圍中之諸如水分或氫的雜質，或基板中之諸如鹼金 屬或重金屬的雜質進入氧化物半導體膜、閘極絕緣膜703 、或該氧化物半導體膜與另一絕緣膜之間的介面及其附近 處。此外，諸如氧化矽膜或氮氧化矽膜之具有低比例之氮 的絕緣膜係形成以便與氧化物半導體膜接觸，使得可防止 具有高障壁性質之絕緣膜與氧化物半導體膜直接接觸。-66- S 201220292 The desired shape is such that the gate electrode 702 is formed. Note that the end portion of the gate electrode is preferably tapered because the range in which the gate insulating film is stacked is improved. The barrier mask can be formed by the method. The formation of the barrier mask by the ink jet method does not require light, and thus the manufacturing cost can be reduced. Next, as depicted in FIG. 2B, a gate insulating film 703 is formed over the gate electrode 702, and then an island-shaped oxide semiconductor 704 is formed over the gate insulating film 703 so as to be The gate electrodes overlap. The gate insulating film 703 may be formed by a plasma CVD method, a sputtering method, or the like in a single layer structure or a stacked layer structure, and the structure or the stacked layer structure may include a hafnium oxide film, a hafnium nitride film, and a nitrogen layer. Any of an oxygen film, a hafnium oxynitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride aluminum oxide oxide film, an oxidation donor film, or a molybdenum oxide film. In contrast, the gate insulating film 703 does not contain as much moisture as possible, such as moisture, hydrogen, or impurities. In the case where a hafnium oxide film is formed by a sputtering method, a target or a quartz target is used as a target, and oxygen or a mixture of oxygen and argon is used as a sputtering gas. The oxide semiconductor which is highly purified by the removal of impurities is not sensitive to the interface state density or the interface charge; therefore, the interface between the highly purified oxygen semiconductor and the gate insulating film 703 is important. Therefore, a highly purified oxide semiconductor contact gate insulating film (GI) requires high quality. For example, it is preferable to use a microwave (frequency: 2.4 5 G Η z ) to form an ink jet cover; a system film 702 or a single-layered ruthenium film thereof, and a gas turbidity gas for a good oxygen, and have a bureau- 67- 201220292 Density plasma enhanced CVD, and the insulating film can be formed into a dense, high withstand voltage and high quality through the CVD. This is because of the highly purified oxide semiconductor and high quality gate. When the insulating film is in close contact, the interface state density can be lowered, and the interface property can be advantageous. Needless to say, any other film forming method such as a sputtering method or a plasma CVD method may be applied as long as a high-quality insulating film can be formed as the gate insulating film 703. Similarly, an insulating film which can improve the quality and/or interface characteristics with an oxide semiconductor by heat treatment after deposition can be used. In any case, any insulating film having a reduced interface state density between the gate insulating film and the oxide semiconductor, and which can form an advantageous interface, and having an advantageous film quality can be used as the gate insulating film. The gate insulating film 703 may be formed to have a structure in which an insulating film containing a material having a high barrier property, and an insulating film having a low proportion of nitrogen such as a hafnium oxide film or a hafnium oxynitride film are stacked. In this case, an insulating film such as a hafnium oxide film or a hafnium oxynitride film is provided between the insulating film having high barrier properties and the oxide semiconductor film. As the insulating film having high barrier properties, for example, a tantalum nitride film, a hafnium oxynitride film, an aluminum nitride film, an aluminum oxide oxide film, or the like can be given. The insulating film having high barrier properties can prevent impurities such as moisture or hydrogen in the atmosphere, or impurities such as alkali metals or heavy metals in the substrate from entering the oxide semiconductor film, the gate insulating film 703, or the oxide semiconductor film and the other The interface between an insulating film and its vicinity. Further, an insulating film having a low proportion of nitrogen such as a hafnium oxide film or a hafnium oxynitride film is formed so as to be in contact with the oxide semiconductor film, so that the insulating film having high barrier properties can be prevented from being in direct contact with the oxide semiconductor film.

-68- S 201220292 例如，具有大於或等於50奈米且小於或等於200奈 米之厚度的氮化矽膜（SiNy ( y&gt;0 ))係藉由濺鍍法而形 成爲第一閘極絕緣膜，且具有大於或等於5奈米且小於或 等於300奈米之厚度的氧化矽膜（SiOx(X&gt;〇))係堆疊 於第一閘極絕緣膜之上，故爲第二閘極絕緣膜；因而，可 形成1 00奈米厚之閘極絕緣膜做爲閘極絕緣膜703。閘極 絕緣膜703的厚度可根據用於電晶體之所需的特徵而予以 適當地設定，且可爲大約3 5 0奈米至400奈米。 在此實施例中，藉由濺鍍法所形成之具有100奈米之 厚度的氧化矽膜係堆疊於藉由濺渡法所形成之具有50奈 米之厚度的氮化矽膜之上，以致使閘極絕緣膜703形成。 注意的是，閘極絕緣膜703係與將於稍後被形成之氧 化物半導體接觸。包含於氧化物半導體之中的氫會不利地 影響到電晶體的特徵；因此，較佳的是，閘極絕緣膜703 不包含氫、氫氧基、及水分。爲了要使閘極絕緣膜703盡 量多地不包含氫、氫氧基、及水分，較佳的是，吸附在形 .成閘極電極702於其上的基板700上之諸如水分或氫的雜 質應藉由預加熱該基板700於濺鍍設備的預加熱室中來予 以消除及去除，而做爲用於膜形成的預加熱。用於該預加 熱的溫度係高於或等於100 °C且低於或等於400 °c，較佳 地，高於或等於150 °C且低於或等於3 00 °C。做爲用於預 加熱室所設置之抽空單元，低溫泵係較佳的。注意的是， 此預加熱處理可被省略。 島狀氧化物半導體膜可藉由將閘極絕緣膜703上所形 -69 - 201220292 成之氧化物半導體膜處理成爲所欲形狀，而予以形 化物半導體膜的厚度係大於或等於2奈米且小於 2 00奈米，較佳地，大於或等於3奈米且小於或等力 米，更佳地，大於或等於3奈米且小於或等於20 氧化物半導體膜係藉由使用氧化物半導體靶極之濺 形成。此外，氧化物半導體膜可在稀有氣體（例如 氛圍、氧氛圍、或稀有氣體（例如，氬）和氧的混 下，藉由濺鍍法而形成。 在藉由濺鍍法而形成氧化物半導體膜之前，於 緣膜703的表面上之灰塵係較佳地藉由其中引入氬 產生電漿之逆濺鍍法而予以去除。該逆濺鍍法表示 無需施加電壓至靶極側，係使用RF電源以供在氬 施加電壓至基板側之用，以便產生電漿於基板附近 表面之方法。取代氬氛圍，可使用氮氛圍、氦氛圍 類似氛圍。同樣地，可使用添加氧、氧化亞氮、或 物之氬氛圍。選擇性地，可使用添加氯、四氟化碳 類似物之氬氛圍。 如上述，可使用以下以供氧化物半導體膜之用 銦；氧化錫；氧化鋅：諸如In-Zn爲主氧化物半導骨 Ζιι爲主氧化物半導體，Al-Zn爲主氧化物半導體， 爲主氧化物半導體，Sn-Mg爲主氧化物半導體，In· 主氧化物半導體，或In-Ga爲主氧化物半導體之二 氧化物；諸如In-Ga-Zn爲主氧化物半導體（亦稱爲 )，In-Al-Zn爲主氧化物半導體，In-Sn-Zn爲主氧 -70- 成。氧 或等於 令50奈 奈米。 鍍法而 ，魏） 合氛圍 閘極絕 氣體且 其中， 氛圍中 而修正 、或其 其類似 、或其 :氧化 I，Sn-Zn-Mg -Mg爲 元金屬 ,IGZO 化物半-68- S 201220292 For example, a tantalum nitride film (SiNy ( y &gt; 0 )) having a thickness greater than or equal to 50 nm and less than or equal to 200 nm is formed as a first gate insulating by sputtering. a film, and a yttrium oxide film (SiOx (X>)) having a thickness of greater than or equal to 5 nm and less than or equal to 300 nm is stacked on the first gate insulating film, so that the second gate is insulated A film; thus, a gate insulating film of 100 nm thick can be formed as the gate insulating film 703. The thickness of the gate insulating film 703 can be appropriately set depending on the desired characteristics for the transistor, and may be about 350 to 400 nm. In this embodiment, the yttrium oxide film having a thickness of 100 nm formed by sputtering is stacked on the tantalum nitride film having a thickness of 50 nm formed by a sputtering method, so that The gate insulating film 703 is formed. Note that the gate insulating film 703 is in contact with an oxide semiconductor which will be formed later. The hydrogen contained in the oxide semiconductor adversely affects the characteristics of the transistor; therefore, it is preferable that the gate insulating film 703 does not contain hydrogen, a hydroxyl group, and moisture. In order to prevent the gate insulating film 703 from containing as much hydrogen, hydroxyl, and moisture as possible, it is preferable to adsorb impurities such as moisture or hydrogen on the substrate 700 on which the gate electrode 702 is formed. The substrate 700 should be removed and removed by preheating the substrate 700 in a preheating chamber of the sputtering apparatus as preheating for film formation. The temperature for the preheating is higher than or equal to 100 ° C and lower than or equal to 400 ° C, preferably higher than or equal to 150 ° C and lower than or equal to 300 ° C. As the evacuation unit provided for the preheating chamber, a cryopump is preferred. Note that this preheating process can be omitted. The island-shaped oxide semiconductor film can be processed into a desired shape by forming an oxide semiconductor film formed on the gate insulating film 703, and the thickness of the formed semiconductor film is greater than or equal to 2 nm. Less than 200 nm, preferably, greater than or equal to 3 nm and less than or equal to the force meter, more preferably, greater than or equal to 3 nm and less than or equal to 20. The oxide semiconductor film is used by using an oxide semiconductor target. Extremely splashing. Further, the oxide semiconductor film can be formed by sputtering under a rare gas (for example, an atmosphere, an oxygen atmosphere, or a mixture of a rare gas (for example, argon) and oxygen. An oxide semiconductor is formed by sputtering. Prior to the film, the dust on the surface of the edge film 703 is preferably removed by reverse sputtering in which argon is introduced into the plasma. This reverse sputtering means that no voltage is applied to the target side, and RF is used. The power source is used for applying a voltage to the substrate side in argon to generate a plasma on the surface near the substrate. Instead of the argon atmosphere, a nitrogen atmosphere or a helium atmosphere may be used. Similarly, oxygen, nitrous oxide, or the like may be used. Alternatively, an argon atmosphere in which chlorine or a carbon tetrafluoride analog is added may be used. As described above, the following may be used for the oxide semiconductor film; indium tin oxide; zinc oxide: such as In- Zn is the main oxide semi-conductive Ζ ι ι lm main oxide semiconductor, Al-Zn is the main oxide semiconductor, the main oxide semiconductor, Sn-Mg is the main oxide semiconductor, In · main oxide semiconductor, or In-Ga for a dioxide of an oxide semiconductor; such as In-Ga-Zn as a main oxide semiconductor (also referred to as), In-Al-Zn as a main oxide semiconductor, and In-Sn-Zn as a main oxygen-70-. Or equal to 50 nanometers. Plating method, Wei) The atmosphere is extremely gas-tight and therein, corrected in the atmosphere, or its similar, or its: oxidation I, Sn-Zn-Mg-Mg is a metametal, IGZO Compound half

S 201220292 導體，Sn-Ga-Zn爲主氧化物半導體，Al-Ga-Zn爲主氧化 物半導體，Sn-Al-Zn爲主氧化物半導體，In-Hf-Zn爲主氧 化物半導體，In-La-Zn爲主氧化物半導體，In-Ce-Zn爲主 氧化物半導體，In-Pr-Zn爲主氧化物半導體，In-Nd-Zn爲 主氧化物半導體，In-Sm-Zn爲主氧化物半導體，In-Eu-Zn 爲主氧化物半導體，In-Gd-Zn爲主氧化物半導體，In-Tb-Zn爲主氧化物半導體，In-Dy-Zn爲主氧化物半導體，In-Ho-Zn爲主氧化物半導體，In-Er-Zn爲主氧化物半導體， In-Tm-Zn爲主氧化物半導體，In-Yb-Zn爲主氧化物半導 體，或In-Lu-Zn爲主氧化物半導體之三元金屬氧化物； 諸如In-Sn-Ga-Zn爲主氧化物半導體，In-Hf-Ga-Zn爲主 氧化物半導體，In-Al-Ga-Zn爲主氧化物半導體，ln_Sn· Al-Zn爲主氧化物半導體，In-Sn-Hf-Zn爲主氧化物半導體 ，或In-Hf-Al-Zn爲主氧化物半導體之四元金屬氧化物。 該氧化物半導體較佳地包含銦（In)，且進一步較佳 地包含In及鎵（Ga)。爲了要獲得I型（本徵）氧化物 半導體膜，對於該氧化物半導體膜之脫水或脫氫且藉由氧 之施與而降低氧缺乏（將於稍後敘述）係有效的》 在此實施例中，做爲氧化物半導體膜，係使用具有30 奈米之厚度的In-Ga-Ζη-Ο爲主氧化物半導體膜，其係藉 由使用包含銦（In)、鎵（Ga)、及鋅（Zn)之靶極的濺 ' 鑛法所獲得。做爲該靶極，例如可使用In2〇3 : Ga203 :S 201220292 Conductor, Sn-Ga-Zn main oxide semiconductor, Al-Ga-Zn main oxide semiconductor, Sn-Al-Zn main oxide semiconductor, In-Hf-Zn main oxide semiconductor, In- La-Zn main oxide semiconductor, In-Ce-Zn main oxide semiconductor, In-Pr-Zn main oxide semiconductor, In-Nd-Zn main oxide semiconductor, In-Sm-Zn main oxidation Semiconductor, In-Eu-Zn main oxide semiconductor, In-Gd-Zn main oxide semiconductor, In-Tb-Zn main oxide semiconductor, In-Dy-Zn main oxide semiconductor, In-Ho -Zn main oxide semiconductor, In-Er-Zn main oxide semiconductor, In-Tm-Zn main oxide semiconductor, In-Yb-Zn main oxide semiconductor, or In-Lu-Zn main oxidation a ternary metal oxide of a semiconductor; an In-Sn-Ga-Zn main oxide semiconductor, an In-Hf-Ga-Zn main oxide semiconductor, an In-Al-Ga-Zn main oxide semiconductor, ln_Sn Al-Zn is a main oxide semiconductor, In-Sn-Hf-Zn is a main oxide semiconductor, or In-Hf-Al-Zn is a quaternary metal oxide of a main oxide semiconductor. The oxide semiconductor preferably contains indium (In), and further preferably contains In and gallium (Ga). In order to obtain a type I (intrinsic) oxide semiconductor film, dehydration or dehydrogenation of the oxide semiconductor film and reduction of oxygen deficiency (to be described later) by application of oxygen are effective here. In the example, as the oxide semiconductor film, an In-Ga-Ζη-Ο main oxide semiconductor film having a thickness of 30 nm is used, which is composed of indium (In), gallium (Ga), and The splash of the target of zinc (Zn) is obtained by the mineral method. As the target, for example, In2〇3 : Ga203 can be used:

ZnO = l : 1 : 1 (克分子比）、ln203: Ga203: ZnO=l : 1 : 2 (克分子比）、或 ln203 : Ga203 : ZnO=l : 1 : 4 (克分 -71 - 201220292 子比）之靶極。包含In、Ga、及Zn之靶極的塡充因子係 高於或等於90%且低於或等於1〇〇%，較佳地，高於或等 於95%且低於100%。當靶極的塡充因子愈高時，則氧化 物半導體膜係更加密質。 當使用Iii-Ζη-Ο爲主材料做爲氧化物半導體時，係使 用具有以In : Zn = 50 : 1至1 : 2之原子比（以Ιη203 : ZnO = 25 : 1至1 : 4之克分子比），較佳地，以In : Zn = 20 :1至1 : 1之原子比（以ln203 : ZnO=10 : 1至2 : 1之 克分子比），或更佳地，以In : Zn=1.5 : 1至15 : 1之原 子比（以ln203 : ZnO = 3 : 4至15 : 2之克分子比）的組成 比之靶極。例如，在用於具有In : Zn : 0 = X : Y : Z之原 子比的In-Zn-O爲主氧化物半導體之形成所使用的靶極中 ，ZM.5X + Y係符合要求的。Zn的比例可設定於上述範圍 內，使用遷移率可予以增進。 在此實施例中，氧化物半導體膜係以此方式而形成於 基板7 00上，亦即，將基板保持在維持於降低壓力的處理 室中；當去除處理室中之殘留水分時之同時，將已去除氫 及水分的濺鍍氣體引入至其中；以及使用上述靶極之方式 。在膜形成中，可將基板溫度設定爲高於或等於1〇〇 °C且 低於或等於600°C，較佳地，高於或等於200°C且低於或 等於400°C。藉由形成氧化物半導體膜於其中使基板加熱 的狀態中，可降低所形成之氧化物半導體膜中所包含之雜 質的濃度。此外，可降低由於濺鍍之損壞。爲了要去除處 理室中之殘留水分，較佳地使用捕集真空泵。例如，較佳 -72-ZnO = l : 1 : 1 (molar ratio), ln203: Ga203: ZnO=l : 1 : 2 (molar ratio), or ln203 : Ga203 : ZnO=l : 1 : 4 (g -71 - 201220292 The target of the ratio). The enthalpy factor of the target comprising In, Ga, and Zn is greater than or equal to 90% and less than or equal to 1%, preferably greater than or equal to 95% and less than 100%. When the target's charge factor is higher, the oxide semiconductor film is more cryptographic. When Iii-Ζη-Ο is used as the oxide semiconductor, the atomic ratio of In : Zn = 50 : 1 to 1: 2 is used (with Ι 203 : ZnO = 25 : 1 to 1: 4 g) Molecular ratio), preferably, an atomic ratio of In : Zn = 20:1 to 1:1 (in a molar ratio of ln203 : ZnO = 10:1 to 2:1), or more preferably, In: Zn = 1.5: 1 to 15: 1 atomic ratio (in the molar ratio of ln203: ZnO = 3: 4 to 15: 2) composition ratio of the target. For example, in a target used for formation of an In-Zn-O main oxide semiconductor having an atom ratio of In : Zn : 0 = X : Y : Z, ZM.5X + Y is satisfactory. The ratio of Zn can be set within the above range, and the mobility can be improved. In this embodiment, the oxide semiconductor film is formed on the substrate 00 in this manner, that is, the substrate is held in the processing chamber maintained under the reduced pressure; while the residual moisture in the processing chamber is removed, A sputtering gas from which hydrogen and moisture have been removed is introduced therein; and a manner of using the above-described target. In film formation, the substrate temperature may be set to be higher than or equal to 1 ° C and lower than or equal to 600 ° C, preferably higher than or equal to 200 ° C and lower than or equal to 400 ° C. In the state in which the oxide semiconductor film is formed to heat the substrate therein, the concentration of the impurities contained in the formed oxide semiconductor film can be lowered. In addition, damage due to sputtering can be reduced. In order to remove residual moisture in the treatment chamber, a trap vacuum pump is preferably used. For example, preferably -72-

S 201220292 地使用低溫泵、離子泵、或鈦昇華泵。抽空單元可爲設置 有冷凝管之渦輪泵。在透過低溫泵而抽空的處理室中，例 如，可去除氫原子、諸如水（H2o )之包含氫原子的化合 物（更佳地，亦係包含碳原子的化合物）、及其類似物， 而在處理室中所形成之氧化物半導體膜中所包含的雜質之 濃度可藉以降低。 做爲沈積情形之一實例，基板與靶極間之距離係1 〇〇 毫米，壓力係0.6帕（Pa)，直流（DC)功率係0.5千瓦 ，以及氛圍係氧氛圍（氧流動率之比例係1 〇〇% )。使用 脈波式直流（DC)電源係較佳的，因爲可降低沈積中所產 生之灰塵，且可使膜厚度成爲均句。 爲了要使氧化物半導體膜盡量多地不包含氫、氫氧基 、及水分，較佳的是，吸附在形成直至包含閘極絕緣膜 7 03之元件於其上的基板700上之諸如水分或氫的雜質應 藉由預加熱該基板700於濺鍍設備的預加熱室中來予以消 除及去除，而做爲用於膜形成的預加熱。用於預加熱之溫 度係高於或等於100 °C且低於或等於400 °C，較佳地，高 於或等於150 °C且低於或等於300 °C。做爲抽空單元，低 溫泵係較佳地設置用於預加熱室。此預加熱可被省略。在 絕緣膜7〇7的形成之前，此預加熱可予以相似地執行在形 成直至包含導電膜705及導電膜706之元件於其上的基板 700之上。 注意的是，用以形成島狀氧化物半導體膜704之蝕刻 可係濕蝕刻、乾蝕刻、或乾蝕刻及濕蝕刻二者。做爲用於 -73- 201220292 乾蝕刻之蝕刻氣體，較佳地使用包含氯之氣體（例如，諸 如氯氣（Cl2 )、三氯化硼（BC13 )、四氯化矽（SiCl4 ) 、或四氯化碳（CC14)之氯爲主氣體。選擇性地，可使用 包含氟之氣體（例如，諸如四氟化碳（cf4 )、六氟化硫 (sf6 )、三氟化氮（nf3 )、或三氟甲烷（chf3 )之氟爲 主氣體）；溴化氫（HBr ):氧氣（02 ):添加諸如氦（ He)或氬（Ar)之稀有氣體的該等氣體之任一者；或其類 似物。 做爲乾蝕刻法，可使用平行板RIE (反應性離子蝕刻 法）或ICP (電感耦合電漿）蝕刻法。爲了要蝕刻膜成爲 所欲之形狀，可適當調整蝕刻情形（所施加至螺旋形電極 之電功率的數量，所施加至基板側電極之電功率的數量， 基板側之電極的溫度，或其類似者）》 做爲使用於濕蝕刻之蝕刻劑，可使用ITO-07N (由 ΚΑΝΤΟ CHEMICAL CO., INC.所生產）。 用以形成島狀氧化物半導體膜704之阻體罩幕可藉由 噴墨法而形成。藉由噴墨法之阻體罩幕的形成並不需要光 罩；因而，可降低製造成本。 較佳的是，逆濺鍍法應在下一步驟中之導電膜的形成 之前被執行，使得留在島狀氧化物半導體膜7〇4及閘極絕 緣膜703的表面上之阻體殘留物或其類似物可予以去除。 注意的是，在某些情況中，藉由濺鍍法或其類似方法 所形成之氧化物半導體膜包含大量的水分或氫（包含氫氧 基）做爲雜質。水分或氫易於形成施體位準，且因此，用 •74-S 201220292 Use a cryopump, ion pump, or titanium sublimation pump. The evacuation unit can be a turbo pump provided with a condensing tube. In a treatment chamber evacuated by a cryopump, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H2o) (more preferably, a compound containing a carbon atom), and the like can be removed, and The concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be lowered. As an example of the deposition case, the distance between the substrate and the target is 1 mm, the pressure is 0.6 Pa (Pa), the DC power is 0.5 kW, and the atmosphere oxygen atmosphere (the ratio of oxygen flow rate is 1 〇〇%). The use of a pulse-wave direct current (DC) power source is preferred because the dust generated during deposition can be reduced and the film thickness can be made uniform. In order that the oxide semiconductor film does not contain hydrogen, a hydroxyl group, and moisture as much as possible, it is preferably adsorbed on the substrate 700 on which the element including the gate insulating film 703 is formed, such as moisture or Hydrogen impurities should be removed and removed by preheating the substrate 700 in a preheating chamber of the sputtering apparatus as preheating for film formation. The temperature for preheating is higher than or equal to 100 ° C and lower than or equal to 400 ° C, preferably higher than or equal to 150 ° C and lower than or equal to 300 ° C. As the evacuation unit, a low temperature pump is preferably provided for the preheating chamber. This preheating can be omitted. This preheating can be similarly performed on the substrate 700 on which the elements including the conductive film 705 and the conductive film 706 are formed before the formation of the insulating film 7?7. Note that the etching for forming the island-shaped oxide semiconductor film 704 may be wet etching, dry etching, or both dry etching and wet etching. As the etching gas for dry etching of -73-201220292, it is preferable to use a gas containing chlorine (for example, such as chlorine (Cl2), boron trichloride (BC13), ruthenium tetrachloride (SiCl4), or tetrachloride. The carbon of carbon (CC14) is a main gas. Alternatively, a gas containing fluorine (for example, carbon tetrafluoride (cf4), sulfur hexafluoride (sf6), nitrogen trifluoride (nf3), or a fluorine of trifluoromethane (chf3) as a main gas); hydrogen bromide (HBr): oxygen (02): any one of such gases added with a rare gas such as helium (He) or argon (Ar); As the dry etching method, a parallel plate RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma) etching method can be used. In order to etch the film into a desired shape, the etching condition can be appropriately adjusted (applied) The amount of electric power to the spiral electrode, the amount of electric power applied to the substrate side electrode, the temperature of the electrode on the substrate side, or the like)" As an etchant for wet etching, ITO-07N can be used (by ΚΑΝΤΟ Produced by CHEMICAL CO., INC.) to form island oxidation The resistive mask of the semiconductor film 704 can be formed by an inkjet method. The formation of the barrier mask by the inkjet method does not require a mask; therefore, the manufacturing cost can be reduced. Preferably, the reverse sputtering The method should be performed before the formation of the conductive film in the next step, so that the residue of the resist remaining on the surface of the island-shaped oxide semiconductor film 7〇4 and the gate insulating film 703 or the like can be removed. In some cases, the oxide semiconductor film formed by sputtering or the like contains a large amount of moisture or hydrogen (including a hydroxyl group) as an impurity. Water or hydrogen is liable to form a donor level. And therefore, with •74-

S 201220292 作氧化物半導體中之雜質。在本發明之一實施例中，爲了 要降低氧化物半導體膜中之諸如水分或氫的雜質（脫水或 脫氫）。島狀氧化物半導體膜704係接受熱處理於降低壓 力之氛圍，氮氣、稀有氣體、或其類似物之惰性氣體氛圍 ，氧氣體氛圍，超乾燥空氣氛圍（在其中測量係藉由露點 計而以光腔衰盪光譜（CRDS )法而執行的情況中，水分 數量係20ppm (藉由轉換成爲露點之-55 t )或更少，較 佳地，lppm或更少，進一步較佳地，lOppb或更少）中。 藉由執行熱處理於島狀氧化物半導體膜704之上，可 消除島狀氧化物半導體膜704中之水分或氫。特定地，熱 處理可執行於高於或等於250 °C且低於或等於75 0t，較 佳地，高於或等於400°C且低於基板之應變點的溫度。例 如，熱處理可執行5 00 °C，約略長於或等於3分鐘且短於 或等於6分鐘之週期。當使用RTA法於熱處理時，可以 以短時間來執行脫水或脫氫；因此，甚至可將處理執行於 比玻璃基板之應變點更高的溫度處。 在此實施例中，係使用電爐，其係熱處理設備的其中 一者。 熱處理設備並未受限於電爐，且可包含用以藉由來自 諸如電阻加熱元件之加熱元件的熱傳導或熱幅射而加熱物 體的裝置。例如，可使用諸如GRTA (氣體快速熱退火） 設備或LRTA (燈快速熱退火）設備之RTA (快速熱退火 )設備。LRT A設備係用以藉由來自諸如鹵素燈、金屬鹵 化物燈、氙弧燈、碳弧燈、高壓鈉燈、或高壓水銀燈之燈 -75- 201220292 備 設 的 體 物 熱 加 而 波 磁 5 獨 Γν 射 輻 之 光 的 出 射 發 所 GRTA設備係使用尚溫氣體之熱處理的設備。做爲該氣體 ，係使用例如氮或諸如氬的稀有氣體之不會與藉由熱處理 所處理的物體反應之惰性氣體。 注意的是，較佳地，在該熱處理中，水分、氫、或其 類似物不包含於氮或諸如氦、氖、或氬之稀有氣體中。較 佳的是，所引入至熱處理設備之內的氮或諸如氦、氖或氬 之稀有氣體的純度應被設定爲6N( 99.9999% )或更高， 更佳地爲 7N ( 99.99999% )或更高（亦即，雜質濃度係 lppm或更低，較佳地係O.lppm或更低）。 透過上述之處理，可降低島狀氧化物半導體膜704中 之氫的濃度，且可使氧化物半導體膜7 04高度純化。因此 ，可使氧化物半導體膜安定化。此外，在低於或等於玻璃 躍遷溫度之溫度的熱處理可由於氫而形成具有寬的能隙及 低的載子密度之氧化物半導體膜。因此，可使用大的基板 而製造出電晶體，以致可增加生產率。上述之熱處理可在 形成氧化物半導體膜之後被執行於任何時間。 在其中將氧化物半導體膜加熱的情況中，雖然係根據 氧化物半導體膜之材料或加熱情形，但在某些情況中會形 成板狀晶體於氧化物半導體膜的表面中。較佳地，該板狀 晶體係單晶，而c軸配向於實質垂直於氧化物半導體膜之 表面的方向中。即使當該等似板狀的晶體並非單晶本體之 形式時，各自晶體亦較佳地爲多晶本體，而c軸配向於實 質垂直於氧化物半導體膜之表面的方向中。在上述之多晶S 201220292 Impurity in oxide semiconductors. In an embodiment of the invention, in order to reduce impurities (dehydration or dehydrogenation) such as moisture or hydrogen in the oxide semiconductor film. The island-shaped oxide semiconductor film 704 is subjected to heat treatment in a pressure-reducing atmosphere, an inert gas atmosphere of nitrogen gas, a rare gas, or the like, an oxygen gas atmosphere, and an ultra-dry air atmosphere (in which the light is measured by a dew point meter) In the case of the cavity ring-down spectroscopy (CRDS) method, the amount of moisture is 20 ppm (by conversion to -55 t of dew point) or less, preferably, 1 ppm or less, further preferably, 10 ppb or more. Less). By performing heat treatment on the island-shaped oxide semiconductor film 704, moisture or hydrogen in the island-shaped oxide semiconductor film 704 can be eliminated. Specifically, the heat treatment may be performed at a temperature higher than or equal to 250 ° C and lower than or equal to 75 °, preferably higher than or equal to 400 ° C and lower than the strain point of the substrate. For example, the heat treatment may be performed at 500 ° C, approximately longer than or equal to 3 minutes and shorter than or equal to 6 minutes. When the RTA method is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time; therefore, the treatment can be performed even at a temperature higher than the strain point of the glass substrate. In this embodiment, an electric furnace is used which is one of the heat treatment apparatuses. The heat treatment apparatus is not limited to an electric furnace and may include means for heating the object by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Annealing) device such as a GRTA (Gas Rapid Thermal Annealing) device or an LRTA (Light Rapid Thermal Annealing) device can be used. LRT A equipment is used to heat the body by means of a heat source from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp - 75 - 201220292 Γ ν The light emitted by the GRTA equipment is a heat treatment equipment using a temperature gas. As the gas, an inert gas such as nitrogen or a rare gas such as argon which does not react with an object to be treated by heat treatment is used. Note that, preferably, in the heat treatment, moisture, hydrogen, or the like is not contained in nitrogen or a rare gas such as helium, neon or argon. Preferably, the purity of nitrogen or a rare gas such as helium, neon or argon introduced into the heat treatment apparatus should be set to 6N (99.9999%) or higher, more preferably 7N (99.999999%) or more. High (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). By the above treatment, the concentration of hydrogen in the island-shaped oxide semiconductor film 704 can be lowered, and the oxide semiconductor film 704 can be highly purified. Therefore, the oxide semiconductor film can be stabilized. Further, the heat treatment at a temperature lower than or equal to the glass transition temperature can form an oxide semiconductor film having a wide energy gap and a low carrier density due to hydrogen. Therefore, a large substrate can be used to manufacture a transistor, so that productivity can be increased. The above heat treatment can be performed at any time after the formation of the oxide semiconductor film. In the case where the oxide semiconductor film is heated, although it is based on the material of the oxide semiconductor film or the heating, in some cases, a plate crystal is formed in the surface of the oxide semiconductor film. Preferably, the plate crystal system is single crystal, and the c-axis is aligned in a direction substantially perpendicular to the surface of the oxide semiconductor film. Even when the plate-like crystals are not in the form of a single crystal body, the respective crystals are preferably polycrystalline bodies, and the c-axis is aligned in a direction perpendicular to the surface of the oxide semiconductor film. Polycrystalline in the above

S -76- 201220292 本體中，除了係C軸配向之外，該等晶體較佳地具有相同 的a-b面、a軸、或b軸》注意的是，當與氧化物半導體 膜接觸之閘極絕緣膜703的表面並非平坦時，則該板狀晶 體係多晶。因此，該閘極絕緣膜703的表面係較佳地盡量 平坦。 接著，如第2 1 C圖中所描繪地，形成作用成爲源極電 極及汲極電極的導電膜705及導電膜706，且形成絕緣膜 707於導電膜705、導電膜706、及島狀氧化物半導體膜 704之上。 導電膜705及導電膜706可以以下方式而形成：導電 膜係藉由濺鍍法或真空蒸鍍法而形成，以便覆蓋島狀氧化 物半導體膜704，且然後，藉由蝕刻法或其類似方式而予 以圖案化》 導電膜705及導電膜706係與島狀氧化物半導體膜 7〇4接觸。做爲用以形成導電膜705及導電膜706之導電 膜的材料，可使用以下材料之任一者：選自鋁、鉻、銅、 ® '鉬、或鎢之元素；包含該等元素之任一者的合金 ;@1上述元素組合之合金膜；或其類似物。可使用其中 '钽、鈦、鉬、或鎢之耐火金屬的膜係堆疊於鋁或 胃&amp; @ _膜的上面或下面的結構。較佳地，鋁或銅係與耐 X € 料結合，以便避免熱阻問題及銹蝕問題。做爲耐 火金屬材料，可使用鉬、鈦、鉻、鉬、鎢、钕、銃、釔、 或其類似物。 步地，導電膜可具有單層結構或二或更多層之堆 -77- 201220292 疊層結構。例如，可給定包含矽之鋁膜的單層結構；其中 鈦膜係堆疊於鋁膜之上的二層結構；其中鈦膜、鋁膜、及 鈦膜係以此順序而堆疊的三層結構；及其類似物。 針對導電膜705及導電膜706中所包含之導電膜，可 使用導電性金屬氧化物。做爲該導電性金屬氧化物，可使 用氧化銦、氧化錫、氧化鋅、氧化銦和氧化錫的合金、氧 化銦和氧化鋅的合金、或包含矽或氧化矽的金屬氧化物材 料。 在其中熱處理係執行於形成導電膜之後的情況中，較 佳地，該導電膜具有足以耐受該熱處理的熱阻。 注意的是，應適當調整材料及蝕刻情形，以致使島狀 氧化物半導體膜704盡量在導電膜的蝕刻中不被去除。根 據蝕刻情形，存在有其中島狀氧化物半導體膜704的暴露 部分被部分地蝕刻，且因而，形成刻槽（凹陷部分）之一 些情況。 在此實施例中，係使用鈦膜於導電膜。因此，可使用 包含氨及雙氧水之溶液（氫氧化銨混合液）而選擇性地執 行濕蝕刻於導電膜之上。特定地，可使用其中以5:2:2 之體積比而混合31重量百分比之雙氧水、28重量百分比 之氫氧化氨、及純水之水溶液。選擇性地，可使用包含氯 氣（Cl2 )、氯化硼（BC13 )、或其類似物之氣體，而執 行乾蝕刻於導電膜之上。 爲了要降低光微影術步驟中之光罩及步驟的數目，可 使用利用可透射光之多色調罩幕所形成的阻體罩幕而執行 -78-S-76-201220292 In the body, except for the C-axis alignment, the crystals preferably have the same ab plane, a-axis, or b-axis. Note that when the gate is in contact with the oxide semiconductor film, the gate is insulated. When the surface of the film 703 is not flat, the plate crystal system is polycrystalline. Therefore, the surface of the gate insulating film 703 is preferably as flat as possible. Next, as described in FIG. 2C, the conductive film 705 and the conductive film 706 functioning as the source electrode and the drain electrode are formed, and the insulating film 707 is formed on the conductive film 705, the conductive film 706, and the island oxidized. Above the semiconductor film 704. The conductive film 705 and the conductive film 706 may be formed in such a manner that the conductive film is formed by sputtering or vacuum evaporation to cover the island-shaped oxide semiconductor film 704, and then, by etching or the like The patterned conductive film 705 and the conductive film 706 are in contact with the island-shaped oxide semiconductor film 7A4. As the material for forming the conductive film of the conductive film 705 and the conductive film 706, any of the following materials may be used: an element selected from aluminum, chromium, copper, ® 'molybdenum, or tungsten; Alloy of one; @1 alloy film of the above element combination; or the like. A film structure in which a refractory metal of '钽, titanium, molybdenum, or tungsten is stacked on the upper or lower side of the aluminum or stomach &amp; @ _ film can be used. Preferably, aluminum or copper is combined with X-resistant material to avoid thermal resistance problems and rust problems. As the fire resistant metal material, molybdenum, titanium, chromium, molybdenum, tungsten, rhenium, ruthenium, osmium, or the like can be used. Alternatively, the conductive film may have a single layer structure or a stack of two or more layers -77-201220292 laminated structure. For example, a single-layer structure including an aluminum film of tantalum; a two-layer structure in which a titanium film is stacked on an aluminum film; a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order can be given ; and its analogues. A conductive metal oxide can be used for the conductive film included in the conductive film 705 and the conductive film 706. As the conductive metal oxide, an alloy of indium oxide, tin oxide, zinc oxide, indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, or a metal oxide material containing cerium or cerium oxide can be used. In the case where the heat treatment is performed after the formation of the conductive film, preferably, the conductive film has a heat resistance sufficient to withstand the heat treatment. Note that the material and etching conditions should be appropriately adjusted so that the island-shaped oxide semiconductor film 704 is not removed as much as possible in the etching of the conductive film. According to the etching case, there are cases in which the exposed portion of the island-shaped oxide semiconductor film 704 is partially etched, and thus, the groove (recessed portion) is formed. In this embodiment, a titanium film is used for the conductive film. Therefore, wet etching can be selectively performed on the conductive film using a solution containing ammonia and hydrogen peroxide (ammonium hydroxide mixed solution). Specifically, an aqueous solution in which 31% by weight of hydrogen peroxide, 28% by weight of ammonium hydroxide, and pure water are mixed in a volume ratio of 5:2:2 can be used. Alternatively, dry etching may be performed on the conductive film using a gas containing chlorine (Cl2), boron chloride (BC13), or the like. In order to reduce the number of reticle and steps in the photolithography step, it is possible to perform the use of a resistive mask formed by a multi-tone mask that transmits light.

S 201220292 蝕刻1以便具有複數個光強度。使用多 阻體罩幕具有複數個厚度’且進一步地 形狀：因而，該阻體罩幕可使用於用以 之複數個蝕刻步驟中。因此，對應於至 同圖案的阻體罩幕可藉由一多色調罩幕 降低光曝射罩幕的數目，且亦可降低對 的數目，而可藉以實現製程之簡化。 注意的是，在絕緣膜707的形成之 導體膜704係接受使用諸如N20、N2、 漿處理。藉由該電漿處理，可將附著至 膜704的表面之所吸附的水或其類似物 理亦可使用氧及氬的混合氣體而執行》 較佳地，絕緣膜707盡量不包含諸 。可使用單層之絕緣膜或堆疊之複數彳 707。包含於絕緣膜707中之氫可進入 提取氧化物半導體膜之中的氧，而使島 7 04之背面通道部分的電阻減少（η型 會形成寄生通道。因此，重要的是，使 之膜形成方法，使得該絕緣膜707盡量 障壁性質之材料係較佳地使用於絕緣膜 矽膜、氧化氮化矽膜、氮化鋁膜、氧化 似物可使用做爲具有高障壁性質之絕緣 堆疊之絕緣膜的情況中，諸如氧化矽膜 比例低的絕緣膜係形成於比具有高障壁 色調罩幕所形成的 可藉由蝕刻而改變 處理成爲不同圖案 少二種或更多種不 而形成。從而，可 應之光微影術步驟 前，島狀氧化物半 或Ar之氣體的電 島狀氧化物半導體 予以去除。電漿處 如水分或氫之雜質 固絕緣膜於絕緣膜 氧化物半導體膜或 狀氧化物半導體膜 導電性）；因而， 用其中並不使用氫 不包含氫。具有高 707。例如，氮化 氮化鋁膜、或其類 膜。在使用複數個 或氮氧化矽膜之氮 性質之絕緣膜更靠 -79- 201220292 近島狀氧化物半導體膜7 04的位置處。然後，具有高障壁 性質之絕緣膜係形成以重疊導電膜705、導電膜706、及 島狀氧化物半導體膜704，而氮比例低的絕緣膜係介於其 間。透過具有高障壁性質之絕緣膜的使用，可防止諸如水 分或氫之雜質進入島狀氧化物半導體膜704、閘極絕緣膜 703、或該島狀氧化物半導體膜704與另一絕緣膜間之介 面及其附近。進一步地，藉由提供諸如氧化矽膜或氮氧化 矽膜之氮比例低的絕緣膜，以便與島狀氧化物半導體膜 704接觸，則可防止具有高障壁性質之絕緣膜與該島狀氧 化物半導體膜704直接接觸》 在此實施例中，絕緣膜707具有其中藉由濺渡法所形 成之具有100奈米之厚度的氮化矽膜係堆疊於藉由濺鍍法 所形成之具有200奈米之厚度的氮化矽膜之上的結構。在 膜形成中之基板溫度可設定爲高於或等於室溫且低於或等 於300°C ;在此實施例中，係100°C。 在形成絕緣膜707之後，可執行熱處理。該熱處理係 較佳地在氮、超乾燥空氣、或稀有氣體（氬，氦，或其類 似物）之氛圍下，被執行於高於或等於2 00 °C且低於或等 於400t，例如，高於或等於2 50°C且低於或等於3 5 0°C的 溫度處。所欲的是，在該氣氣體中之水的含量係2 Oppm或 更少，較佳地係1 p p m或更少，且更佳地係1 0 p p b或更少 。例如，在此實施例中，係在氮氛圍下執行250 °C之熱處 理，1小時。選擇性地，可以以與先前在氧化物半導體膜 上所執行之用以降低水分或氫之熱處理方式相似的方式， -80 -S 201220292 Etch 1 to have a plurality of light intensities. The multi-resistance mask has a plurality of thicknesses' and is further shaped: thus, the barrier mask can be used in a plurality of etching steps. Therefore, the resist mask corresponding to the same pattern can reduce the number of light-exposure masks by a multi-tone mask, and can also reduce the number of pairs, thereby simplifying the process. Note that the conductor film 704 formed in the insulating film 707 is subjected to treatment such as N20, N2, slurry. By the plasma treatment, the adsorbed water or the like attached to the surface of the film 704 can be carried out using a mixed gas of oxygen and argon. Preferably, the insulating film 707 is not included as much as possible. A single layer of insulating film or a stacked plurality of 707 707 can be used. The hydrogen contained in the insulating film 707 can enter the oxygen in the extraction oxide semiconductor film, and the resistance of the channel portion of the back surface of the island 704 is reduced (the n-type forms a parasitic channel. Therefore, it is important to form the film. In the method, the insulating film 707 is preferably used as a barrier material for the insulating film, the tantalum oxide film, the aluminum nitride film, and the oxide can be used as the insulating layer of the insulating stack having high barrier properties. In the case of a film, an insulating film such as a low proportion of yttrium oxide film is formed not less than two or more types which are formed by a mask having a high barrier color tone and which can be changed into a different pattern by etching. Before the photolithography step, the island-like oxide semi- or Ar gas gas island-like oxide semiconductor is removed. The plasma is filled with impurities such as moisture or hydrogen, and the insulating film is in the insulating film oxide semiconductor film or shape. The oxide semiconductor film is electrically conductive; therefore, hydrogen is not contained therein without using hydrogen. Has a high of 707. For example, an aluminum nitride nitride film, or a film thereof. The insulating film using a plurality of nitrogen or yttrium oxynitride films is further located at -79-201220292 near the island-shaped oxide semiconductor film 704. Then, an insulating film having a high barrier property is formed to overlap the conductive film 705, the conductive film 706, and the island-shaped oxide semiconductor film 704 with an insulating film having a low nitrogen ratio interposed therebetween. By using the insulating film having high barrier properties, impurities such as moisture or hydrogen can be prevented from entering the island-shaped oxide semiconductor film 704, the gate insulating film 703, or the island-shaped oxide semiconductor film 704 and another insulating film. Interface and its vicinity. Further, by providing an insulating film having a low proportion of nitrogen such as a hafnium oxide film or a hafnium oxynitride film to be in contact with the island-shaped oxide semiconductor film 704, an insulating film having high barrier properties and the island oxide can be prevented. The semiconductor film 704 is in direct contact with each other. In this embodiment, the insulating film 707 has a tantalum nitride film layer having a thickness of 100 nm formed by a sputtering method and having a thickness of 200 nm formed by a sputtering method. The thickness of the structure above the tantalum nitride film. The substrate temperature in film formation can be set to be higher than or equal to room temperature and lower than or equal to 300 ° C; in this embodiment, 100 ° C. After the insulating film 707 is formed, heat treatment can be performed. The heat treatment is preferably carried out at a temperature higher than or equal to 200 ° C and lower than or equal to 400 t under an atmosphere of nitrogen, ultra-dry air, or a rare gas (argon, helium, or the like), for example, Above or equal to 2 50 ° C and below or equal to 350 ° C. Desirably, the content of water in the gas is 2 Oppm or less, preferably 1 p p m or less, and more preferably 10 p p b or less. For example, in this embodiment, heat treatment at 250 °C was performed under a nitrogen atmosphere for 1 hour. Alternatively, it may be in a similar manner to the heat treatment previously performed on the oxide semiconductor film to reduce moisture or hydrogen, -80 -

S 201220292 而在導電膜705及導電膜706的形成之前執行高溫短時間 的RT A處理。即使當氧缺乏係由於先前的熱處理而產生 於島狀氧化物半導體膜704之中時，藉由在提供包含氧的 絕緣膜707之後而執行熱處理，亦可將氧自絕緣膜707而 供應至島狀氧化物半導體膜704。由於針對島狀氧化物半 導體膜704的氧施與，所以可降低島狀氧化物半導體膜 704中之用作施體的氧缺乏，且可滿足化學計量的組成。 較佳地，該島狀氧化物半導體膜704包含組成比例超過化 學計量組成比例的氧。因而，可使島狀氧化物半導體膜 704成爲實質i型，且可降低由於氧缺乏之電晶體之電性 特徵中的變化：因此，可增進電性特徵。此熱處理的時序 並未受到特別限制，只要其係在絕緣膜707的形成之後即 可。當此熱處理重複成爲諸如用於樹脂膜之形成的熱處理 或用於透光導電膜之電阻降低的熱處理之另一步驟時，可 無需增加製造步驟的數目而使該島狀氧化物半導體膜704 成爲實質i型。 此外，在島狀氧化物半導體膜704中之用作施體的氧 缺乏可藉由使該島狀氧化物半導體膜704接受在氧氛圍中 之使得氧被添加至氧化物半導體的熱處理，而予以降低。 例如，該熱處理係執行於高於或等於l〇〇°C且低於3 5 0°C ，較佳地於高於或等於150°C且低於25 0 °C的溫度處。較 佳地，使用於氧氛圍下之熱處理的氧氣體不包含水、氫、 或其類似物。選擇性地，所引入至熱處理設備之內的氧氣 體之純度係較佳地大於或等於6N( 99.9999%)，或更佳 -81 - 201220292 地大於或等於7N ( 99·99999% )(亦即，在該氧中 濃度係小於或等於lppm，或較佳地小於或等於〇. 〇 選擇性地，可藉由離子佈植法或離子摻雜法而 加至島狀氧化物半導體膜704，以降低用作施體之 。例如’可將藉由2.45 GHz的微波而變成電漿狀態 加至島狀氧化物半導體膜704。 背面閘極電極可藉由形成導電膜於絕緣膜707 然後’使該導電膜圖案化而予以形成，以便與島狀 半導體膜7〇4重疊。在其中形成背面閘極電極的情 較佳地形成絕緣膜，以便覆蓋該背面閘極電極。該 極電極可使用與閘極電極702或導電膜705及706 材料及結構相似的材料及結構而形成。 背面閘極電極的厚度係10奈米至400奈米， 係100奈米至200奈米。例如，背面閘極電極可以 式而形成，亦即，形成其中堆疊鈦膜、鋁膜、及鈦 電膜，藉由光微影術方法或其類似方法而形成阻體 以及藉由蝕刻而去除導電膜之不必要的部分，以致 電膜被處理（圖案化）成爲所欲之形狀的方式。 透過上述處理，可形成電晶體708。 電晶體708包含：閘極電極702 ;閘極絕緣膜 在閘極電極702之上；島狀氧化物半導體膜7〇4， 閘極絕緣膜703之上，且與閘極電極7〇2重疊；以 膜705及導電膜7〇6之對，係形成於島狀氧化物半 之雜質 1 ppm ) 將氧添 氧缺乏 之氧添 上，且 氧化物 況中， 背面閘 之該等 較佳地 以此方 膜之導 罩幕， 使該導 703， 其係在 及導電 導體膜S 201220292 And the high temperature short time RT A process is performed before the formation of the conductive film 705 and the conductive film 706. Even when oxygen deficiency is generated in the island-shaped oxide semiconductor film 704 due to the prior heat treatment, oxygen can be supplied from the insulating film 707 to the island by performing heat treatment after providing the insulating film 707 containing oxygen. An oxide semiconductor film 704. Since the oxygen is applied to the island-shaped oxide semiconductor film 704, the oxygen deficiency used as the donor in the island-shaped oxide semiconductor film 704 can be reduced, and the stoichiometric composition can be satisfied. Preferably, the island-shaped oxide semiconductor film 704 contains oxygen having a composition ratio exceeding a stoichiometric composition ratio. Therefore, the island-shaped oxide semiconductor film 704 can be made substantially i-type, and variations in the electrical characteristics of the transistor due to oxygen deficiency can be reduced: therefore, electrical characteristics can be enhanced. The timing of this heat treatment is not particularly limited as long as it is after the formation of the insulating film 707. When this heat treatment is repeated as another step such as heat treatment for forming a resin film or heat treatment for reducing resistance of the light-transmitting conductive film, the island-shaped oxide semiconductor film 704 can be made without increasing the number of manufacturing steps. Substantial i-type. Further, the oxygen deficiency used as the donor in the island-shaped oxide semiconductor film 704 can be obtained by subjecting the island-shaped oxide semiconductor film 704 to heat treatment in which an oxygen is added to the oxide semiconductor. reduce. For example, the heat treatment is performed at a temperature higher than or equal to 10 ° C and lower than 350 ° C, preferably higher than or equal to 150 ° C and lower than 25 ° C. Preferably, the oxygen gas used for the heat treatment under an oxygen atmosphere does not contain water, hydrogen, or the like. Optionally, the purity of the oxygen gas introduced into the heat treatment apparatus is preferably greater than or equal to 6N (99.9999%), or more preferably -81 - 201220292 is greater than or equal to 7N (99.99999%) (ie, The concentration in the oxygen is less than or equal to 1 ppm, or preferably less than or equal to 〇. 〇 selectively, may be added to the island-shaped oxide semiconductor film 704 by ion implantation or ion doping, The lowering is applied to the island-shaped oxide semiconductor film 704 by a microwave of 2.45 GHz. The back gate electrode can be formed by forming a conductive film on the insulating film 707 and then The conductive film is patterned to be overlapped to overlap with the island-shaped semiconductor film 7〇4. In the case where the back gate electrode is formed, an insulating film is preferably formed so as to cover the back gate electrode. The electrode 702 or the conductive film 705 and 706 are formed of materials and structures similar in structure. The thickness of the back gate electrode is 10 nm to 400 nm, and is 100 nm to 200 nm. For example, the back gate electrode Can be formed, that is, Forming a titanium film, an aluminum film, and a titanium electric film therein, forming a resistor by a photolithography method or the like, and removing unnecessary portions of the conductive film by etching, to call the film to be processed (pattern The transistor is formed into a desired shape. Through the above process, a transistor 708 can be formed. The transistor 708 includes: a gate electrode 702; a gate insulating film over the gate electrode 702; and an island-shaped oxide semiconductor film 7 4, on the gate insulating film 703, and overlap with the gate electrode 7〇2; the pair of the film 705 and the conductive film 7〇6 are formed in the island oxide half impurity 1 ppm) The oxygen is added, and in the oxide state, the back gate is preferably the guide film of the square film, and the conductor 703 is attached to the conductive conductor film.

-82- S 201220292 704之上。進一步地，電晶體708可包含絕緣膜7〇7，做 爲其組分。在第21C圖中所描繪的電晶體708具有通道蝕 刻之結構，其中係蝕刻導電膜7〇5與導電膜706間之島狀 氧化物半導體膜704的一部分。 雖然電晶體708係描繪成爲單一閘極電晶體，但包含 複數個通道形成區之多閘極電晶體亦可被製造出；在該情 況中，係包含彼此互相電性連接之複數個閘極電極702。 此實施例可與上述該等實施例之任一者適當地結合。 (實施例4) 在此實施例4之中，將敘述電晶體的結構實例。注意 的是，與上述實施例中之該等部分相同的部分，具有與上 述實施例中之該等功能相似之功能的部分，與上述實施例 中之該等步驟相同的步驟，以及與上述實施例中之該等步 驟相似的步驟可如上述實施例中似地被描述，且其重複之 說明將在此實施例中予以省略。此外，用於相同部分之具 體說明亦將予以省略。 在第22A圖中所描繪之電晶體2450包含：閘極電極 2401，於基板2400上；閘極絕緣膜2402，於閘極電極 24 01上；氧化物半導體膜2403，於閘極絕緣膜2402上； 以及源極電極24〇5a及汲極電極2405b，於氧化物半導體 膜2403上。絕緣膜2407係形成於氧化物半導體膜2403， 源極電極2405a，及汲極電極2405b之上。保護絕緣膜 2409可形成於絕緣膜24〇7上。電晶體2450係底部閘極電 -83- 201220292 晶體，且亦係反轉交錯型電晶體。 在第22B圖中所描繪之電晶體2460包含：閘極電極 2401，於基板2400上；閘極絕緣膜2402，於閘極電極 2401上：氧化物半導體膜2403，於閘極絕緣膜2402上； 通道保護層2406，於氧化物半導體膜2403上；以及源極 電極2 40 5a及汲極電極2405b，於通道保護層24 06及氧化 物半導體膜24 03上。保護絕緣膜2409可形成於源極電極 2405a及汲極電極2405b之上。電晶體2460係所謂通道保 護型（亦稱爲通道阻斷型）電晶體之底部閘極電晶體，且 亦係反轉交錯型電晶體。該通道保護層2406可使用與任 何其他絕緣膜之該等材料及方法相似的材料及方法而形成 〇 在第22C圖中所描繪之電晶體2470包含：基底膜 2436，於基板2400上；氧化物半導體膜2403，於基底膜 2436上；源極電極2405a及汲極電極2405b，於氧化物半 導體膜2403及基底膜2436上：閘極絕緣膜2402，於氧化 物半導體膜2403、源極電極2 40 5a、及汲極電極2 40 5b上 ;以及閘極電極2401，於閘極絕緣膜2402上。保護絕緣 膜2409可形成於閘極電極2401之上。電晶體2470係頂 部閘極電晶體。 第2 2D圖中所描繪之電晶體2480包含：第一閘極電 極2411，於基板24 00上；第一閘極絕緣膜2413，於第一 閘極電極241 1上；氧化物半導體膜2403，於第一閘極絕 緣膜2413上；以及源極電極2405a及汲極電極2405b，於 -84--82- S 201220292 704 above. Further, the transistor 708 may include an insulating film 7〇7 as a component thereof. The transistor 708 depicted in Fig. 21C has a channel etched structure in which a portion of the island-shaped oxide semiconductor film 704 between the conductive film 7〇5 and the conductive film 706 is etched. Although the transistor 708 is depicted as a single gate transistor, a multi-gate transistor comprising a plurality of channel formation regions can also be fabricated; in this case, a plurality of gate electrodes electrically connected to each other 702. This embodiment can be combined as appropriate with any of the above-described embodiments. (Embodiment 4) In this Embodiment 4, a structural example of a transistor will be described. It is to be noted that the same portions as those of the above-described embodiments have the same functions as those of the above-described embodiments, the same steps as those of the above-described embodiments, and the above-described implementation. The steps similar to those in the examples can be described as in the above embodiment, and the repeated description thereof will be omitted in this embodiment. In addition, specific descriptions for the same parts will also be omitted. The transistor 2450 depicted in FIG. 22A includes: a gate electrode 2401 on the substrate 2400; a gate insulating film 2402 on the gate electrode 241; and an oxide semiconductor film 2403 on the gate insulating film 2402. And a source electrode 24A5a and a drain electrode 2405b on the oxide semiconductor film 2403. The insulating film 2407 is formed over the oxide semiconductor film 2403, the source electrode 2405a, and the drain electrode 2405b. A protective insulating film 2409 may be formed on the insulating film 24A. The transistor 2450 is a bottom gate electrically -83-201220292 crystal, and is also an inverted staggered transistor. The transistor 2460 depicted in FIG. 22B includes: a gate electrode 2401 on the substrate 2400; a gate insulating film 2402 on the gate electrode 2401: an oxide semiconductor film 2403 on the gate insulating film 2402; The channel protection layer 2406 is on the oxide semiconductor film 2403; and the source electrode 2 40 5a and the drain electrode 2405b are on the channel protection layer 460 and the oxide semiconductor film 242. A protective insulating film 2409 may be formed over the source electrode 2405a and the drain electrode 2405b. The transistor 2460 is a bottom gate transistor of a so-called channel protection type (also referred to as channel blocking type) transistor, and is also an inverted staggered type transistor. The channel protection layer 2406 can be formed using materials and methods similar to those of any other insulating film. The transistor 2470 depicted in FIG. 22C includes a base film 2436 on the substrate 2400; an oxide The semiconductor film 2403 is on the base film 2436; the source electrode 2405a and the drain electrode 2405b are on the oxide semiconductor film 2403 and the base film 2436: a gate insulating film 2402, and an oxide semiconductor film 2403 and a source electrode 240. 5a, and the drain electrode 2 40 5b; and the gate electrode 2401 on the gate insulating film 2402. A protective insulating film 2409 may be formed over the gate electrode 2401. Transistor 2470 is the top gate transistor. The transistor 2480 depicted in FIG. 2D includes: a first gate electrode 2411 on the substrate 24 00; a first gate insulating film 2413 on the first gate electrode 2411; and an oxide semiconductor film 2403, On the first gate insulating film 2413; and the source electrode 2405a and the drain electrode 2405b, at -84-

S 201220292 氧化物半導體膜2403及第一閘極絕緣膜2413上。第二閘 極絕緣膜2414係形成於氧化物半導體膜2403、源極電極 2405a、及汲極電極2405b上，以及第二閘極電極2412係 形成於第二閘極絕緣膜2414之上。保護絕緣膜2409可形 成於第二閘極電極2412之上。 電晶體2480具有結合電晶體2450及電晶體2470的 結構。第一閘極電極241 1及第二閘極電極2412可彼此互 相電性連接，以致使它們作用成爲一閘極電極。第一閘極 電極2 4 11或第二閘極電極24 12之任一者可簡稱爲閘極電 極，且另一者可稱爲背面閘極電極。 藉由改變背面閘極電極的電位，可改變電晶體的臨限 電壓。該背面閘極電極係形成以便與氧化物半導體膜2403 中的通道形成區重疊。進一步地，該背面閘極電極可予以 電性絕緣，亦即，在浮動狀態中，或可在其中該背面閘極 電極係供應以電位的狀態中。在後者之情況中，可以以與 閘極電極之位準相同位準的電位，或可以以諸如接地電位 的固定電位來供應背面閘極電極。所施加至背面閘極電極 之電位的位準係控制使得電晶體2480的臨限電壓可加以 控制》 氧化物半導體膜2403係覆蓋以背面閘極電極，而可 藉以防止來自背面閘極電極側的光進入該氧化物半導體膜 2403。因此，可防止該氧化物半導體膜2403的光致降級 ，且可防止諸如臨限電壓偏移之電晶體特徵中的劣化。 較佳地，與氧化物半導體膜2403接觸的絕緣膜（在 -85- 201220292 此實施例中，對應於閘極絕緣膜2402、絕备 道保護層2406、基底膜2436、第一閘極絕| 第二閘極絕緣膜2414之各者）係使用包含 13)元素及氧之絕緣材料而形成。許多氧化 包含族13元素，且包含族13元素之絕緣材 導體作功良好。藉由使用包含族13元素之 供與氧化物半導體膜接觸的絕緣膜之用，則 導體膜之介面可保持有利狀態。 包含族13元素之絕緣材料意指包含一 ϊ 元素的絕緣材料。做爲包含族13元素之絕 ，可給定氧化鎵、氧化鋁、氧化鋁鎵、及氧 ，在氧化鋁鎵中的原子百分比之中，鋁的數 數量，而在氧化鎵鋁中的原子百分比.之中， 於鋁之數量。 例如，在形成與包含鎵之氧化物半導體 膜的情況中，可使用包含氧化鎵之材料於絕 有利的特徵可保持於氧化物半導體膜與絕緣 。例如，藉由提供彼此互相接觸之氧化物半 氧化鎵之絕緣膜，可降低該氧化物半導體膜 的介面處之氫的堆積。注意的是，在其中使 導體膜之組成元素相同族群之元素於絕緣膜 可獲得相似的功效。例如，透過包含氧化鋁 而形成絕緣膜係有效的。因爲氧化鋁具有不 ’所以就防止水進入至氧化物半導體膜而言 条膜24〇7、通 象膜2413、及 族 13 ( Group 物半導體材料 料與氧化物半 該絕緣材料以 與該氧化物半 突更多個族13 緣材料，例如 化鎵鋁。此處 量係大於鎵之 鎵的數量係大 膜接觸之絕緣 緣膜，以致使 膜間之介面處 導體膜及包含 與該絕緣膜間 用與氧化物半 中的情況中， 之材料的使用 易透水之性質 ，使用包含氧S 201220292 The oxide semiconductor film 2403 and the first gate insulating film 2413. The second gate insulating film 2414 is formed on the oxide semiconductor film 2403, the source electrode 2405a, and the drain electrode 2405b, and the second gate electrode 2412 is formed on the second gate insulating film 2414. A protective insulating film 2409 may be formed over the second gate electrode 2412. The transistor 2480 has a structure in which a transistor 2450 and a transistor 2470 are bonded. The first gate electrode 241 1 and the second gate electrode 2412 may be electrically connected to each other such that they act as a gate electrode. Either the first gate electrode 2 4 11 or the second gate electrode 24 12 may be simply referred to as a gate electrode, and the other may be referred to as a back gate electrode. The threshold voltage of the transistor can be changed by changing the potential of the back gate electrode. The back gate electrode is formed so as to overlap with the channel formation region in the oxide semiconductor film 2403. Further, the back gate electrode may be electrically insulated, that is, in a floating state, or may be in a state in which the back gate electrode system is supplied with a potential. In the latter case, the potential of the gate electrode may be at the same level as the level of the gate electrode, or the gate electrode may be supplied with a fixed potential such as a ground potential. The level control applied to the potential of the back gate electrode allows the threshold voltage of the transistor 2480 to be controlled. The oxide semiconductor film 2403 is covered with the back gate electrode, thereby preventing the gate electrode side from the back side. Light enters the oxide semiconductor film 2403. Therefore, photodegradation of the oxide semiconductor film 2403 can be prevented, and deterioration in a transistor characteristic such as a threshold voltage shift can be prevented. Preferably, the insulating film is in contact with the oxide semiconductor film 2403 (in the embodiment -85-201220292, corresponding to the gate insulating film 2402, the absolute protective layer 2406, the base film 2436, and the first gate absolutely | Each of the second gate insulating films 2414 is formed using an insulating material containing 13) elements and oxygen. Many of the oxides contain a group 13 element, and the insulator material containing the group 13 element works well. By using an insulating film containing a group 13 element for contact with the oxide semiconductor film, the interface of the conductor film can be maintained in an advantageous state. An insulating material containing a group 13 element means an insulating material containing a bismuth element. As a member of the group 13 element, given gallium oxide, aluminum oxide, aluminum gallium oxide, and oxygen, among the atomic percentages in aluminum gallium, the number of aluminum, and the atomic percentage in gallium aluminum oxide Among them, the amount of aluminum. For example, in the case of forming an oxide semiconductor film containing gallium, a material containing gallium oxide can be used to maintain the oxide semiconductor film and insulation in an advantageous characteristic. For example, by providing an insulating film of oxide gallium oxide which is in contact with each other, the accumulation of hydrogen at the interface of the oxide semiconductor film can be reduced. Note that an element in which the same group of constituent elements of the conductor film is made to have a similar effect on the insulating film. For example, it is effective to form an insulating film by including alumina. Since the alumina has no ', it prevents the water from entering the oxide semiconductor film, the strip film 24〇7, the pass film 2413, and the group 13 (the group semiconductor material and the oxide half of the insulating material and the oxide More than a family of 13 edge materials, such as gallium aluminum. Here the amount of gallium larger than gallium is the insulating film of the large film contact, so that the film between the film and the interface between the film and the insulating film In the case of use with oxides, the use of materials is easily permeable to water, including the use of oxygen

-86- S 201220292 化鋁之材料係較佳的。 較佳地，與氧化物半導體膜2403接觸之絕緣膜藉由 在氧氛圍中之熱處理，或氧摻雜，而以高於化學計量的組 成中之比例的比例來包含氧。氧摻雜意指添加氧至巨形之 內。“巨形”之用語係使用以便釐清的是，氧不僅被添加至 薄膜的表面，而且被添加至薄膜內部。此外，氧摻雜在其 種類中包含氧電漿摻雜，其中將變成爲電漿之氧添加至巨 形。氧摻雜可使用離子佈植法或離子摻雜法而執行。 例如，在其中與氧化物半導體膜2403接觸的絕緣膜 係由氧化鎵所形成的情況中，氧化鎵之組成可藉由在氧氛 圍中之熱處理，或氧摻雜，而被設定成爲Ga2Ox(x = 3+a ，0 &lt; α &lt; · 1 )。 在其中與氧化物半導體膜2403接觸的絕緣膜係由氧 化鋁所形成的情況中，氧化鋁之組成可藉由在氧氛圍中之 熱處理，或氧摻雜，而被設定成爲Α120χ(χ = 3+α - 0&lt;α &lt; 1 ) ° 在其中與氧化物半導體膜2403接觸的絕緣膜係由氧 化鎵鋁（或氧化鋁鎵）所形成的情況中，氧化鎵鋁（或氧 化鋁鎵）之組成可藉由在氧氛圍中之熱處理，或氧摻雜， 而被設定成爲 GaxAl2.x03 + a (0&lt;χ&lt;·2，0&lt;α&lt;1)。 藉由氧摻雜，可形成包含其中氧的比例係高於化學計 量的組成中之氧的比例之區域的絕緣膜。當包含該區域之 絕緣膜與氧化物半導體膜接觸時，過量存在於絕緣膜中之 氧會被供應至氧化物半導體膜，且在氧化物半導體膜中或 -87- 201220292 在氧化物半導體膜與絕緣膜間之介面處的氧 因此，氧化物半導體膜可形成爲i型或實質 導體。 包含其中氧的比例係高於化學計量的組 例之區域的絕緣膜可施加至與氧化物半導體 的該等絕緣膜之設置於氧化物半導體膜的上 ，或設置於氧化物半導體膜的下方側之絕緣 加該絕緣膜至與氧化物半導體膜2403接觸 二者係佳的》上述功效可以以其中氧化物d 係介於該等絕緣膜之間的結構來予以增強， 各自包含其中氧的比例係高於化學計量的組 例之區域，且該等絕緣膜係使用做爲與氧 2403接觸以及設置在氧化物半導體膜2403 方側之絕緣膜。 在氧化物半導體膜2403的上方側及下 可包含相同的組成元素或不同的組成元素。 側及下方側之該等絕緣膜均可使用其中組成 χ = 3+ α ，〇&lt; α &lt;1 )的氧化鎵而形成。選擇性 及下方側之該等絕緣膜的其中一者可使用 Ga2Ox ( χ = 3+ α，0&lt; α &lt;1 )的氧化鎵而形成 使用其中組成物係Α12Οχ(χ = 3+α，0&lt;α&lt;1 形成。 與氧化物半導體膜24〇3接觸之絕緣膜 自包含其中氧的比例係高於化學計量的組成 ,缺乏會降低。 i型氧化物半 成中之氧的比 :膜2403接觸 方側之絕緣膜 膜；然而，施 的該等絕緣膜 _導體膜2403 而該等絕緣膜 成中之氧的比 化物半導體膜 的上方側及下 方側之絕緣膜 例如，在上方 物係Ga2Ox ( 地，在上方側 其中組成物係 ，且另一者可 )的氧化鋁而 可藉由堆疊各 中之氧的比例 -88 --86- S 201220292 Aluminium alloy material is preferred. Preferably, the insulating film in contact with the oxide semiconductor film 2403 contains oxygen in a ratio of a ratio higher than the stoichiometric composition by heat treatment in an oxygen atmosphere or oxygen doping. Oxygen doping means the addition of oxygen to the giant form. The term "giant shape" is used to clarify that oxygen is not only added to the surface of the film but also added to the inside of the film. In addition, oxygen doping includes oxygen plasma doping in its species, where oxygen which becomes plasma is added to the giant shape. Oxygen doping can be performed using ion implantation or ion doping. For example, in the case where the insulating film in contact with the oxide semiconductor film 2403 is formed of gallium oxide, the composition of gallium oxide can be set to Ga2Ox (x) by heat treatment in an oxygen atmosphere or oxygen doping. = 3+a , 0 &lt; α &lt; · 1 ). In the case where the insulating film in contact with the oxide semiconductor film 2403 is formed of alumina, the composition of the alumina can be set to Α120 藉 by heat treatment in an oxygen atmosphere or oxygen doping (χ = 3) +α - 0&lt;α &lt; 1 ) ° In the case where the insulating film in contact with the oxide semiconductor film 2403 is formed of gallium aluminum oxide (or aluminum gallium oxide), gallium aluminum oxide (or aluminum gallium oxide) The composition can be set to GaxAl2.x03 + a (0&lt;χ&lt;·2, 0 &lt; α &lt; 1) by heat treatment in an oxygen atmosphere or oxygen doping. By doping with oxygen, an insulating film containing a region in which the ratio of oxygen is higher than the ratio of oxygen in the composition of the stoichiometric amount can be formed. When the insulating film including the region is in contact with the oxide semiconductor film, oxygen excessively present in the insulating film is supplied to the oxide semiconductor film, and in the oxide semiconductor film or -87-201220292 in the oxide semiconductor film and Oxygen at the interface between the insulating films Therefore, the oxide semiconductor film can be formed as an i-type or a substantial conductor. An insulating film including a region in which the ratio of oxygen is higher than a stoichiometric group may be applied to the insulating semiconductor film of the oxide semiconductor or to the lower side of the oxide semiconductor film. The insulating effect of the insulating film is preferably in contact with the oxide semiconductor film 2403. The above effects can be enhanced by a structure in which the oxide d is interposed between the insulating films, each of which contains a ratio of oxygen therein. A region higher than the stoichiometric group, and the insulating film is used as an insulating film which is in contact with the oxygen 2403 and is disposed on the side of the oxide semiconductor film 2403. The same constituent elements or different constituent elements may be contained on the upper side and the lower side of the oxide semiconductor film 2403. The insulating films on the side and the lower side can be formed using gallium oxide having a composition of χ = 3 + α , 〇 &lt; α &lt;1 ). One of the selective and lower insulating films may be formed using Ga2Ox (χ = 3+ α, 0 &lt; α &lt; 1 ) gallium oxide, wherein the composition system Α 12 Οχ (χ = 3+α, 0 &lt;; α &lt;1 is formed. The insulating film in contact with the oxide semiconductor film 24〇3 is composed of a ratio in which oxygen is higher than a stoichiometric composition, and the deficiency is lowered. The ratio of oxygen in the half-type oxide of the type I oxide: film 2403 An insulating film on the side of the contact side; however, the insulating film of the insulating film _ conductor film 2403 is applied to the upper side and the lower side of the semiconductor film of the insulating film in which the insulating film is formed, for example, in the upper structure Ga2Ox (ground, on the upper side, which constitutes the system, and the other can) alumina can be stacked by the ratio of oxygen in each -88 -

S 201220292 之區域的絕緣膜而形成。例如’在氧化物半導體膜2403 的上方側之絕緣膜可如下地形成：形成其中組成物係 Ga2Ox(x = 3+ a，0&lt;α&lt;1)之氧化鎵，且形成其中組成物 係GaxAl2.x〇3+a ( 〇&lt;x&lt;2 ’ 〇&lt; α &lt;1 )之氧化鎵鋁（氧化鋁 鎵）於其上。注意的是，在氧化物半導體膜2 403的下方 側之絕緣膜可藉由堆疊各自包含其中氧的比例係高於化學 計量的組成中之氧的比例之區域的絕緣膜而形成。進一步 地，在氧化物半導體膜2403的上方側及下方側之該等絕 緣膜二者均可藉由堆疊各自包含其中氧的比例係高於化學 計量的組成中之氧的比例之區域的絕緣膜而形成。 此實施例可與上述該等實施例之任一者適當地結合。 (實施例5 ) 在實施例 5中，將參照第23Α、23Β、23C、23C，、 23D、2 3D，、23Ε、23Ε，、24Α、2 4Β、及 24C 圖來敘述依 據本發明一實施例的液晶顯示裝置中所使用之基板的實施 例。 將被分離之層6116係形成於基板6200上，而分離層 6201係設置於其間（請參閱第23Α圖）。 石英基板，藍寶石基板，陶質基板，玻璃基板，金屬 基板’或其類似物可使用做爲基板6200。注意的是，足夠 厚而不會明確地成爲可撓曲的基板可致能諸如電晶體之元 件的精確形成。“不會明確地成爲可撓曲，，之程度意指該基 板的彈性模數係高於或等於在一般製造液晶顯示器中所使 89 - 201220292 用之玻璃基板的彈性模數。 分離層620 1係使用選自鎢（评）、鉬（Mo )、鈦（ Ti)、钽（Ta)、鈮（Nb)、鎳（Ni)、鈷（co)、锆（ Zr )、鋅（Zn )、釕（RU )、铑（Rh )、鈀（pd )、餓 (Os)、銥（Ir)、及矽（Si )之任一元素，包含上述任 —元素做爲其主要成分之合金材料，以及包含上述任一元 素做爲其主要成分之化合物材料，而藉由濺鍍法、電漿 CVD法、施加法、印刷法、或其類似方法，以單層或堆疊 層來予以形成。 在其中分離層6201具有單層之結構的情況中，較佳 地形成鎢層、鉬層、或包含鎢及鉬之混合物的層。選擇性 地，可形成包含鎢之氧化物或氮氧化物的層、包含鉬之氧 化物或氮氧化物的層、或包含鎢及鉬的混合物之氧化物或 氮氧化物的層。例如，鎢及鉬的混合物對應於鎢及鉬的合 金。 在其中分離層6201具有堆疊層之結構的情況中，較 佳的是，金屬層及金屬氧化物層分別形成爲第一層及第二 層。大致地，形成鎢層、鉬層、或包含鎢及鉬的混合物之 層做爲第一層，且形成鎢、鉬、或鎢及鉬的混合物之氧化 物、氮化物、氮氧化物、或氧化氮化物做爲第二層係較佳 的。當形成金屬氧化物層做爲第二層時，可在第一層的金 屬層上形成氧化物層（諸如可使用做爲絕緣層之氧化矽層 )，以致使該金屬的氧化物形成於該金屬層的表面上。 將被分離之層6 1 1 6包含用於元件基板所必要的組件 -90-S 201220292 is formed by an insulating film in the area. For example, the insulating film on the upper side of the oxide semiconductor film 2403 can be formed by forming gallium oxide in which the composition system Ga2Ox (x = 3+ a, 0 &lt; α &lt; 1), and forming the composition system GaxAl2 therein. X 〇 3 + a ( 〇 &lt; x &lt; 2 ' 〇 &lt; α &lt; 1 ) gallium aluminum oxide (gallium oxide) thereon. Note that the insulating film on the lower side of the oxide semiconductor film 2 403 can be formed by stacking insulating films each containing a region in which the ratio of oxygen is higher than the ratio of oxygen in the stoichiometric composition. Further, both of the insulating films on the upper side and the lower side of the oxide semiconductor film 2403 can be stacked by stacking an insulating film each containing a region in which the ratio of oxygen is higher than that in the stoichiometric composition. And formed. This embodiment can be combined as appropriate with any of the above-described embodiments. (Embodiment 5) In Embodiment 5, an embodiment according to the present invention will be described with reference to Figs. 23, 23, 23C, 23C, 23D, 2 3D, 23Ε, 23Ε, 24Α, 2 4Β, and 24C. An embodiment of a substrate used in a liquid crystal display device. The separated layer 6116 is formed on the substrate 6200, and the separation layer 6201 is disposed therebetween (see Fig. 23). A quartz substrate, a sapphire substrate, a ceramic substrate, a glass substrate, a metal substrate 'or the like can be used as the substrate 6200. It is noted that a substrate that is thick enough not to be clearly flexible can enable accurate formation of components such as transistors. "It does not explicitly become flexible, to the extent that the modulus of elasticity of the substrate is higher than or equal to the modulus of elasticity of the glass substrate used in the general manufacture of liquid crystal displays 89 - 201220292. Separation layer 620 1 It is selected from the group consisting of tungsten (nickel), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (co), zirconium (Zr), zinc (Zn), niobium. Any of (RU), rhodium (Rh), palladium (pd), hungry (Os), iridium (Ir), and yttrium (Si), including the above-mentioned any element as an alloy material of its main component, and Any of the above elements is used as a compound material as a main component thereof, and is formed by a single layer or a stacked layer by a sputtering method, a plasma CVD method, an application method, a printing method, or the like. In the case of a structure having a single layer of 6201, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is preferably formed. Alternatively, a layer containing tungsten oxide or oxynitride may be formed, including molybdenum. a layer of an oxide or oxynitride, or a layer comprising an oxide or oxynitride of a mixture of tungsten and molybdenum For example, a mixture of tungsten and molybdenum corresponds to an alloy of tungsten and molybdenum. In the case where the separation layer 6201 has a structure of a stacked layer, it is preferable that the metal layer and the metal oxide layer are formed as the first layer and the second layer, respectively. Generally, a tungsten layer, a molybdenum layer, or a layer comprising a mixture of tungsten and molybdenum is formed as a first layer, and tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed as an oxide, a nitride, an oxynitride, Or an oxynitride is preferred as the second layer. When the metal oxide layer is formed as the second layer, an oxide layer can be formed on the metal layer of the first layer (such as oxidation can be used as an insulating layer) a layer of germanium so that an oxide of the metal is formed on the surface of the metal layer. The layer 6 1 16 to be separated contains the components necessary for the element substrate - 90-

S 201220292 ’例如電晶體、層間絕緣膜、佈線、及像素電極，且視需 要地包含相對電極、遮光膜、配向膜、及其類似物。大致 ， 地’該等組件係形成於分離層6 2 0 1之上。該等組件之材 料、製造方法、及結構係與上述實施例的任一者中所敘述 之該等材料、製造方法、及結構相似，且其重複說明將予 以省赂於此實施例中。因此，電晶體及電極可使用已知的 材料和已知的方法而精確地形成。 其次，將被分離之層6116係透過用於分離之黏著劑 62〇3的使用而接合至臨時支撐基板6202，且然後，使將 被分離之層6116分離自將被轉移的基板6200上之分離層 62 01 (請參閱第23B圖）。在此方式中，可使將被分離之 層6116被設置在臨時支撐基板側。注意的是，在此說明 書中，用以自基板來轉移將被分離之層至臨時支撐基板的 處理係稱爲轉移處理》 做爲該臨時支撐基板6202，可使用玻璃基板、石英基 板、藍寶石基板、陶質基板、金屬基板、或其類似物。選 擇性地，可使用可耐受跟著的處理之溫度的塑膠基板。 做爲在此所使用之用於分離的黏著劑6203，係使用可 溶於水或溶劑之中的黏著劑、能在當照射紫外光時被塑化 之黏著劑、或其類似物，使得當需要時，可使臨時支撐基 板6 20 2:與將被分離之層6116分離。 可適當地使用各式各樣方法的任一者於用以轉移將被 分離之層6116至臨時支撐基板6202的處理中。例如，當 包含金屬氧化物膜之膜係形成爲分離層6201以便與將被 -91 - 201220292 分離之層6116接觸時，該金屬氧化物膜係藉由晶體化來 予以脆化，而將被分離之層6116可藉以自基板6200而分 離。當包含氫之非晶矽膜係形成爲基板6200與將被分離 之層6 1 1 6間的分離層620 1時，則包含氫之非晶矽膜係藉 由雷射光照射或蝕刻而被去除，以致使將被分離之層6116 可自基板6200而分離。在其中包含氮、氧、氫、或其類 似物之膜（例如，包含氫之非晶矽膜，包含氫之合金膜， 包含氧之合金膜，或其類似物）係使用做爲分離層62 0 1 的情況中，該分離層620 1可以以雷射光來照射，而釋出 分離層6201中所包含的氮、氧、或氫成爲氣體，以致可 促進將被分離之層6116與基板62 00間的分離。選擇性地 ，可使液體穿透分離層6201與將被分離之層6116間的介 面，而導致將被分離之層6116與基板62 00的分離。仍選 擇性地，當分離層6201係使用鎢而形成時，則在使用氨 水及過氧化氫溶液的混合溶液而蝕刻分離層的同時，可執 行該分離。 進一步地，轉移處理可藉由結合地使用上述之複數種 分離方法而予以促成。也就是說，在執行雷射光照射於分 離層的一部分，以氣體、液體、或其類似物而執行蝕刻於 分離層的一部分，或以銳利小刀、手術刀、或其類似物而 執行分離層之一部分的機械性去除之後，可以以物理力（ 藉由機器或其類似物）而執行分離，以使分離層與將被分 離之層可易於彼此互相分離。在其中分離層6201係形成 爲具有金屬及金屬氧化物之成層結構的情況中，將被分離 -92-S 201220292 ', for example, a transistor, an interlayer insulating film, a wiring, and a pixel electrode, and optionally include an opposite electrode, a light shielding film, an alignment film, and the like. Roughly, the components are formed on the separation layer 6 2 0 1 . The materials, manufacturing methods, and structures of the components are similar to those described in any of the above embodiments, and the repeated description thereof will be omitted in this embodiment. Therefore, the crystal and the electrode can be accurately formed using known materials and known methods. Next, the separated layer 6116 is bonded to the temporary supporting substrate 6202 through the use of the adhesive 62 〇 3 for separation, and then, the separated layer 6116 is separated from the substrate 6200 to be transferred. Layer 62 01 (see Figure 23B). In this manner, the layer 6116 to be separated can be disposed on the side of the temporary supporting substrate. Note that, in this specification, a process for transferring a layer to be separated from a substrate to a temporary support substrate is referred to as a transfer process. As the temporary support substrate 6202, a glass substrate, a quartz substrate, or a sapphire substrate may be used. , a ceramic substrate, a metal substrate, or the like. Alternatively, a plastic substrate that can withstand the temperature of the subsequent treatment can be used. As the adhesive 6203 for separation used herein, an adhesive which is soluble in water or a solvent, an adhesive which can be plasticized when irradiated with ultraviolet light, or the like is used. If desired, the temporary support substrate 6 20 2 can be separated from the layer 6116 to be separated. Any of a variety of methods can be suitably used in the process for transferring the layer 6116 to be separated to the temporary support substrate 6202. For example, when a film system including a metal oxide film is formed as the separation layer 6201 so as to be in contact with the layer 6116 to be separated by -91 - 201220292, the metal oxide film is embrittled by crystallization, and will be separated. The layer 6116 can be separated from the substrate 6200. When the amorphous germanium film containing hydrogen is formed as the separation layer 620 1 between the substrate 6200 and the layer 6 1 16 to be separated, the amorphous germanium film containing hydrogen is removed by laser irradiation or etching. So that the layer 6116 to be separated can be separated from the substrate 6200. A film containing nitrogen, oxygen, hydrogen, or the like (for example, an amorphous ruthenium film containing hydrogen, an alloy film containing hydrogen, an alloy film containing oxygen, or the like) is used as the separation layer 62. In the case of 0 1 , the separation layer 620 1 may be irradiated with laser light to release nitrogen, oxygen, or hydrogen contained in the separation layer 6201 into a gas, so that the layer 6116 to be separated and the substrate 62 00 may be promoted. Separation between. Alternatively, the liquid can be allowed to penetrate the interface between the separation layer 6201 and the layer 6116 to be separated, resulting in separation of the separated layer 6116 from the substrate 62 00. Still alternatively, when the separation layer 6201 is formed using tungsten, the separation can be performed while etching the separation layer using a mixed solution of ammonia water and a hydrogen peroxide solution. Further, the transfer treatment can be facilitated by using a plurality of separation methods as described above in combination. That is, a portion of the separation layer is etched with a gas, a liquid, or the like, or a separation layer is performed with a sharp knife, a scalpel, or the like, while performing laser light irradiation on a part of the separation layer. After a part of the mechanical removal, the separation can be performed by physical force (by machine or the like) so that the separation layer and the layer to be separated can be easily separated from each other. In the case where the separation layer 6201 is formed to have a layered structure of a metal and a metal oxide, it will be separated -92-

S 201220292 之層可藉由使用雷射光照射所形成的刻槽或銳利小刀、手 術刀、或其類似物所作成的刮痕當作起頭，而易於自分離 層實體地分離。 選擇性地，分離可在當澆注諸如水之液體時的同時， 且予以執行。 做爲用以自基板6200而分離將被分離之層6116的方 法，可選擇性地使用其中形成將被分離之層6 1 1 6於其上 的基板6200係藉由機械硏磨法，或藉由使用溶液或諸如 NF3、13rF3、或C1F3之鹵素氟化物氣體的蝕刻法而予以去 除之方法，或其類似方法。在該情況中，無需一定要設置 分離層6201。 接著，由於將被分離之層6116與基板62 00的分離而 暴露出之將被分離之層6116或分離層6201的表面係使用 第一黏著層6111而接合至轉移基板6110，該第一黏著層 6111包含與用於分離之黏著劑6203不同的黏著劑（請參 閱第2 3 C圖）。 做爲第一黏著層6111，可使用各式各樣硬化型黏著劑 之任一者，例如，諸如紫外線硬化黏著劑之光硬化黏著劑 、反應性硬化黏著劑、執硬化黏著劑、及厭氧黏著劑。 做爲轉移基板6110，可適當地使用諸如有機樹脂膜及 金屬基板之具有高韌性之各式各樣基板的任一者。具有高 的韌性之基板具備高的抗衝擊性，且因此，較不可能損壞 。在使用輕便之有機樹脂膜或薄金屬基板的情況中，重量 可大大地低於使用一般玻璃基板之情況。透過該基板之使 -93- 201220292 用，可製造出不易損壞之輕便的液晶顯示裝置。 在透射式或透射反射式液晶顯示裝置的情況中，可使 用具有高韌性且可透射可見光之基板做爲轉移基板6110。 做爲該基板之材料，例如，可給定諸如聚乙烯對苯二甲酸 酯（PET)、聚乙烯萘二甲酸酯（PEN )、丙烯酸樹脂、 聚丙烯腈樹脂、聚醯乙胺樹脂、聚甲基丙烯酸甲酯樹脂、 聚碳酸酯（PC )樹脂、聚醚颯（PES )樹脂、聚醯胺樹脂 、環烯烴聚合物樹脂、聚苯乙烯樹脂、聚醯胺乙胺樹脂、 及聚氯乙烯樹脂之多元酯樹脂。藉由該有機樹脂所製成之 基板具有高的韌性且因而具有高的抗衝擊性，以及較不可 能損壞。進一步地，輕便之該有機樹脂的膜可使顯示裝置 之重量大大地降低，而不似一般的玻璃基板。在該情況中 ，該轉移基板6110係更佳地設置有金屬板6206，而該金 屬板6206至少具有孔於與其中透射各像素之光的區域重 疊的部分中。透過上述之結構，可形成具有高的韌性及高 的抗衝擊性且較不可能損壞，而同時可抑制尺寸之改變的 轉移基板6110。進一步地，當降低金屬板6206之厚度時 ，則可形成比一般玻璃基板更輕的轉移基板6110。透過該 基板之使用，可製造出不易損壞之輕便的液晶顯示裝置（ 請參閱第2 3 D圖）》The layer of S 201220292 can be used as a start by scratches formed by irradiation of laser light or a sharp knife, a scalpel, or the like, and is easily separated from the separation layer. Alternatively, the separation may be performed while pouring a liquid such as water. As a method for separating the layer 6116 to be separated from the substrate 6200, the substrate 6200 in which the layer 6 1 16 to be separated is formed may be selectively used by mechanical honing, or by A method of removing by using an etching method using a solution or a halogen fluoride gas such as NF3, 13rF3, or C1F3, or the like. In this case, it is not necessary to provide the separation layer 6201. Next, the surface of the layer 6116 or the separation layer 6201 to be separated due to the separation of the separated layer 6116 from the substrate 62 00 is bonded to the transfer substrate 6110 using the first adhesive layer 6111, the first adhesive layer. 6111 contains an adhesive different from the adhesive 6203 used for separation (see Figure 2 3 C). As the first adhesive layer 6111, any of various hardening adhesives can be used, for example, a photohardening adhesive such as an ultraviolet curing adhesive, a reactive hardening adhesive, a hardening adhesive, and an anaerobic agent. Adhesive. As the transfer substrate 6110, any of various substrates having high toughness such as an organic resin film and a metal substrate can be suitably used. A substrate having high toughness has high impact resistance and, therefore, is less likely to be damaged. In the case of using a lightweight organic resin film or a thin metal substrate, the weight can be considerably lower than in the case of using a general glass substrate. By using -93-201220292 through this substrate, it is possible to manufacture a portable liquid crystal display device that is not easily damaged. In the case of a transmissive or transflective liquid crystal display device, a substrate having high toughness and transmitting visible light can be used as the transfer substrate 6110. As the material of the substrate, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), acrylic resin, polyacrylonitrile resin, polyamide resin, Polymethyl methacrylate resin, polycarbonate (PC) resin, polyether oxime (PES) resin, polyamine resin, cycloolefin polymer resin, polystyrene resin, polyamidamine resin, and polychlorinated Polyester resin of vinyl resin. The substrate made of the organic resin has high toughness and thus high impact resistance, and is less likely to be damaged. Further, the light-weight film of the organic resin can greatly reduce the weight of the display device unlike a general glass substrate. In this case, the transfer substrate 6110 is more preferably provided with a metal plate 6206, and the metal plate 6206 has at least a portion that is bored in a region overlapping with a region in which the light of each pixel is transmitted. Through the above structure, the transfer substrate 6110 which has high toughness and high impact resistance and is less likely to be damaged can be formed while suppressing the change in size. Further, when the thickness of the metal plate 6206 is lowered, the transfer substrate 6110 which is lighter than the general glass substrate can be formed. Through the use of the substrate, a portable liquid crystal display device that is not easily damaged can be manufactured (see Figure 2 3 D).

第24A圖係液晶顯示裝置之頂部視圖的實例。在其中 第一佈線層6210及第二佈線層6211彼此相交，且由第一 佈線層6210及第二佈線層6211所包圍的區域係透光區 6212之如第24A圖中所描繪的情況中，可使用如第24BFig. 24A is an example of a top view of a liquid crystal display device. In the case where the first wiring layer 6210 and the second wiring layer 6211 intersect each other, and the region surrounded by the first wiring layer 6210 and the second wiring layer 6211 is a light transmitting region 6212 as depicted in FIG. 24A, Can be used as in 24B

-94 - S 201220292 圖中之金屬板6206，而該金屬板6206具有以格柵所形成 的孔，以便留下與第一佈線層6210及/或第二佈線層6211 重疊的部分。如第24C圖中所示之金屬板6206的附著， 可抑制由於使用由有機樹脂所製成之基板的不適宜之配向 或基板之伸縮所造成的尺寸改變。當偏光板（未顯示）係 必要時，可將其設置在轉移基板6110與金屬板6206之間 或在金屬板6206之外側。該偏光板可予以事先附著至金 屬板620 6。就重量降低而言，較佳地使用薄且具有尺寸穩 定性之基板做爲金屬板6206。 之後，自將被分離之層6116而分離臨時支撐基板 62 02。因爲用於分離之黏著劑620 3包含能在當需要時彼 此相互分離臨時支撐基板6202與將被分離之層6116的材 料，所以該臨時支撐基板6202可藉由適用於該材料之方 法而予以分離。注意的是，光係如圖式中之箭頭所示地自 背光而發射出（請參閱第23E圖）。 因此，包含諸如電晶體及像素電極之元件的將被分離 之層6】.1 6 (視需要地，亦可設置相對電極、遮光膜、配向 膜、或其類似物）可形成於轉移基板6110上，而具有高 的抗衝擊性之輕便的元件基板可藉以形成。 〈修正實例〉 具有上述結構之液晶顯示裝置係本發明之一實施例， 且本發明亦包含具有與上述液晶顯示裝置的結構不同之結 構的液晶顯示裝置。在上述轉移處理（第23B圖）之後， -95- 201220292 可在轉移基板6110的附著之前，將金屬板62 06附著至分 離層6201或將被分離之層6116的暴露表面（見第23C，圖 )。在該情況中’阻隔層6207係較佳地設置於金屬板 62 0 6與將被分離之層6116之間，使得可防止來自金屬板 6206之污染物不利地影響到將被分離之層6116中之電晶 體的特徵。在提供該阻隔層6 2 0 7的情況中，該阻隔層 6207可在金屬板6206的附著之前被設置鄰接於分離層 6201或將被分離之層6116的暴露表面。該阻隔層6207可 使用無機材料，有機材料，或其類似物而形成；典型地， 可使用氮化矽或其類似物。阻隔層之材料並未受限於上文 。只要可防止電晶體之污染即可。該阻隔層係使用透光材 料而形成，或係形成爲小到足以透射光之厚度，以致使阻 隔層至少可透射可見光。金屬板6206可伴隨著第二黏著 層（未顯示）之使用而接合，該第二黏著層包含與用於分 離之黏著劑6203不同的黏著劑。 之後，將第一黏著層6111形成爲鄰接於金屬板62 06 的表面，且將轉移基板6110附著至第一黏著層6111 (第 23 D’圖），以及將臨時支撐基板6202分離自將被分離之 層6116(第23E’圖），而具有高的抗衝擊性之輕便的元 件基板可藉以形成。注意的是，光係如圖式中之箭頭所示 地自背光而發射出。 如上述所形成之具有高的抗衝擊性之輕便的元件基板 係使用密封劑而牢固地附著至相對基板，且液晶層係設置 於該等基板之間，而可藉以製造出具有高的抗衝擊性之輕 -96--94 - S 201220292 A metal plate 6206 in the figure, and the metal plate 6206 has a hole formed in a grid so as to leave a portion overlapping the first wiring layer 6210 and/or the second wiring layer 6211. The adhesion of the metal plate 6206 as shown in Fig. 24C can suppress the dimensional change caused by the unsuitable alignment of the substrate made of the organic resin or the expansion and contraction of the substrate. When a polarizing plate (not shown) is necessary, it may be disposed between the transfer substrate 6110 and the metal plate 6206 or on the outer side of the metal plate 6206. The polarizing plate can be attached to the metal plate 620 6 in advance. In terms of weight reduction, a substrate having a thin and dimensional stability is preferably used as the metal plate 6206. Thereafter, the temporary support substrate 62 02 is separated from the layer 6116 to be separated. Since the adhesive 620 3 for separation contains materials capable of temporarily supporting the substrate 6202 and the layer 6116 to be separated when separated from each other as needed, the temporary support substrate 6202 can be separated by a method suitable for the material. . Note that the light system is emitted from the backlight as indicated by the arrow in the figure (see Figure 23E). Therefore, the layer 6 to be separated including the elements such as the transistor and the pixel electrode may be formed on the transfer substrate 6110 (optionally, an opposite electrode, a light shielding film, an alignment film, or the like) may be formed. Above, a lightweight component substrate having high impact resistance can be formed. <Modification Example> A liquid crystal display device having the above configuration is an embodiment of the present invention, and the present invention also includes a liquid crystal display device having a structure different from that of the above liquid crystal display device. After the above transfer process (Fig. 23B), -95-201220292 may attach the metal plate 62 06 to the separation layer 6201 or the exposed surface of the layer 6116 to be separated before the attachment of the transfer substrate 6110 (see Fig. 23C, Fig. 23C) ). In this case, the barrier layer 6207 is preferably disposed between the metal plate 62 0 6 and the layer 6116 to be separated, so that contaminants from the metal plate 6206 can be prevented from adversely affecting the layer 6116 to be separated. The characteristics of the transistor. In the case where the barrier layer 6 2 0 7 is provided, the barrier layer 6207 may be disposed adjacent to the separation layer 6201 or the exposed surface of the layer 6116 to be separated before the attachment of the metal plate 6206. The barrier layer 6207 can be formed using an inorganic material, an organic material, or the like; typically, tantalum nitride or the like can be used. The material of the barrier layer is not limited to the above. As long as the contamination of the transistor can be prevented. The barrier layer is formed using a light transmissive material or is formed to a thickness small enough to transmit light such that the barrier layer transmits at least visible light. The metal plate 6206 can be joined with the use of a second adhesive layer (not shown) containing an adhesive different from the adhesive 6203 used for separation. Thereafter, the first adhesive layer 6111 is formed to be adjacent to the surface of the metal plate 62 06, and the transfer substrate 6110 is attached to the first adhesive layer 6111 (Fig. 23D'), and the temporary support substrate 6202 is separated from being separated. The layer 6116 (Fig. 23E') can be formed by a lightweight component substrate having high impact resistance. Note that the light system is emitted from the backlight as indicated by the arrow in the figure. The lightweight component substrate having high impact resistance formed as described above is firmly adhered to the opposite substrate using a sealant, and the liquid crystal layer is disposed between the substrates, whereby a high impact resistance can be produced. Slightness -96-

S 201220292 便的液晶顯示裝置。做爲該相對基板，可使用具有高的韌 性且可透射可見光之基板（與可使用做爲轉移基板6110 之塑膠基板相似）。進一步地，可視需要地設置偏光板、 遮光膜、相對電極、或配向膜。做爲用以形成液晶層之方 法，可如習知情況中似地使用點膠法、注入法、或其類似 方法。 在如上述所製造出之具有高抗衝擊性之輕便的液晶顯 示裝置之情況中，可將諸如電晶體之精密元件形成於具有 相對高的尺寸穩定性之玻璃基板或其類似物上，且可施加 習知之製造方法，以致使甚至該精密元件亦可被精確地形 成。因此，具有高的抗衝擊性之輕便的液晶顯示裝置可以 以高的精確度及高的品質而顯示影像。 進一步地，如上述所製造出之液晶顯示裝置可係撓性 的。 此實施例可與上述該等實施例之任一者適當地結合。 (實施例6) 接著，將參照第26A及26B圖來敘述本發明之一實施 例的液晶顯示裝置。第26A圖係面板的頂部視圖，其中基 板4001係以密封劑4005而附著至相對基板4006 ;以及第 26B圖係沿著第26A圖中之點線A-A’的橫剖面視圖。 密封劑4 0 0 5係提供以便包圍設置在基板4 0 0 1上的像 素部4002及掃描線驅動器電路4004。此外，相對基板 4006係設置於像素部4002及掃描線驅動器電路4004之上 -97- 201220292 。因此，該像素部4002及掃描線驅動器電路4004係藉由 基板4001、密封劑4005、及相對基板4006，而與液晶 4007 —起被密封。 設置有信號線驅動器電路4003之基板4021係安裝於 基板4001上之與藉由密封劑4005所包圍之區域不同的區 域中。在第26B圖中，係描繪包含於信號線驅動器電路 4003中之電晶體4009。 複數個電晶體係包含於設置在基板400 1上的像素部 4002及掃描線驅動器電路4004之中。在第26B圖中，係 描繪包含於像素部4 002之中的電晶體4010及4022。電晶 體4 010及電晶體4022各自包含氧化物半導體於通.道形成 區之中。設置用於相對基板4006之遮光膜4040係與該等 電晶體4010及4022重疊。藉由對於電晶體4010及4022 而遮斷光，可防止電晶體中之氧化物半導體由於光而劣化 :因此，可防止諸如臨限電壓的偏移之電晶體4010及 4022特徵的劣化。 包含於液晶元件401 1中之像素電極4030係電性連接 至電晶體4010。該液晶元件4011的相對電極4031係設置 用於相對基板4006。其中像素電極4030，相對電極4031 ，及液晶4007彼此互相重疊的部分對應於液晶元件40 11 〇 間隔物403 5係設置要控制像素電極4030與相對電極 403 1之間的距離（胞格間隙）。第2 6B圖顯示其中該間 隔物403 5係藉由絕緣膜之圖案化而形成的情況；選擇性 -98 -S 201220292 LCD display device. As the counter substrate, a substrate having high toughness and transmitting visible light can be used (similar to a plastic substrate which can be used as the transfer substrate 6110). Further, a polarizing plate, a light shielding film, an opposite electrode, or an alignment film may be provided as needed. As a method for forming a liquid crystal layer, a dispensing method, an injection method, or the like can be used as in the conventional case. In the case of a portable liquid crystal display device having high impact resistance as manufactured as described above, a precision element such as a transistor can be formed on a glass substrate or the like having relatively high dimensional stability, and A conventional manufacturing method is applied so that even the precision element can be accurately formed. Therefore, a portable liquid crystal display device having high impact resistance can display images with high precision and high quality. Further, the liquid crystal display device manufactured as described above can be flexible. This embodiment can be combined as appropriate with any of the above-described embodiments. (Embodiment 6) Next, a liquid crystal display device according to an embodiment of the present invention will be described with reference to Figs. 26A and 26B. Fig. 26A is a top view of the panel in which the substrate 4001 is attached to the opposite substrate 4006 with the sealant 4005; and the 26B is a cross-sectional view taken along the dotted line A-A' in Fig. 26A. A sealant 4500 is provided to surround the pixel portion 4002 and the scan line driver circuit 4004 provided on the substrate 4101. Further, the counter substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004 -97 - 201220292. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are sealed together with the liquid crystal 4007 by the substrate 4001, the encapsulant 4005, and the counter substrate 4006. The substrate 4021 provided with the signal line driver circuit 4003 is mounted on a different area of the substrate 4001 than the area surrounded by the sealant 4005. In Fig. 26B, the transistor 4009 included in the signal line driver circuit 4003 is depicted. A plurality of electro-crystal systems are included in the pixel portion 4002 and the scanning line driver circuit 4004 provided on the substrate 4001. In Fig. 26B, transistors 4010 and 4022 included in the pixel portion 4 002 are depicted. The electromorph 4 010 and the transistor 4022 each comprise an oxide semiconductor in the pass formation region. The light shielding film 4040 provided for the opposite substrate 4006 is overlapped with the transistors 4010 and 4022. By blocking the light for the transistors 4010 and 4022, it is possible to prevent the oxide semiconductor in the transistor from being deteriorated by light: therefore, deterioration of the characteristics of the transistors 4010 and 4022 such as the shift of the threshold voltage can be prevented. The pixel electrode 4030 included in the liquid crystal element 401 1 is electrically connected to the transistor 4010. The opposite electrode 4031 of the liquid crystal element 4011 is provided for the opposite substrate 4006. A portion in which the pixel electrode 4030, the opposite electrode 4031, and the liquid crystal 4007 overlap each other corresponds to the liquid crystal element 40 11 〇 The spacer 403 5 is provided to control the distance (cell gap) between the pixel electrode 4030 and the opposite electrode 403 1 . Fig. 2 6B shows a case in which the spacer 4035 is formed by patterning of an insulating film; selectivity -98 -

S 201220292 地，可使用球狀間隔物。 各式各樣的信號及電位係透過引線4014及4015，而 自連接端子4016來供應至信號線驅動器電路4003、掃描 線驅動器電路4004、及像素部4002。該連接端子4016係 經由各向異性導電膜4019而電性連接至FPC 4018的端子 〇 注意的是’基板4001、相對基板4006、及基板4021 的任一者可使用玻璃、陶瓷物、或塑膠而形成。塑膠包含 纖維玻璃強化塑膠（FRP )板、聚氟乙烯（PVF )膜、聚 酯膜、丙烯酸樹脂膜、及類似物於其種類中。同樣地，可 使用具有其中鋁箔係插入於PVF膜間之結構的薄片。 注意的是’以其中光係透過液晶元件40 1 1而提取之 方向所放置的基板係使用諸如玻璃板、塑膠、聚酯膜、或 丙烯酸膜之透光材料而形成。 第27圖係描繪本發明一實施例之液晶顯示裝置的結 構之透視圖的實例。在第27圖中所描繪之液晶顯示裝置 包含面板1601、第一漫射板1 602、稜鏡片1 603、第二漫 射板16 04、光導板1605、背光面板1607、電路板1608、 及基板1611，而面板1601包含像素部以及基板1611係設 置有信號線驅動器電路。 面板1601、第一漫射板1602、稜鏡片1603、第二漫 射板16 04、光導板1605、及背光面板1607係順序地堆疊 。背光面板1 607具有包含複數個光源的背光1612。來自 背光1612而漫射於光導板1605中的光係透過第一漫射板 -99- 201220292 1 602、稜鏡片1 603、及第二漫射板1 604，而遞送至面板 1601 ° 雖然第一漫射板1 602及第二漫射板1 604係使用於此 實施例中，但漫射板的數目並未受限於二；漫射板的數目 可係一，或可係三或更多個。漫射板係設置於光導板1605 與面板1601之間。漫射板可僅設置在比稜鏡片1 603更靠 近面板1601之側，或可僅設置在比稜鏡片1 603更靠近光 導板1 605之側。 進一步地，在第27圖中所描繪之稜鏡片1 603的橫剖 面之形狀並未受限於細齒狀：該橫剖面可具有其中來自光 導板1 605的光可被聚集至面板1601側的任何形狀。 電路板1608係設置有可產生輸入至面板1601之各式 各樣信號的電路，可處理該等信號的電路，或其類似電路 。在第27圖中，電路板1608係經由COF帶1609而連接 至面板1 601。此外，設置有信號線驅動器電路之基板 1611係藉由晶片在膜上（COF)方法而連接至COF帶 1 609 » 第27圖描繪其中電路板1 608係設置有控制背光1612 之驅動的控制電路，且該控制電路係經由FPC 1610而連 接至背光面板1607。該控制電路可形成於面板1601上。 在該情況中，面板1601可經由FPC或其類似物而連接至 背光面板1 607 ^ 此實施例可與上述該等實施例之任一者適當地結合。S 201220292 Ground, spherical spacers can be used. A variety of signals and potentials are transmitted through the leads 4014 and 4015, and are supplied from the connection terminal 4016 to the signal line driver circuit 4003, the scanning line driver circuit 4004, and the pixel portion 4002. The connection terminal 4016 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. Note that any of the substrate 4001, the opposite substrate 4006, and the substrate 4021 can use glass, ceramic, or plastic. form. The plastics include fiberglass reinforced plastic (FRP) sheets, polyvinyl fluoride (PVF) films, polyester films, acrylic films, and the like. Also, a sheet having a structure in which an aluminum foil is interposed between PVF films can be used. Note that the substrate placed in the direction in which the light is extracted through the liquid crystal element 40 1 1 is formed using a light-transmitting material such as a glass plate, a plastic, a polyester film, or an acrylic film. Figure 27 is a view showing an example of a perspective view of the structure of a liquid crystal display device of an embodiment of the present invention. The liquid crystal display device depicted in FIG. 27 includes a panel 1601, a first diffusion plate 1 602, a die 1 603, a second diffusion plate 16 04, a light guide plate 1605, a backlight panel 1607, a circuit board 1608, and a substrate. 1611, the panel 1601 includes a pixel portion, and the substrate 1611 is provided with a signal line driver circuit. The panel 1601, the first diffusion plate 1602, the cymbal piece 1603, the second diffusion plate 164, the light guide plate 1605, and the backlight panel 1607 are sequentially stacked. The backlight panel 1 607 has a backlight 1612 including a plurality of light sources. The light from the backlight 1612 diffused in the light guiding plate 1605 passes through the first diffusing plate -99 - 201220292 1 602, the cymbal 1 603, and the second diffusing plate 1 604, and is delivered to the panel 1601 ° although the first The diffusing plate 1 602 and the second diffusing plate 1 604 are used in this embodiment, but the number of diffusing plates is not limited to two; the number of diffusing plates may be one, or may be three or more One. The diffusing plate is disposed between the light guiding plate 1605 and the panel 1601. The diffusing plate may be disposed only on the side closer to the face plate 1601 than the crotch panel 1 603, or may be disposed only on the side closer to the light guide plate 1 605 than the crotch panel 1 603. Further, the shape of the cross section of the crotch panel 1 603 depicted in FIG. 27 is not limited to the serration: the cross section may have light in which the light from the light guide plate 1 605 can be collected to the side of the panel 1601. Any shape. Circuit board 1608 is provided with circuitry for generating a variety of signals input to panel 1601, circuitry for processing such signals, or the like. In Fig. 27, the circuit board 1608 is connected to the panel 1 601 via the COF tape 1609. Further, the substrate 1611 provided with the signal line driver circuit is connected to the COF tape 1 609 by a wafer on-film (COF) method. FIG. 27 depicts a control circuit in which the circuit board 1 608 is provided with a drive for controlling the backlight 1612. And the control circuit is connected to the backlight panel 1607 via the FPC 1610. The control circuit can be formed on the panel 1601. In this case, the panel 1601 may be connected to the backlight panel 1 607 via an FPC or the like. This embodiment may be combined as appropriate with any of the above-described embodiments.

S -100- 201220292 (實施例7) 第25 A圖描繪像素之頂部視圖的實例。沿著第 中之鏈線A1-A2的橫剖面視圖係第25B圖。 第25A及25B圖中所描繪之像素包含：導電膜 作用成爲掃描線GL ;導電膜502，作用成爲信號縛 導電膜503 ’作用成爲佈線COM ;以及導電膜504 成爲電晶體16的第二端子。導電膜501亦作用成J 圖中所描繪之電晶體1 6的閘極電極。此外，導電 亦作用成爲電晶體1 6的第一端子。 導電膜501及導電膜5 03可藉由處理形成於具 表面之基板500上的一導電膜成爲所欲之形狀，而 成。閘極絕緣膜5 06係形成於導電膜50 1及導電膜 上。進一步地，導電膜502及導電膜504可藉由處 於該閘極絕緣膜5 06上之一導電膜成爲所欲的形狀 以形成。 電晶體16之主動層507係形成於閘極絕緣膜 ，以便與導電膜501重疊，如第25A及2δΒ圖中所 ，主動層507係較佳地與作用成爲閘極電極之導電 完全地重疊。透過該結構，在該主動層5 07中之氧 導體可防止由於來自基板5 0 0側之入射光所導致的 因此，可防止諸如臨限電壓的偏移之電晶體特 化。 進一步地，在第25A及25B圖中所描繪的像素 緣膜5 1 2及絕緣膜5 1 3係順序地形成’以便覆蓋 2 5 A圖 501， t SL ； ，作用 !第2B 膜502 有絕緣 予以形 5 03之 理形成 ，而予 5 06上 描繪地 膜501 化物半 劣化； 徵的劣 中，絕 主動層 -101 - 201220292 507、導電膜502、及導電膜5 04。此外，像素電極505係 形成於絕緣膜513上，且導電膜504係透過形成於絕緣膜 512及絕緣膜513中之接觸孔而連接至像素電極505。 其中作用成爲佈線COM之導電膜5 03與導電膜504 重疊，而閘極絕緣膜506係設置於其間之部分，作用成爲 電容器。 在此實施例中，絕緣膜5 0 8係形成於導電膜5 0 1與閘 極絕緣膜506之間。絕緣膜508係設置於導電膜501與導 電膜502之間；因而，在導電膜501與導電膜502之間所 產生的寄生電容可藉由絕緣膜508而被抑制爲更低。 在此實施例中，絕緣膜509係形成於導電膜503與閘 極絕緣膜5 06之間。此外，間隔物5 1 0係形成於像素電極 5 05之上，以便與絕緣膜509重疊。 第25 A圖係正好在間隔物5 1 0的形成步驟之後的像素 之頂部視圖。第25B圖描繪其中基板514係設置以便以第 25A圖中所描繪之狀態而面向基板5 00的狀態。 相對電極5 1 5係設置用於基板5 1 4，且包含液晶之液 晶層516係設置於像素電極505與相對電極515之間。液 晶元件1 8係形成於其中像素電極5 0 5，相對電極5 1 5，及 液晶層516彼此互相重疊的部分中。 例如，像素電極505及相對電極5 1 5可使用諸如包含 氧化矽之氧化銦錫（ITSO)、氧化銦錫（ITO )、氧化鋅 (ZnO)、氧化銦鋅（IZO)、或添加鎵之氧化鋅（GZO ) 的透光導電材料而形成。S - 100 - 201220292 (Embodiment 7) Figure 25A depicts an example of a top view of a pixel. A cross-sectional view along the center chain line A1-A2 is shown in Fig. 25B. The pixels depicted in Figs. 25A and 25B include: the conductive film functions as the scanning line GL; the conductive film 502 acts as the signal-bonding conductive film 503' to function as the wiring COM; and the conductive film 504 becomes the second terminal of the transistor 16. The conductive film 501 also acts as a gate electrode of the transistor 16 depicted in the figure J. In addition, the electrical conduction also acts as the first terminal of the transistor 16. The conductive film 501 and the conductive film 030 can be formed into a desired shape by processing a conductive film formed on the substrate 500 having the surface. A gate insulating film 506 is formed on the conductive film 50 1 and the conductive film. Further, the conductive film 502 and the conductive film 504 can be formed by forming a conductive film on the gate insulating film 506 into a desired shape. The active layer 507 of the transistor 16 is formed on the gate insulating film so as to overlap the conductive film 501. As in the 25th and 2nd Β diagrams, the active layer 507 is preferably completely overlapped with the conductive function of the gate electrode. With this structure, the oxygen conductor in the active layer 507 can be prevented from being caused by incident light from the side of the substrate 500, thereby preventing transistor characteristics such as shifting of the threshold voltage. Further, the pixel edge film 5 1 2 and the insulating film 5 1 3 depicted in FIGS. 25A and 25B are sequentially formed 'to cover the 2 5 A FIG. 501, t SL ; function! The 2B film 502 is insulated Formed according to the principle of Form 5 03, and the film 501 is semi-degraded on the film; the inferior, the active layer -101 - 201220292 507, the conductive film 502, and the conductive film 504. Further, the pixel electrode 505 is formed on the insulating film 513, and the conductive film 504 is connected to the pixel electrode 505 through a contact hole formed in the insulating film 512 and the insulating film 513. The conductive film 030 which functions as the wiring COM overlaps with the conductive film 504, and the gate insulating film 506 is disposed between the portions thereof to function as a capacitor. In this embodiment, an insulating film 508 is formed between the conductive film 510 and the gate insulating film 506. The insulating film 508 is disposed between the conductive film 501 and the conductive film 502; therefore, the parasitic capacitance generated between the conductive film 501 and the conductive film 502 can be suppressed to be lower by the insulating film 508. In this embodiment, an insulating film 509 is formed between the conductive film 503 and the gate insulating film 506. Further, a spacer 5 10 is formed over the pixel electrode 505 so as to overlap the insulating film 509. Figure 25A is a top view of the pixel just after the formation step of spacer 50. Fig. 25B depicts a state in which the substrate 514 is disposed so as to face the substrate 500 in the state depicted in Fig. 25A. The opposite electrode 5 15 is provided for the substrate 516, and the liquid crystal layer 516 containing liquid crystal is disposed between the pixel electrode 505 and the opposite electrode 515. The liquid crystal element 18 is formed in a portion in which the pixel electrode 505, the opposite electrode 515, and the liquid crystal layer 516 overlap each other. For example, the pixel electrode 505 and the opposite electrode 5 15 may be oxidized using, for example, indium tin oxide (ITSO), indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), or gallium added containing yttrium oxide. Zinc (GZO) is formed by a light-transmitting conductive material.

-102- S 201220292 配向膜可適當地設置於像素電極5 05與液晶層5 1 6之 間及/或相對電極51 5與液晶層516之間。配向膜可使用 諸如聚醯乙胺或聚乙烯醇之有機樹脂而形成。諸如擦拭之 配向處理係執行於配向膜的表面上。以便以一定方向而配 向液晶分子。擦拭可藉由滾動纏繞有尼龍或其類似物之布 的滾筒，且同時與配向膜接觸而執行，以致使配向膜之表 面被以一定方向而擦拭。注意的是，亦可使用諸如氧化矽 之無機材料，藉由蒸鍍法或其類似方法以形成具有配向特 _徵的配向膜，而無需配向處理。 用以形成液晶層5 1 6之液晶可藉由點膠法（滴注法） 或浸漬法（抽運法）而予以注入。 在基板5 1 4之上，爲j要防止由於像素間之液晶配向 的無序所造成之錯向被感知，或爲了要防止漫射光進入複 數個鄰接像素之內，係設置能遮斷光線之遮光膜517。遮 光膜5 1 7可使用包含諸如碳黑或低鈦氧化物之黑色著色劑 的有機樹脂所形成，而該低鈦氧化物之氧化數目係小於二 氧化鈦之氧化數目。選擇性地，該遮光膜517可以以使用 鉻所形成之膜而形成。 藉由提供遮光膜517以便與電晶體16之主動層507 重疊，可防止主動層5 07中之氧化物半導體由於來自基板 5 1 4側之入射光而劣化；因此，可防止諸如臨限電壓的偏 移之電晶體1 6特徵的劣化。 雖然其中液晶層5 1 6係設置於像素電極505與相對電 極515之間的液晶元件18係描繪於第25A及25B圖中做 -103- 201220292 爲實例，但本發明一實施例之液晶顯示裝置的結構並未受 限於此結構。電極之對可如在ips液晶元件或在使用顯現 藍色相之液晶的液晶元件之中似地，形成於一基板上。 注意的是，在形成驅動器電路於其中形成面板於其上 的基板上之情況中，藉由設置閘極電極或遮光膜以便對驅 動器電路中之電晶體遮斷光，亦可防止諸如臨限電壓的轉 移之電晶體特徵的劣化。 爲了要更確實地防止光進入主動層507，可設置遮光 導電膜以便與主動層507重疊。在第32A及32B圖中，遮 光導電膜5 3 0係設置以與第25A及25B圖中所示的像素中 之主動層507重疊。第32A圖係像素的頂部視圖，且沿著 第32A圖中之鏈線A1_A2的橫剖面視圖係第32B圖。 具體而言，在第32A及32B圖之中，絕緣膜531係設 置於絕緣膜512上，且導電膜530係形成於該絕緣膜531 之上。絕緣膜5 1 3係.形成於絕緣膜5 3 1之上，以便覆蓋導 電膜5 3 0。 主動層5 07與導電膜502及504係部分地重疊；因此 ，該主動層507具有其中係藉由導電膜502或導電膜5 04 所覆蓋之部分，以及其中並未透過導電膜502及5 04而覆 蓋之暴露部分。在第32A及32B圖之中，導電膜530係設 置以便與其中並未透過導電膜5 02及5 04而覆蓋之暴露部 分相重曼。 透過導電膜530，可防止主動層507中之氧化物半導 體由於來自基板514側之入射光而劣化；因此，可防止諸-102- S 201220292 The alignment film may be suitably disposed between the pixel electrode 505 and the liquid crystal layer 5 16 and/or between the opposite electrode 515 and the liquid crystal layer 516. The alignment film can be formed using an organic resin such as polyethylamine or polyvinyl alcohol. An alignment treatment such as wiping is performed on the surface of the alignment film. In order to align liquid crystal molecules in a certain direction. Wiping can be performed by rolling a roller wound with a cloth of nylon or the like and simultaneously contacting the alignment film so that the surface of the alignment film is wiped in a certain direction. Note that an inorganic material such as yttria may also be used, by an evaporation method or the like to form an alignment film having an alignment characteristic without an alignment treatment. The liquid crystal for forming the liquid crystal layer 516 can be injected by a dispensing method (drip method) or a dipping method (pumping method). Above the substrate 5 1 4, j is to prevent the erroneous direction caused by the disorder of the liquid crystal alignment between the pixels from being perceived, or to prevent the diffused light from entering the plurality of adjacent pixels, and is arranged to block the light. Light shielding film 517. The light-shielding film 51 may be formed using an organic resin containing a black colorant such as carbon black or low titanium oxide, and the number of oxidation of the low-titanium oxide is less than the number of oxidation of titanium oxide. Alternatively, the light shielding film 517 may be formed using a film formed of chromium. By providing the light shielding film 517 so as to overlap with the active layer 507 of the transistor 16, the oxide semiconductor in the active layer 507 can be prevented from being deteriorated due to incident light from the side of the substrate 5 14; therefore, for example, a threshold voltage can be prevented. Degradation of the characteristics of the offset transistor 16. The liquid crystal element 18 in which the liquid crystal layer 516 is disposed between the pixel electrode 505 and the opposite electrode 515 is depicted in FIGS. 25A and 25B as an example of -103-201220292, but the liquid crystal display device of one embodiment of the present invention is used. The structure is not limited to this structure. The pair of electrodes may be formed on a substrate as in an ips liquid crystal cell or a liquid crystal cell using a liquid crystal exhibiting a blue phase. Note that in the case where the driver circuit is formed on the substrate on which the panel is formed, by providing a gate electrode or a light shielding film to block the transistor in the driver circuit, it is also possible to prevent a voltage such as threshold voltage. The degradation of the characteristics of the transferred transistor. In order to more surely prevent light from entering the active layer 507, a light-shielding conductive film may be provided to overlap the active layer 507. In Figs. 32A and 32B, the light-shielding conductive film 530 is disposed to overlap the active layer 507 in the pixel shown in Figs. 25A and 25B. Fig. 32A is a top view of the pixel, and a cross-sectional view along the chain line A1_A2 in Fig. 32A is a 32B diagram. Specifically, in the 32A and 32B drawings, the insulating film 531 is placed on the insulating film 512, and the conductive film 530 is formed on the insulating film 531. An insulating film 5 1 3 is formed over the insulating film 531 to cover the conductive film 530. The active layer 507 partially overlaps with the conductive films 502 and 504; therefore, the active layer 507 has a portion covered by the conductive film 502 or the conductive film 504, and the conductive film 502 and 504 are not transmitted therein. And cover the exposed part. In the 32A and 32B drawings, the conductive film 530 is disposed so as to be heavier than the exposed portion which is not covered by the conductive films 502 and 504. The conductive film 530 is prevented from deteriorating the oxide semiconductor in the active layer 507 due to incident light from the side of the substrate 514; therefore, it is possible to prevent

S -104- 201220292 如臨限電壓的偏移之電晶體1 6特徵的劣化。 導電膜53 0可在浮動狀態中，亦即，被電性絕緣；或 可在被施加以電位的狀態中。 此實施例可與上述該等實施例的任一者適當地結合。 (實施例8 ) 在實施例8中，電晶體95 1係使用另一實施例中所述 之製造方法而製造，具有背面閘極電極的電晶體952被製 造出’且透過以光照射在該等電晶體上的負偏壓應力測試 之臨限電壓（Vth )改變數量的評估結果將予以敘述。 首先，參照第29A圖所敘述的係電晶體95 1之堆疊層 結構及其製造方法。在基板900上，氮化矽膜（.厚度： 200奈米）及氮氧化矽膜（厚度：40 0奈米）之堆疊層膜 係藉由CVD法而形成爲基底膜936。其次，在基底膜936 上’氮化鉅膜（厚度：30奈米）及鎢膜（厚度：100奈米 )之堆疊層膜係藉由濺鍍法而形成，且被選擇性地蝕刻而 形成閘極電極9 0 1。 接著，在閘極電極901上，氮氧化矽膜（厚度：30奈 米）係藉由高密度電漿增強型CVD法而形成爲閘極絕緣 膜 902。 其次，在閘極絕緣膜902上，氧化物半導體膜（厚度 :30奈米）係使用In-Ga-Ζη-Ο爲主氧化物半導體之靶極 ’而藉由源鍍法所形成。然後，該氧化物半導體膜被選擇 性地蝕刻’而形成島狀氧化物半導體膜903。 -105- 201220292 接著，在氮氛圍之下，執行第一熱處理於4 50°C，60 分鐘。 其次，在氧化物半導體膜903上，鈦膜（厚度：100 奈米）、鋁膜（厚度：2〇〇奈米）、及鈦膜（厚度：100 奈米）之堆疊層膜係藉由濺鍍法而形成，且被選擇性地蝕 刻以形成源極電極905a及汲極電極905b。 接著，在氮氛圍之下，執行第二熱處理於3 00 °C，60 分鐘。 其次，在源極電極905a及汲極電極905b上，氧化矽 膜係藉由濺渡法而形成爲絕緣膜907，以便與氧化物半導 體膜903的一部分接觸，且在絕緣膜907上，聚醯乙胺樹 脂膜（厚度：1.5微米）係形成爲絕緣膜908。 接著，在氮氛圍之下，執行第三熱處理於2 50 °C，60 分鐘。 其次，在絕緣膜9 08上，聚醯乙胺樹脂膜（厚度： 2.0微米）係形成爲絕緣膜909。 接著，在氮氛圍之下，執行第四熱處理於25 0°C，60 分鐘。 第29B圖中所示的電晶體952可以以與電晶體951之 方式相似的方式而製造。電晶體952係與電晶體95 1不同 ，其中背面閘極電極9 1 2係設置於絕緣膜908及909之間 。該背面閘極電極912係如下地形成：鈦膜（厚度：1 00 奈米）、鋁膜（厚度：200奈米）、及鈦膜（厚度：1〇〇 奈米）之堆疊層膜係藉由濺鍍法而形成於絕緣膜9 08上，S -104- 201220292 Degradation of the characteristics of the transistor 16 such as the offset voltage. The conductive film 530 may be electrically insulated in a floating state, that is, in a state in which a potential is applied. This embodiment can be combined as appropriate with any of the above-described embodiments. (Embodiment 8) In Embodiment 8, the transistor 95 1 is manufactured using the manufacturing method described in another embodiment, and the transistor 952 having the back gate electrode is fabricated and transmitted through the light. The evaluation results of the threshold voltage (Vth) change of the negative bias stress test on the isoelectric crystal will be described. First, the stacked layer structure of the system transistor 95 1 described with reference to Fig. 29A and a method of manufacturing the same are described. On the substrate 900, a stacked film of a tantalum nitride film (. thickness: 200 nm) and a hafnium oxynitride film (thickness: 40 nm) was formed into a base film 936 by a CVD method. Next, a stacked film of a nitride film (thickness: 30 nm) and a tungsten film (thickness: 100 nm) on the base film 936 is formed by sputtering, and is selectively etched to form Gate electrode 9 0 1 . Next, on the gate electrode 901, a hafnium oxynitride film (thickness: 30 nm) is formed as a gate insulating film 902 by a high-density plasma enhanced CVD method. Next, on the gate insulating film 902, an oxide semiconductor film (thickness: 30 nm) is formed by source plating using In-Ga-Ζη-Ο as the target electrode of the main oxide semiconductor. Then, the oxide semiconductor film is selectively etched to form an island-shaped oxide semiconductor film 903. -105- 201220292 Next, under a nitrogen atmosphere, a first heat treatment was performed at 405 ° C for 60 minutes. Next, on the oxide semiconductor film 903, a stacked film of a titanium film (thickness: 100 nm), an aluminum film (thickness: 2 Å nanometer), and a titanium film (thickness: 100 nm) is spattered. It is formed by plating and selectively etched to form source electrode 905a and drain electrode 905b. Next, under a nitrogen atmosphere, a second heat treatment was performed at 300 ° C for 60 minutes. Next, on the source electrode 905a and the drain electrode 905b, the ruthenium oxide film is formed as an insulating film 907 by a sputtering method so as to be in contact with a part of the oxide semiconductor film 903, and on the insulating film 907, on the insulating film 907. An ethylamine resin film (thickness: 1.5 μm) was formed as an insulating film 908. Next, under a nitrogen atmosphere, a third heat treatment was performed at 2 50 ° C for 60 minutes. Next, on the insulating film 908, a polyethylene glycol resin film (thickness: 2.0 μm) was formed as an insulating film 909. Next, under a nitrogen atmosphere, a fourth heat treatment was performed at 25 ° C for 60 minutes. The transistor 952 shown in Fig. 29B can be fabricated in a manner similar to that of the transistor 951. The transistor 952 is different from the transistor 95 1 in that a back gate electrode 9 1 2 is provided between the insulating films 908 and 909. The back gate electrode 912 is formed by a titanium film (thickness: 100 nm), an aluminum film (thickness: 200 nm), and a stacked film of a titanium film (thickness: 1 nanometer). Formed on the insulating film 908 by sputtering,

S -106- 201220292 且被選擇性地蝕刻。背面閘極電極9 1 2係 電極905a。 在電晶體951及952之每一者中，通 ，且通道寬度係20微米。 接著所敘述的係在電晶體95 1及952 光照射的負偏壓應力測試。 透過光照射之負偏壓應力測試係一種 在短週期時間中透過光照射而評估電晶體 尤其，透過以光照射的負偏壓應力測試之 Vth的改變數量係用於可靠度重要基準。 負偏壓應力測試之電晶體臨限電壓Vth的 則電晶體的可靠度愈高。透過以光照射的 之改變數量係較佳地小於或等於1伏特（ 於或等於0.5伏特（V)。 具體而言，依據以光照射的負偏壓應 來照射電晶體時之同時，設置有電晶體之 板溫度）係保持於固定溫度，電晶體之源 極係設定於相同的電位，以及電晶體之閘 源極電極及汲極電極之電位的電位而被施 〇 以光照射的負偏壓應力測試之應力強 情形，基板溫度，所施加至閘極絕緣膜之 及施加電場的時間，而予以決定。所施加 電場的強度係依據藉由以該閘極絕緣膜的 電性連接至源極 道長度係3微米 上所執行之透過 加速測試，且可 之特徵的改變。 電晶體臨限電壓 透過以光照射的 改變數量愈小， 負偏壓應力測試 V )，更佳地小 力測試，當以光 基板的溫度（基 極電極及汲極電 極電極係以低於 加以一定之週期 度可依據光照射 電場的強度，以 至閘極絕緣膜之 厚度來畫分閘極 -107- 201220292 電極與源極及汲極電極間之電位差所獲得的値，而予以決 定。例如，在其中所施加至具有1 00奈米之厚度的閘極絕 緣膜之電場的強度將成爲2MV/cm的情況中，可將電位差 設定爲20伏特。 其中將高於源極電極及汲極電極之電位的電位施加至 光照射下之閘極電極的測試稱爲以光照射之正偏壓應力測 試。透過以光照射之負偏壓應力測試，電晶體的特徵會比 透過以光照射之正偏壓應力測試更可能改變，且因此，在 此實施例中採用以光照射之負偏壓應力測試。 在此實施例中之以光照射之負偏壓應力測試係以以下 情形而執行：基板溫度係室溫（25 °C )，所施加至閘極絕 緣膜902之電場強度係2MV/cm，以及光照射及電場施加 之週期係1小時。光照射之情形係如下：使用 Asahi Spectra Co.，Ltd.所製造之氙氣燈源“MAX-302”，而峰値 波長爲400奈米（半波長寬度：10奈米），且輻照度係 3 26pW/cm2 〇 在以光照射之負偏壓應力測試之前，測量各個電晶體 的初始特徵。在此實施例中所測量的係Vg-Id特徵，亦即 ，在以下情形之下所流動於源極電極與汲極電極間之電流 (在下文中，該電流係稱爲汲極電流或Id)的改變特徵： 基板溫度係室溫（25 °C )，源極電極與汲極電極之間的電 壓（在下文中，該電壓係稱爲汲極電壓或Vd)係3伏特 ，以及源極電極與間極電極之間的電壓（在下文中，該電 壓係稱爲閘極電壓或Vg)係自-5伏特而改變至+5伏特。 -108- 201220292 接著，起動光照射於絕緣膜909側，設定電晶體之源 極及汲極電極的各自電位成爲0伏特，且將負電壓施加至 閘極電極90 1，以致使所施加至電晶體之閘極絕緣膜902 的電場強度變成2MV/cm。在此實施例中，電晶體之閘極 絕緣膜902的厚度係30奈米，且因此，-6伏特被施加至 閘極電極901，且維持1小時。在此實施例中之電壓施加 的時間係1小時；然而，該時間可依據目的而適當地決定 〇 接著，於保持光照射的同時，結束電壓施加，而在與 初始特徵之測量相同的情形下測量Vg-Id特徵，以致可獲 得在以光照射之負偏壓應力測試之後的Vg-Id特徵。 在此實施例中之臨限電壓Vth係使用第30圖而界定 於下文。在第3 0圖中，水平軸表示在線性標度上之閘極 電壓，以及垂直軸表示在線性標度上之汲極電流的平方根 (在下文中亦稱作#)。曲線921指示Vg-Id特徵中之 Vth的値的平方裉（在下文中，該曲線亦稱爲#曲線）。 首先，#曲線（曲線921 )係自Vg-Id曲線而獲得。 接著，取得相對於#曲線上之λ/反曲線的微分値係最大値 的點之切線924。然後’延長該切線924，且界定該切線 924上之在0安培（A)的汲極電流Id處之閘極電壓Vg， 也就是說，在水平軸截段，亦即，該切線924之閘極電壓 軸截段925處之値爲Vth。 第3 1 A至3 1 C圖顯示在以光照射之負偏壓應力測試之 前及之後的電晶體951及952之Vg-Id特徵。在第31A及 -109- 201220292 31B圖的每一圖中，水平軸表示閘極電壓（Vg)，以及垂 直軸係以對數標度來表示相對於該閘極電壓的汲極電流（ Id ) ° 第3 1 A圖顯示在以光照射之負偏壓應力測試之前及之 後的電晶體951之Vg-Id特徵。初始特徵931係在接受以 光照射之負偏壓應力測試之前的電晶體951之Vg-Id特徵 ’以及後測試特徵9 3 2係在接受以光照射之負偏壓應力測 試之後的電晶體951之Vg-Id特徵。該初始特徵931的臨 限電壓Vth係1.01伏特’以及該後測試特徵93 2的臨限 電壓Vth係0.44伏特。 第31B圖顯示在以光照射之負偏壓應力測試之前及之 後的電晶體952之Vg-Id特徵。第31C圖係第31B圖中之 部分9 4 5的放大圖形。初始特徵9 4 1係在接受以光照射之 負偏壓應力測試之前的電晶體952之Vg-Id特徵，以及後 測試特徵942係在接受以光照射之負偏壓應力測試之後的 電晶體952之Vg-Id特徵。該初始特徵941的臨限電壓 Vth係1.16伏特，以及該後測試特徵942的臨限電壓Vth 係1 · 1 0伏特。因爲電晶體9 5 2之背面閘極電極9 1 2係電 性連接至源極電極905a，所以背面閘極電極912的電位等 於源極電極905a的電位。 在第31A圖中，後測試特徵93 2的臨限電壓Vth係以 依初始特徵93 1的臨限電壓Vth之負方向而改變0.57伏 特：以及在第31B圖中，後測試特徵942的臨限電壓Vth 係以依初始特徵941的臨限電壓Vth之負方向而改變0.06S -106- 201220292 and is selectively etched. The back gate electrode 9 1 2 is an electrode 905a. In each of the transistors 951 and 952, the channel width is 20 microns. Next, the negative bias stress test of the light irradiation of the transistors 95 1 and 952 is described. The negative bias stress test by light irradiation is an evaluation of the number of changes in Vth through the light irradiation in a short cycle time, especially through the negative bias stress test by light, which is used as an important reference for reliability. The reliability of the transistor is higher for the transistor threshold voltage Vth of the negative bias stress test. The amount of change by irradiation with light is preferably less than or equal to 1 volt (at or equal to 0.5 volts (V). Specifically, depending on the negative bias applied by light, the transistor should be irradiated while being provided with The plate temperature of the transistor is maintained at a fixed temperature, the source of the transistor is set at the same potential, and the potential of the potential of the gate electrode and the gate electrode of the transistor is applied to the negative bias of the light. The stress in the compressive stress test, the substrate temperature, the time applied to the gate insulating film, and the time during which the electric field is applied are determined. The strength of the applied electric field is based on a transmission acceleration test performed by electrically connecting the gate insulating film to the source track length of 3 μm, and the characteristics can be changed. The transistor threshold voltage is transmitted through the light, the smaller the change, the negative bias stress test V), and the better the small force test, when the temperature of the light substrate (the base electrode and the drain electrode are lower than The certain period of time can be determined according to the intensity of the light-irradiating electric field and the thickness of the gate insulating film to draw the enthalpy obtained by the potential difference between the electrode and the source and the drain electrode. For example, In the case where the intensity of the electric field applied to the gate insulating film having a thickness of 100 nm is 2 MV/cm, the potential difference can be set to 20 volts, which will be higher than the source electrode and the drain electrode. The test of the potential of the potential applied to the gate electrode under the illumination of light is called the positive bias stress test by light irradiation. Through the negative bias stress test by light irradiation, the characteristics of the transistor will be more positive than the transmission by the light. The compressive stress test is more likely to change, and therefore, a negative bias stress test by light irradiation is employed in this embodiment. The negative bias stress test by light irradiation in this embodiment is as follows. Execution: The substrate temperature is room temperature (25 ° C), the electric field strength applied to the gate insulating film 902 is 2 MV/cm, and the period of light irradiation and electric field application is 1 hour. The case of light irradiation is as follows: using Asahi A xenon lamp source "MAX-302" manufactured by Spectra Co., Ltd., and a peak wavelength of 400 nm (half wavelength width: 10 nm), and an irradiance of 3 26 pW/cm 2 〇 is irradiated with light. Prior to the negative bias stress test, the initial characteristics of the individual transistors were measured. The Vg-Id characteristics measured in this example, that is, the current flowing between the source electrode and the drain electrode under the following conditions (In the following, the current is called the drain current or Id). The substrate temperature is room temperature (25 °C), the voltage between the source electrode and the drain electrode (hereinafter, the voltage is called The drain voltage or Vd) is 3 volts, and the voltage between the source electrode and the interpole electrode (hereinafter, this voltage is referred to as the gate voltage or Vg) is changed from -5 volts to +5 volts. 108- 201220292 Next, the starting light is irradiated on the side of the insulating film 909, and the electro-crystal is set. The respective potentials of the source and the drain electrodes become 0 volt, and a negative voltage is applied to the gate electrode 90 1, so that the electric field intensity of the gate insulating film 902 applied to the transistor becomes 2 MV/cm. In the example, the thickness of the gate insulating film 902 of the transistor is 30 nm, and therefore, -6 volts is applied to the gate electrode 901 for 1 hour. The voltage applied in this embodiment is 1 hour. However, the time can be appropriately determined depending on the purpose, and then the voltage application is ended while maintaining the light irradiation, and the Vg-Id characteristic is measured under the same conditions as the measurement of the initial feature, so that the light can be obtained. Vg-Id characteristics after the negative bias stress test. The threshold voltage Vth in this embodiment is defined below using Fig. 30. In Fig. 30, the horizontal axis represents the gate voltage on the linear scale, and the vertical axis represents the square root of the drain current on the linear scale (hereinafter also referred to as #). Curve 921 indicates the squared 値 of 値 of Vth in the Vg-Id feature (hereinafter, the curve is also referred to as #curve). First, the #curve (curve 921) is obtained from the Vg-Id curve. Next, a tangent 924 to the point of the maximum 値 of the differential 値 system of the λ/reverse curve on the #curve is obtained. Then, the tangent 924 is extended and the gate voltage Vg at the threshold current Id at 0 amps (A) on the tangent 924 is defined, that is, in the horizontal axis section, that is, the gate of the tangent 924 The 电压 at the pole voltage axis section 925 is Vth. The 3 1 A to 3 1 C graph shows the Vg-Id characteristics of the transistors 951 and 952 before and after the negative bias stress test by light irradiation. In each of the figures 31A and -109-201220292 31B, the horizontal axis represents the gate voltage (Vg), and the vertical axis represents the gate current (Id) relative to the gate voltage on a logarithmic scale. Figure 31A shows the Vg-Id characteristics of the transistor 951 before and after the negative bias stress test with light illumination. The initial feature 931 is the Vg-Id characteristic ' of the transistor 951 before receiving the negative bias stress test by light irradiation, and the post-test feature 9 3 2 is the transistor 951 after receiving the negative bias stress test by light irradiation. The Vg-Id feature. The threshold voltage Vth of the initial feature 931 is 1.01 volts' and the threshold voltage Vth of the post-test feature 93 2 is 0.44 volts. Figure 31B shows the Vg-Id characteristics of the transistor 952 before and after the negative bias stress test with light illumination. Fig. 31C is an enlarged view of a portion 945 of Fig. 31B. The initial feature 94 is the Vg-Id characteristic of the transistor 952 prior to receiving the negative bias stress test with light illumination, and the post test feature 942 is the transistor 952 after receiving the negative bias stress test with light illumination. The Vg-Id feature. The threshold voltage Vth of the initial feature 941 is 1.16 volts, and the threshold voltage Vth of the post test feature 942 is 1 · 10 volts. Since the back gate electrode 9 1 2 of the transistor 905 is electrically connected to the source electrode 905a, the potential of the back gate electrode 912 is equal to the potential of the source electrode 905a. In Fig. 31A, the threshold voltage Vth of the post-test feature 93 2 is varied by 0.57 volts in the negative direction of the threshold voltage Vth of the initial feature 93 1 : and in the 31B, the threshold of the post-test feature 942 The voltage Vth is changed by 0.06 in the negative direction of the threshold voltage Vth of the initial characteristic 941.

-110- S 201220292 伏特。電晶體951及電晶體952的任一者之改變量均小於 1伏特，而可藉以確認的是，該等電晶體二者均具有高的 可靠度。此外，因爲設置有背面閘極912之電晶體952的 臨限電壓Vth之改變量係小於0· 1伏特，所以可確認的是 ，電晶體952具有比電晶體951更高的可靠度。 (實例1 ) 具備本發明一實施例之液晶顯示裝置，可提供能顯示 高品質影像的電子裝置。具備本發明一實施例之液晶顯示 裝置，可提供具有低功率消耗的電子裝置》尤其，在不易 恆定供應功率之行動電子裝置中.，被包含成爲組件之本發 明一實施例的液晶顯示裝置在連續使用時間中提供了增加 之優點* 本發明一實施例之液晶顯示裝置可使顯示裝置，膝上 型個人電腦，或設置有記錄媒體的影像再生裝置（典型地 ，可再生諸如數位多功能碟片（DVD )之記錄媒體的內容 ，且具有用以顯示再生之影像的顯示器之裝置）》除了上 述實例之外’做爲可包含本發明一實施例之液晶顯示裝置 的電子裝置，可給定以下：行動電話，攜帶式遊戲機，攜 帶式資訊終端機’電子書閱讀器，諸如攝影機或數位相機 之相機’眼鏡型顯示器（頭戴式顯示器），導航系統，聲 頻再生裝置（例如’汽車音響組件及數位聲頻播放器）， 拷貝機，傳真機，印刷機，多功能印刷機，自動櫃員機（ ATM )，販賣機，及其類似物。該等電子裝置的具體實例 -111 - 201220292 係顯示於第28A至28F圖之中。 第28A圖描繪電子書閱讀器，包含外殼7001、顯示 部7 002、及其類似物。本發明一實施例之液晶顯示裝置可 使用於顯示部7002。透過所施加至顯示部7〇〇2之本發明 —實施例的液晶顯示裝置，可提供能顯示高品質影像的電 子書閱讀器或具有低功率消耗的電子書閱讀器。此外，面 板，可使用撓性基板而形成且觸控面板可係撓性的，而液 晶顯示裝置可藉以具有撓性，其使撓性、輕便、及易於使 用之電子書閱讀器能被提供。 第28B圖描繪顯示裝置，包含外殼 7011、顯示部 70 1 2、支架70 1 3、及其類似物。本發明一實施例之液晶顯 示裝置可使用於顯示部7012。透過所施加至顯示部7012 之本發明一實施例的液晶顯示裝置，可提供能顯示高品質 影像的顯示裝置或具有低功率消耗的顯示裝置。在其種類 中，該顯示裝置包含用於個人電腦、電視（TV)廣播接收 、廣告、及其類似者之任何資訊顯示裝置。 第28C圖描繪自動櫃員機，包含外殼7 02 1、顯示部 7022、硬幣槽7023、紙幣槽7024、卡片槽7025、存摺槽 7 02 6、及其類似物。本發明一實施例之液晶顯示裝置可使 用於顯示部7022。透過所施加至顯示部7022之本發明一 實施例的液晶顯示裝置，可提供能顯示高品質影像的自動 櫃員機或具有低功率消耗的自動櫃員機。 第28D圖描繪攜帶式遊戲機，包含外殻7031、外殻 7032、顯示部7033、顯示部7034、微音器7035、揚聲器 -112- 201220292 703 6、操作鍵703 7、尖筆703 8、及其類似物。本發明一 實施例之液晶顯示裝置可使用於顯示部7033及/或7034。 透過所施加至顯示部7033及/或7034之本發明一實施例 的液晶顯示裝置，可提供能顯示高品質影像的攜帶式遊戲 機或具有低功率消耗的攜帶式遊戲機。雖然第28D圖中所 描繪之攜帶式遊戲機具有二顯示部703 3及7034，但包含 於該攜帶式遊戲機中之顯示部的數目並未受限於二。 第28E圖描繪行動電話，包含外殼704 1、顯示部 7042 '聲頻輸入部7043、聲頻輸出部7044、操作鍵7045 、光接收部7046、及其類似物。在光接收部7046中所接 收的光係轉換成爲電信號，而外部影像可藉以載入。本發 明一實施例之液晶顯示裝置可使用於顯示部7042。透過所 施加至顯示部7042之本發明一實施例的液晶顯示裝置， 可提供能顯示高品質影像的行動電話或具有低功率消耗的 行動電話。 第28F圖描繪攜帶式資訊終端機，包含外殻7051、顯 示部7052、操作鍵7053、及其類似物。調變解調器可結 合於第28F圖中所描繪之攜帶式資訊終端機的外殻705 1 中。本發明一實施例之液晶顯示裝置可使用於顯示部7052 。透過所施加至顯示部7 0 5 2之本發明一實施例的液晶顯 示裝置，可提供能顯示高品質影像的攜帶式資訊終端機或 具有低功率消耗的攜帶式資訊終端機。 此實施例可與上述該等實施例之任一者適當地結合。 此申請案係根據2 01 0年7月2日在日本專利局所申 -113- 201220292 請之日本專利申請案序號20 1 0- 1 52 1 5 8，該申請案的全部 內容係結合於本文中，以供參考。 【圖式簡單說明】 第1圖係描繪液晶顯示裝置之結構的方塊圖； 第2A及2B圖描繪面板的結構及像素的組態； 第3圖槪略地描繪液晶顯示裝置的驅動方法及背光的 操作； 第4A至4C圖槪略地描繪供應至區域之光的色相之實 例； 第5A及5B圖槪略地描繪供應至區域之光的色相之實 例； 第6圖描繪掃描線驅動器電路的組態； 第7圖槪略地描繪第X脈波輸出電路2 0_x ; 第8A圖描繪脈波輸出電路的組態，且第8B及8C圖 係其時序圖； 第9圖係掃描線驅動器電路的時序圖； 第1 〇圖係掃描線驅動器電路的時序圖； 第Π圖描繪信號線驅動器電路的組態； 第1 2A及1 2B圖描繪供應至信號線的影像信號（ DATA )之時序的實例； 第13圖描繪選擇信號之掃描的時序及背光之照明的 時序； 第14圖描繪選擇信號之掃描的時序及背光之照明的 -114--110- S 201220292 volts. The amount of change of either of the transistor 951 and the transistor 952 is less than 1 volt, and it can be confirmed that both of the transistors have high reliability. Further, since the amount of change in the threshold voltage Vth of the transistor 952 provided with the back gate 912 is less than 0.1 volt, it can be confirmed that the transistor 952 has higher reliability than the transistor 951. (Example 1) A liquid crystal display device according to an embodiment of the present invention can provide an electronic device capable of displaying high quality images. A liquid crystal display device according to an embodiment of the present invention can provide an electronic device having low power consumption. In particular, in a mobile electronic device that is not easy to supply power constantly, the liquid crystal display device according to an embodiment of the present invention including the component is Advantages of the increase in continuous use time* The liquid crystal display device of one embodiment of the present invention can be used for a display device, a laptop personal computer, or an image reproduction device provided with a recording medium (typically, a digital versatile disc can be reproduced, such as a digital versatile disc a device for recording the content of a medium (DVD) and having a display for displaying the reproduced image)" In addition to the above examples, an electronic device which can include the liquid crystal display device of an embodiment of the present invention can be given The following: mobile phones, portable game consoles, portable information terminals 'e-book readers, cameras such as cameras or digital cameras' glasses-type displays (head-mounted displays), navigation systems, audio reproduction devices (eg 'car audio Component and digital audio player), copy machine, fax machine, printing machine, multi-function Printers, automated teller machines (the ATM), vending machines, and the like. Specific examples of such electronic devices -111 - 201220292 are shown in Figures 28A through 28F. Fig. 28A depicts an e-book reader including a housing 7001, a display portion 002, and the like. A liquid crystal display device according to an embodiment of the present invention can be used in the display portion 7002. Through the liquid crystal display device of the present invention to the display portion 7〇〇2, an electronic book reader capable of displaying high quality images or an e-book reader having low power consumption can be provided. Further, the face plate can be formed using a flexible substrate and the touch panel can be flexible, and the liquid crystal display device can be made flexible, which enables a flexible, lightweight, and easy-to-use e-book reader to be provided. Fig. 28B depicts a display device comprising a housing 7011, a display portion 70 1 2, a bracket 70 1 3, and the like. A liquid crystal display device according to an embodiment of the present invention can be used for the display portion 7012. A liquid crystal display device according to an embodiment of the present invention applied to the display portion 7012 can provide a display device capable of displaying high quality images or a display device having low power consumption. In its category, the display device includes any information display device for personal computer, television (TV) broadcast reception, advertising, and the like. Fig. 28C depicts an automated teller machine including a housing 702, a display portion 7022, a coin slot 7023, a banknote slot 7024, a card slot 7025, a passbook slot 7626, and the like. The liquid crystal display device of one embodiment of the present invention can be applied to the display portion 7022. Through the liquid crystal display device of an embodiment of the present invention applied to the display portion 7022, an automatic teller machine capable of displaying high quality images or an automatic teller machine having low power consumption can be provided. FIG. 28D depicts a portable game machine including a housing 7031, a housing 7032, a display portion 7033, a display portion 7034, a microphone 7035, a speaker-112-201220292 703 6, an operation button 703 7 , a stylus 703 8 , and Its analogues. The liquid crystal display device of one embodiment of the present invention can be used for the display portion 7033 and/or 7034. A liquid crystal display device according to an embodiment of the present invention applied to the display portion 7033 and/or 7034 can provide a portable game machine capable of displaying high quality images or a portable game machine having low power consumption. Although the portable game machine depicted in Fig. 28D has two display portions 703 3 and 7034, the number of display portions included in the portable game machine is not limited to two. Fig. 28E depicts a mobile phone including a housing 704 1 , a display unit 7042 'audio input unit 7043, an audio output unit 7044, an operation key 7045, a light receiving unit 7046, and the like. The light received in the light receiving portion 7046 is converted into an electrical signal, and the external image can be loaded. The liquid crystal display device of one embodiment of the present invention can be used for the display portion 7042. By the liquid crystal display device of an embodiment of the present invention applied to the display portion 7042, a mobile phone capable of displaying high quality images or a mobile phone having low power consumption can be provided. Figure 28F depicts a portable information terminal including a housing 7051, a display portion 7052, operation keys 7053, and the like. The modem can be incorporated into the housing 705 1 of the portable information terminal depicted in Figure 28F. A liquid crystal display device according to an embodiment of the present invention can be used for the display portion 7052. A liquid crystal display device according to an embodiment of the present invention applied to the display portion 7 0 5 2 can provide a portable information terminal device capable of displaying high-quality images or a portable information terminal device having low power consumption. This embodiment can be combined as appropriate with any of the above-described embodiments. This application is based on the Japanese Patent Application No. 20 1 0- 1 52 1 5, which is filed on July 2, 2000 in the Japanese Patent Office. For reference. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the structure of a liquid crystal display device; FIGS. 2A and 2B are diagrams showing the structure of a panel and a configuration of a pixel; FIG. 3 is a schematic diagram showing a driving method of a liquid crystal display device and a backlight 4A to 4C schematically depict an example of a hue of light supplied to a region; FIGS. 5A and 5B schematically depict an example of a hue of light supplied to a region; FIG. 6 depicts a scan line driver circuit Configuration; Figure 7 schematically depicts the X-pulse output circuit 2 0_x; Figure 8A depicts the configuration of the pulse output circuit, and Figures 8B and 8C are timing diagrams; Figure 9 is the scan line driver circuit Timing diagram; Figure 1 is a timing diagram of the scan line driver circuit; Figure 1 depicts the configuration of the signal line driver circuit; Figures 1 2A and 1 2B depict the timing of the image signal ( DATA ) supplied to the signal line Example; Figure 13 depicts the timing of the scan of the selection signal and the timing of the illumination of the backlight; Figure 14 depicts the timing of the scan of the selection signal and the illumination of the backlight -114-

S 201220292 時序； 第15A圖描繪面板的結構，且第15B至15D圖各自 描繪像素的組態； 第1 6圖描繪掃描線驅動器電路的結構； 第1 7圖係掃描線驅動器電路的時序圖； 第1 8圖描繪信號線驅動器電路的組態，· 第19A及19B圖描繪脈波輸出電路的組態； 第20A及20B圖描繪脈波輸出電路的組態； 第2 1 A至2 1 C圖係描繪電晶體之製造方法的橫剖面視 t,q.| · 圖， 第22A至22D圖係電晶體的橫剖面視圖； 第 23A 、 23B 、 23C 、 23C， 、 23D 、 23D， 、 23E ，及 23E’係描繪液晶顯示裝置之製造方法的橫剖面視圖； 第24A至24C圖係液晶顯示裝置的頂視圖； 第25A及25B圖係像素的頂視圖及橫剖面視圖； 第26A及26B圖係液晶顯示裝置的頂視圖及橫剖面視 圖； 第27圖係描繪液晶顯示裝置之結構的透視圖； 第28A至28F圖各自描繪電子裝置； 第29A及29B圖描繪電晶體的結構； 第30圖係用以界定Vth的圖形； 第31A至31C圖係顯示透過光照射的負偏壓應力測試 之結果的圖形：以及 第32A及32B圖係像素的頂視圖及橫剖面視圖。 -115- 201220292 【主要元件符號說明】 10， 60， 412， 4002 ：像素部 11，61，414，4004:掃描線驅動器電路 1 2，6 2，4 1 3，4 0 0 3 :信號線驅動器電路 1 5，6 1 5 :像素 16 ， 31-39 ， 50-53 ， 121 ， 65a〜65c ， 616 ， 708 ， 951 ，952 ， 2450 ， 2460 ， 2470 &gt; 2480 ， 4009 ， 4010 ， 4022 ： 電晶體 1 7，617 :電容器 1 8，6 1 8，4 0 1 1 :液晶元件 20 :脈波輸出電路 2 1〜27 :端子 101〜103， 601〜603 &gt;6212，：區域 120，611~613，620:移位暫存器 123，623 :開關元件組群 301 :全彩色影像顯示週期 3 02 :單色移動影像顯示週期 3 03 :單色靜止影像顯示週期 400 :液晶顯示裝置 401 :影像記憶體 402 :影像資料選擇電路 403 :選擇器S 201220292 timing; Figure 15A depicts the structure of the panel, and Figures 15B to 15D each depict the configuration of the pixel; Figure 16 depicts the structure of the scan line driver circuit; Figure 17 shows the timing diagram of the scan line driver circuit; Figure 18 depicts the configuration of the signal line driver circuit, · 19A and 19B depict the configuration of the pulse output circuit; 20A and 20B depict the configuration of the pulse output circuit; 2 1 A to 2 1 C The figure depicts a cross-sectional view of the manufacturing method of the transistor, t, q.| · Fig. 22A to 22D, a cross-sectional view of the transistor; 23A, 23B, 23C, 23C, 23D, 23D, 23E, And 23E' are cross-sectional views depicting a method of fabricating a liquid crystal display device; 24A to 24C are top views of liquid crystal display devices; top and cross-sectional views of pixels 25A and 25B; and Figs. 26A and 26B A top view and a cross-sectional view of the liquid crystal display device; Fig. 27 is a perspective view showing the structure of the liquid crystal display device; Figs. 28A to 28F each depict an electronic device; and Figs. 29A and 29B depict the structure of the transistor; a map used to define Vth ; Line of FIG. 31A to 31C show through negative bias stress test result of light irradiation pattern: FIG. 32B and 32A and the second pixel based top view and a cross sectional view. -115- 201220292 [Description of main component symbols] 10, 60, 412, 4002: Pixel section 11, 61, 414, 4004: Scanning line driver circuit 1 2, 6 2, 4 1 3, 4 0 0 3 : Signal line driver Circuit 1 5,6 1 5 : pixels 16, 31-39, 50-53, 121, 65a~65c, 616, 708, 951, 952, 2450, 2460, 2470 &gt; 2480, 4009, 4010, 4022: transistor 1, 7,617: Capacitor 1, 8, 1 1, 4 0 1 1 : Liquid crystal element 20: Pulse output circuit 2 1 to 27: Terminals 101 to 103, 601 to 603 &gt; 6212, Area 120, 611 to 613 , 620: shift register 123, 623: switching element group 301: full color image display period 3 02: monochrome moving image display period 3 03: monochrome still image display period 400: liquid crystal display device 401: image memory Body 402: image data selection circuit 403: selector

404 ： CPU404 : CPU

S 201220292 4 05 ： 控制器 4 0 6 ' 1601 :面板 40 7 &gt; 1 6 1 2 :背光 408 ： 背光控制電路 410 ： 全彩色影像資料 4 11： 單色影像資料 420 ： 輸入裝置 421 ： 光度測定電路 5 00 ， 514 ， 700 ， 900 ， 16 11 ， 2400 ， 400 1 ， 402 1 6 2 0 Ο :基板 501-504 &gt; 530 &gt; 705， 706 ：導電膜 5 0 5， 4 0 3 0:像素電極 5 06， 703，902，2402 :閫極絕緣膜 5 07 ： 主動層 5 08 ， 5 09 ， 512 ， 513 ， 531 ， 701 ， 707 ， 907〜909 2407 :絕緣膜 510， 4 0 3 5 :間隔物 515， 403 1 :相對電極 516 ： 液晶層 517， 4040 :遮光膜 702， 901，2401 :閘極電極 7 04， 903，2403 :氧化物半導體膜 9 0:5a ，2405a:源極電極 9 05b ，2405b:汲極電極 -117- 201220292 9 1 2 :背面閘極電極 9 2 1 :曲線 9 2 4 :切線 925 :閘極電壓軸截段 931，941 :初始特徵 932，942 :後測試特徵 93 6，243 f :基底膜 945 :部分 1 602 :第一漫射板 1 6 0 3 :稜鏡片 1 604 :第二漫射板 1 605 :光導板 1 607 :背光面板 1 6 0 8 :電路板 1 609 ： COF 帶 1610， 4018： FPC 2406 :通道保護膜 2409 :保護絕緣膜 2411 :第一閘極電極 2412:第二閘極電極 2413 :第一閘極絕緣膜 2414 :第二閘極絕緣膜 4 0 0 5 :密封劑 4006 :相對基板S 201220292 4 05 : Controller 4 0 6 ' 1601 : Panel 40 7 &gt; 1 6 1 2 : Backlight 408 : Backlight control circuit 410 : Full color image data 4 11 : Monochrome image data 420 : Input device 421 : Photometric Circuits 5 00 , 514 , 700 , 900 , 16 11 , 2400 , 400 1 , 402 1 6 2 0 Ο : substrate 501-504 &gt; 530 &gt; 705, 706 : conductive film 5 0 5, 4 0 3 0: pixel Electrode 5 06, 703, 902, 2402: drain insulating film 5 07 : active layer 5 08 , 5 09 , 512 , 513 , 531 , 701 , 707 , 907 to 909 2407 : insulating film 510 , 4 0 3 5 : interval 515, 403 1 : opposite electrode 516: liquid crystal layer 517, 4040: light shielding film 702, 901, 2401: gate electrode 7 04, 903, 2403: oxide semiconductor film 9 0: 5a, 2405a: source electrode 9 05b , 2405b: Bipolar electrode - 117- 201220292 9 1 2 : Back gate electrode 9 2 1 : Curve 9 2 4 : Tangent line 925: Gate voltage axis section 931, 941: Initial characteristics 932, 942: Post test feature 93 6,243 f : base film 945 : part 1 602 : first diffusing plate 1 6 0 3 : bracts 1 604 : second Diffusing plate 1 605 : Light guide plate 1 607 : Backlight panel 1 6 0 8 : Circuit board 1 609 : COF tape 1610, 4018: FPC 2406 : Channel protective film 2409 : Protective insulating film 2411 : First gate electrode 2412 : Two gate electrode 2413 : first gate insulating film 2414 : second gate insulating film 4 0 0 5 : sealant 4006 : opposite substrate

-118- S 201220292 4007 :液晶 4014 &gt; 4015 ：引線 4016 :連接端子 4019 :各向異性導電膜 6 1 1 0 :轉移基板 6 111:第一黏著層 6116:將被分離之層 620 1 :分離層 6202 :臨時支撐基板 6203 :用於分離之黏著劑 6 2 0 6 :金屬板 6:2 0 7 :阻隔層 6210 :第一佈線層 6 21 1 :第二佈線層 7 0 01，7011，7021，7031，7032，7041，7 05 1 ：外殼 7002， 7012， 7022， 7033， 7034， 7042， 7052 ：顯示 7013 ：支架 7023 :硬幣槽 7 0 2 4 :紙幣槽 7025 :卡片槽 7026 :存摺槽 703 5 :微音器 703 6 :揚聲器 -119- 201220292 7037， 7045 &gt; 7053 ：操作鍵 703 8 :尖筆 7043 :聲頻輸入部 7044 :聲頻輸出部 7046 :光接收部-118- S 201220292 4007 : Liquid crystal 4014 &gt; 4015 : Lead 4016 : Connection terminal 4019 : Anisotropic conductive film 6 1 1 0 : Transfer substrate 6 111: First adhesive layer 6116: Layer to be separated 620 1 : Separation Layer 6202: temporary support substrate 6203: adhesive for separation 6 2 0 6 : metal plate 6: 2 0 7 : barrier layer 6210: first wiring layer 6 21 1 : second wiring layer 7 0 01, 7011, 7021 , 7031, 7032, 7041, 7 05 1 : Housing 7002, 7012, 7022, 7033, 7034, 7042, 7052: Display 7013: Bracket 7023: Coin slot 7 0 2 4: Banknote slot 7025: Card slot 7026: Passbook slot 703 5: Microphone 703 6 : Speaker - 119 - 201220292 7037, 7045 &gt; 7053 : Operation key 703 8 : Point pen 7043 : Audio input unit 7044 : Audio output unit 7046 : Light receiving unit

-120- S-120- S

Claims (1)

Translated fromChinese

201220292 七、申請專利範圍： 1 . —種液晶顯不裝置，包括： 像素部，包含第一區及第二區：以及 複數個光源， 其中該第一區及該第二區各自包含液晶元件及電晶體 ，該液晶元件之透射率係依據影像信號的電壓而被控制， 且該電晶體係用以控制該電壓的保持’ 其中該電晶體的通道形成區包含半導體材料’其能隙 係比矽半導體的能隙更寬，且其本質載子密度係比該矽半 導體的本質載子密度更低， 其中該複數個光源係組構要執行第一驅動及第二驅動 &gt; 其中色相係彼此互相不同的複數個光係以第一旋轉順 序而依序地供應至該第一區，且色相係彼此互相不同的該 複數個光係以與該第一驅動中之該第一旋轉順序不同的第 二旋轉順序而依序地供應至該第二區， 其中具有單一色相的光係在該第二驅動中被連續供應 至該第一區及該第二區的其中一者或二者，以及 其中用以保持該電壓的週期係在該第一驅動與該第二 驅動之間不同。 2.如申請專利範圍第1項之液晶顯示裝置，其中該 半導體材料係氧化物半導體。 3 ·如申請專利範圍第2項之液晶顯示裝置，其中該 氧化物半導體係In-Ga-Ζη-Ο爲主氧化物半導體》 -121 - 201220292 4.如申請專利範圍第2項之液晶顯示裝置，其中該 通道形成區的氫濃度係小於或等於5xl019/Cm3。 5 ·如申請專利範圍第1項之液晶顯示裝置，其中該 電晶體之截止狀態電流密度係小於或等於1 OOyA/μιη。 6. —種液晶顯示裝置，包括： 像素部，包含第一區及第二區；以及 複數個光源， 其中該第一區及該第二區各自包含液晶元件及電晶體 ，該液晶元件之透射率係依據影像信號的電壓而被控制， 且該電晶體係用以控制該電壓的保持， 其中該電晶體的通道形成區包含半導體材料，其能隙 係比矽半導體的能隙更寬，且其本質載子密度係比該矽半 導體的本質載子密度更低， 其中該複數個光源係組構要執行第一驅動及第二驅動 y 其中色相係彼此互相不同的複數個光係以第一旋轉順 序而依序地供應至該第一區，且色相係彼此互相不同的該 複數個光係以與該第一驅動中之該第一旋轉順序不同的第 二旋轉順序而依序地供應至該第二區， 其中具有單一色相的光係在該第二驅動中被連續供應 至該第一區及該第二區的其中一者或二者，以及 其中用以保持該電壓的週期係在當驅動係自該第一驅 動而切換至該第二驅動時增加。 7. 如申請專利範圍第6項之液晶顯示裝置，其中該 -122- S 201220292 半導體材料係氧化物半導體。 8 .如申請專利範圍第7項之液晶顯示裝置，其中該 氧化物半導體係In-Ga-Ζη-Ο爲主氧化物半導體。 9.如申請專利範圍第7項之液晶顯示裝置，其中該 通道形成區的氫濃度係小於或等於5xl019/Cm3。 1 〇.如申請專利範圍第6項之液晶顯示裝置，其中該 電晶體之截止狀態電流密度係小於或等於1 OOyA/μιη。 11. 一種液晶顯示裝置，包括： 像素部，包含第一區及第二區； 複數個光源；以及 輸入裝置， 其中該第一區及該第二區各自包含液晶元件及電晶體 ，該液晶元件之透射率係依據影像信號的電壓而被控制， 且該電晶體係用以控制該電壓的保持， 其中該電晶體的通道形成區包含半導體材料，其能隙 係比矽半導體的能隙更寬，且其本質載子密度係比該矽半 導體的本質載子密度更低， 其中該複數個光源係組構要執行第一驅動及第二驅動 &gt; 其中色相係彼此互相不同的複數個光係以第一旋轉順 序而依序地供應至該第一區，且色相係彼此互相不同的該 複數個光係以與該第一驅動中之該第一旋轉順序不同的第 二旋轉順序而依序地供應至該第二區， 其中具有單一色相的光係在該第二驅動中被連續供應 -123- 201220292 至該第一區及該第二區的其中一者或二者’ 其中驅動係依據來自該輸入裝置的信號而切換於該第 一驅動與該第二驅動之間，以及 其中用以保持該電壓的週期係在該第一驅動與該第二 驅動之間不同。 12.如申請專利範圍第1 1項之液晶顯示裝置，其中 該半導體材料係氧化物半導體。 1 3 .如申請專利範圍第1 2項之液晶顯示裝置，其中 該氧化物半導體係In-Ga-Ζη-Ο爲主氧化物半導體。 1 4.如申請專利範圍第1 2項之液晶顯示裝置，其中 該通道形成區的氫濃度係小於或等於5X1019/cm3。 15. 如申請專利範圍第11項之液晶顯示裝置，其中 該電晶體之截止狀態電流密度係小於或等於lOOyA/μτη。 16. —種液晶顯示裝置，包括： 像素部，包含第一區及第二區； 複數個光源；以及 輸入裝置， 其中該第一區及該第二區各自包含液晶元件及電晶體 ’該液晶元件之透射率係依據影像信號的電壓而被控制， 且該電晶體係用以控制該電壓的保持， 其中該電晶體的通道形成區包含半導體材料，其能隙 $ It矽半導體的能隙更寬，且其本質載子密度係比該矽半 導體的本質載子密度更低， 其中該複數個光源係組構要執行第一驅動及第二驅動 -124- 201220292 其中色相係彼此互相不同的複數個光係以第一旋轉順 序而依序地供應至該第一區，且色相係彼此互相不同的該 複數個光係以與該第一驅動中之該第一旋轉順序不同的第 二旋轉順序而依序地供應至該第二區， 其中具有單一色相的光係在該第二驅動中被連續供應 至該第一區及該第二區的其中一者或二者， 其中驅動係依據來自該輸入裝置的信號而切換於該第 一驅動與該第二驅動之間，以及 其中用以保持該電壓的週期係在當驅動係自該第一驅 動而切換至該第二驅動時增加。 1 7.如申請專利範圍第1 6項之液晶顯示裝置，其中 該半導體材料係氧化物半導體。 1 8 .如申請專利範圍第1 7項之液晶顯示裝置，其中 該氧化物半導體係In-Ga-Ζη-Ο爲主氧化物半導體。 19. 如申請專利範圍第1 7項之液晶顯示裝置，其中 該通道形成區的氫濃度係小於或等於5xl019/cm3。 20. 如申請專利範圍第1 6項之液晶顯示裝置，其中 該電晶體之截止狀態電流密度係小於或等於lOOyA/μπι。 -125201220292 VII. Patent application scope: 1. A liquid crystal display device, comprising: a pixel portion comprising a first region and a second region: and a plurality of light sources, wherein the first region and the second region each comprise a liquid crystal element and In the transistor, the transmittance of the liquid crystal element is controlled according to the voltage of the image signal, and the electro-crystal system is used to control the holding of the voltage. Wherein the channel forming region of the transistor comprises a semiconductor material, and the energy gap ratio is The energy gap of the semiconductor is wider, and its essential carrier density is lower than the intrinsic carrier density of the germanium semiconductor, wherein the plurality of light source systems are configured to perform the first driving and the second driving> wherein the hue systems are mutually Different plurality of light systems are sequentially supplied to the first region in a first rotation order, and the plurality of light systems different in hue from each other are different from the first rotation order in the first driving Two rotation sequences are sequentially supplied to the second zone, wherein a light system having a single hue is continuously supplied to one of the first zone and the second zone in the second drive Or both, and wherein the holding period for the voltage in the first driving system between the different second driver. 2. The liquid crystal display device of claim 1, wherein the semiconductor material is an oxide semiconductor. 3. The liquid crystal display device of claim 2, wherein the oxide semiconductor is In-Ga-Ζη-Ο is a main oxide semiconductor. -121 - 201220292 4. The liquid crystal display device of claim 2 Wherein the channel formation zone has a hydrogen concentration of less than or equal to 5 x 1019 / cm3. 5. The liquid crystal display device of claim 1, wherein the off-state current density of the transistor is less than or equal to 100 yA/μιη. 6. A liquid crystal display device comprising: a pixel portion including a first region and a second region; and a plurality of light sources, wherein the first region and the second region each comprise a liquid crystal element and a transistor, and the liquid crystal element transmits The rate is controlled according to the voltage of the image signal, and the crystal system is used to control the holding of the voltage, wherein the channel forming region of the transistor comprises a semiconductor material, and the energy gap is wider than that of the germanium semiconductor, and The intrinsic carrier density is lower than the intrinsic carrier density of the germanium semiconductor, wherein the plurality of light source structures are configured to perform a first driving and a second driving y, wherein the plurality of light systems having mutually different hue systems are first The plurality of light systems sequentially supplied to the first region in a rotation order and having different hue systems from each other are sequentially supplied to the second rotation sequence different from the first rotation order in the first drive a second zone, wherein a light system having a single hue is continuously supplied to one or both of the first zone and the second zone in the second drive, and wherein the Periodic pressure due to the increase in the drive train when the drive from the first to the second driving switches. 7. The liquid crystal display device of claim 6, wherein the -122-S 201220292 semiconductor material is an oxide semiconductor. 8. The liquid crystal display device of claim 7, wherein the oxide semiconductor is In-Ga-Ζη-Ο is a main oxide semiconductor. 9. The liquid crystal display device of claim 7, wherein the channel formation region has a hydrogen concentration of less than or equal to 5 x 1019 / cm3. The liquid crystal display device of claim 6, wherein the off-state current density of the transistor is less than or equal to 100 Å/μιη. A liquid crystal display device comprising: a pixel portion including a first region and a second region; a plurality of light sources; and an input device, wherein the first region and the second region each comprise a liquid crystal element and a transistor, the liquid crystal element The transmittance is controlled according to the voltage of the image signal, and the crystal system is used to control the holding of the voltage, wherein the channel forming region of the transistor comprises a semiconductor material, and the energy gap is wider than that of the germanium semiconductor. And having an intrinsic carrier density lower than an intrinsic carrier density of the germanium semiconductor, wherein the plurality of light source systems are configured to perform a first driving and a second driving> wherein the plurality of light systems are different from each other The plurality of light systems sequentially supplied to the first region in a first rotation order, and the hue systems are different from each other, in a second rotation order different from the first rotation order in the first drive Supplying to the second zone, wherein a light system having a single hue is continuously supplied in the second drive - 123 - 201220292 to one of the first zone and the second zone or Wherein the driving system is switched between the first driving and the second driving according to a signal from the input device, and wherein a period for maintaining the voltage is between the first driving and the second driving different. 12. The liquid crystal display device of claim 11, wherein the semiconductor material is an oxide semiconductor. The liquid crystal display device of claim 12, wherein the oxide semiconductor is In-Ga-Ζη-Ο is a main oxide semiconductor. The liquid crystal display device of claim 12, wherein the channel formation region has a hydrogen concentration of less than or equal to 5 x 10 19 /cm 3 . 15. The liquid crystal display device of claim 11, wherein the off-state current density of the transistor is less than or equal to 100 yA/μτη. 16. A liquid crystal display device comprising: a pixel portion including a first region and a second region; a plurality of light sources; and an input device, wherein the first region and the second region each comprise a liquid crystal element and a transistor The transmittance of the component is controlled according to the voltage of the image signal, and the transistor system is used to control the retention of the voltage, wherein the channel formation region of the transistor comprises a semiconductor material, and the gap of the energy gap of the semiconductor is more Wide, and its essential carrier density is lower than the intrinsic carrier density of the germanium semiconductor, wherein the plurality of light source systems are configured to perform a first driving and a second driving - 124 - 201220292 wherein the hue systems are different from each other The plurality of light systems are sequentially supplied to the first area in a first rotation order, and the plurality of light systems different in hue from each other are in a second rotation order different from the first rotation order in the first drive And sequentially supplied to the second zone, wherein a light system having a single hue is continuously supplied to one or both of the first zone and the second zone in the second drive Wherein the driving system is switched between the first driving and the second driving according to a signal from the input device, and wherein a period for maintaining the voltage is when the driving system switches from the first driving to the second driving Increased when driving. The liquid crystal display device of claim 16, wherein the semiconductor material is an oxide semiconductor. The liquid crystal display device of claim 17, wherein the oxide semiconductor is In-Ga-Ζη-Ο is a main oxide semiconductor. 19. The liquid crystal display device of claim 17, wherein the channel formation region has a hydrogen concentration of less than or equal to 5 x 1 019 / cm 3 . 20. The liquid crystal display device of claim 16, wherein the off-state current density of the transistor is less than or equal to 100 yA/μπι. -125