201218595 六、發明說明： 【發明所屬之技術領域】 本發明係細-種電_㈣，_是_-種改善電源 轉換器次諧波的電路及方法。 【先前技術】 圖1係以典型的馳返式電源轉換器為例，其中整流電路 10將交流電壓VAC整流，電容Cbulk用以穩壓整流電路10 的輸出以產生 Vbulk ’控制器14送出信號GATE切換與 變壓器12的一次侧線圈Lp串聯的功率開關M1，進而使電壓 Vbulk轉換為輸出電壓Vo，感測電阻Rcs與功率開關M1串 聯，用以取得與電流Ip相關的信號Vcs，控制器14根據信號 Vcs與預設的電流限制信號決定信號GATE。近來，為了提升 產品競爭力，降低成本也成為設計時的要求目標，因此元件的 選用也日益嚴苛，電容Cbulk相對於以往的設計也越來越小。 然而，對於相同額定之系統來說，當系統處於低輸入電壓時， 較小的電容Cbulk將使電壓Vbulk的維持時間(holdup time)變 短’因此從變壓器12的一次側看到的電壓vbulk將變化極大， 這在系統開機脫離軟啟動(soft-start)或進入過載時，將產生嚴 重的次諧波問題。嚴重的次諧波可能造成在滿載時低輸入電壓 無法啟動或輸入電壓高低壓過载保護(over current pr〇tecti〇n) 差異極大的問題。 圖2用以說明習知馳返式電源轉換器的次諧波問題，其中 波形20係控制器14内部的時脈CLK，波形22係前緣遮蔽信 201218595 號LEB，波形24係信號GATE，波形26係電流限制信號，波 形28係健Vcs。時脈CLK係用以決定信號-的週期， _緣遮蔽健LEB歧用以舰錄VeS的突波，當信號 ， Vcs大於電流限制信號時’信號GATE轉為低準位以使^開 關Ml關閉(turn off)。參賴2，在低輸人電壓時，功率^ Ml的導通時間(ontime)較長以取得足夠的能量，如時間^至 時間t2，然而，功率開關M1的切換週期是固定的，因此功率 開關Ml的截止時間(offtime)會相對的變短，這造成能量無法 # 完全釋放，所以當功率開關Ml再次打開(論on)時，如^ t3所示’信號Vcs的起始準位變高，使得信號Vcs很快的大於 電流限制信號，如時間t4所示，因而導致功率開關M1的導 通時間變短，功率開關Ml的導通時間的劇烈變化將使馳返式 電源轉換器產生嚴重的次諧波問題。 【發明内容】 • 本發明的目的，在於提出一種改善電源轉換器次諧波的電 路及方法。 根據本發明，一種改善電源轉換器次諧波的電路包括第一 電流限制信號產生器提供第一電流限制信號，第二電流限制信 號產生器提供第二電流限制信號，電流限制信號控制器根據功 率開關的開關週期比產生切換信號，以及選擇器根據該切換信 號從該第一及第二電流限制信號中選取其中一個作為最終電 流限制信號以限制該功率開關電流的最大值。當該開關週期比 小於預設的臨界值時，該選擇器選擇該第一電流限制信號作為 201218595 δ玄最終電限制t號，當該開關週期比大於該預設的臨界值 時’該選擇H選擇該第二電流限制信號作為該最終電流限制信 號。 根據本發明，-觀善電_換||:域波的方法包括提供 第一電流限制fs號及第二電流限制信號，以該第一電流限制信 號作為預設的最終電流限制信號以限制功率開關電流的最大 值’侧該功率Μ關的開關週期比，以及當該開關週期比大於 預設的臨界辦，改_第二紐關錢作輕最終電流限 制信號。 根據本發明…種改善電源轉換器次諧波的電路包括多個 電流限制信號產生器提供多個電流限制信號，電流限制信號控 制器根據功糊_關職比產生娜健，以及選擇器根 據該切換錢選擇該多個電流限健號其巾—個作為最終電 流限制信號以限繼功率關電流的最域。當該關週期比 小於預設的臨界值時’該選擇器選擇該多個電流限制信號中的 第電/ϋ號作為該最終電流限制信號；當該開關週期比 大於掘界值時，該麵H依稍擇該帛—電流關信號以外 的其他電w限條號作為該祕電流_健後，再選擇該第 -電流限制信號作為該最終電流限制信號。 根據本L —種改善電源轉換器次諧波的方法包括提供 多個電祕制信號，從該多個電流_信號帽取第—電流限 制信號作為—_信砂_鲜_電流的最大 值偵測該功率開關的開關週期比，當該開關週期比小於預設 的L界值時’轉該帛—電皱制信齡為該最終電流限制信 5 201218595 號’當該開關週期比大_預設的臨界值時，依序 電流限制信狀外的其他電流限繼號作為該 信號，以及在依賴擇糾他電流_錢料魏 制信號之後，再選擇該第-紐關信號作為棘終電流= 信號。 由於最終電流限制信號根據功率開關的開關週期 變’因此當細關週航過大時，於下個週射以選擇適 最終電流限制信號以避免該開關週期比變化過大，進而減 諧波問題。 4 Ί 【實施方式】 圖3係應用本發明於馳返式電源轉換器，其包括變壓器 η、功率開關m與變壓器12的一次側線圈串聯、感測電阻 Res與功率開關Ml串聯以及控制器14控制功率開關奶的切 換以將輸入電壓Vin轉換為輸出電壓v〇。控制器M包括振盈 • 11 2〇提供時脈CLK及與該時脈CLK同步的鑛齒波信號201218595 VI. Description of the Invention: [Technical Field of the Invention] The present invention is a fine-type electric _(four), _ is a circuit and method for improving the subharmonics of a power converter. [Prior Art] FIG. 1 is an example of a typical flyback power converter in which a rectifying circuit 10 rectifies an alternating current voltage VAC, and a capacitor Cbulk is used to regulate the output of the rectifying circuit 10 to generate a Vbulk 'controller 14 to send a signal GATE. Switching the power switch M1 in series with the primary side coil Lp of the transformer 12, thereby converting the voltage Vbulk into an output voltage Vo, the sensing resistor Rcs is connected in series with the power switch M1 for obtaining a signal Vcs related to the current Ip, and the controller 14 The signal Vcs and the preset current limit signal determine the signal GATE. Recently, in order to enhance product competitiveness and reduce costs, it has become a design goal, and the selection of components has become increasingly stringent. Capacitor Cbulk is becoming smaller and smaller than previous designs. However, for the same rated system, when the system is at a low input voltage, the smaller capacitor Cbulk will shorten the holdup time of the voltage Vbulk 'so the voltage vbulk seen from the primary side of the transformer 12 will The change is extremely large, which will cause serious subharmonic problems when the system is powered off from soft-start or into overload. Severe subharmonics can cause problems with low input voltage failure at full load or high voltage and low voltage overload protection (over current pr〇tecti〇n). 2 is used to illustrate the subharmonic problem of the conventional flyback power converter, wherein the waveform 20 is the clock CLK inside the controller 14, the waveform 22 is the leading edge shielding letter 201218595 LEB, the waveform 24 is the signal GATE, the waveform 26 series current limit signal, waveform 28 is healthy Vcs. The clock CLK is used to determine the period of the signal-, and the edge of the LEB is used to record the spur of the VeS. When the signal, Vcs is greater than the current limit signal, the signal GATE is turned to the low level so that the switch M1 is turned off. (turn off). According to 2, when the input voltage is low, the on time of the power ^ Ml is long to obtain sufficient energy, such as time ^ to time t2, however, the switching period of the power switch M1 is fixed, so the power switch The off time of Ml will be relatively short, which causes the energy to fail to be completely released. Therefore, when the power switch M1 is turned on again (on), as shown in ^3, the starting level of the signal Vcs becomes high. The signal Vcs is made much faster than the current limit signal, as shown by time t4, thus causing the on-time of the power switch M1 to be shortened, and the drastic change of the on-time of the power switch M1 will cause the regenerative power converter to generate a severe subharmonic Wave problem. SUMMARY OF THE INVENTION The object of the present invention is to provide a circuit and method for improving the subharmonics of a power converter. In accordance with the present invention, a circuit for improving subharmonics of a power converter includes a first current limit signal generator providing a first current limit signal, a second current limit signal generator providing a second current limit signal, and a current limit signal controller based on power The switching cycle ratio of the switch generates a switching signal, and the selector selects one of the first and second current limiting signals as a final current limiting signal according to the switching signal to limit the maximum value of the power switching current. When the switch cycle ratio is less than a preset threshold, the selector selects the first current limit signal as the 201218595 δ 玄 final power limit t number, when the switch cycle ratio is greater than the preset threshold value, the selection H The second current limit signal is selected as the final current limit signal. According to the present invention, a method for controlling a power-converting||domain wave includes providing a first current limit fs number and a second current limit signal, the first current limit signal being used as a preset final current limit signal to limit power The maximum value of the switching current' side of the power-switching switching cycle ratio, and when the switching cycle ratio is greater than the preset threshold, the second final value is used as the light final current limiting signal. According to the present invention, a circuit for improving a sub-harmonic of a power converter includes a plurality of current limit signal generators for providing a plurality of current limit signals, the current limit signal controller generating Najian according to a work-off ratio, and a selector according to the The switching money selects the plurality of current limit signals as a final current limiting signal to limit the most recent range of power off currents. When the off period ratio is less than a preset threshold value, the selector selects the first electric/signal number of the plurality of current limiting signals as the final current limiting signal; when the switching period ratio is greater than the digging value, the surface H selects the other current w limit number other than the current off signal as the secret current, and then selects the first current limit signal as the final current limit signal. The method for improving the power sub-harmonic of the power converter according to the present invention includes providing a plurality of electrical secret signals, and taking the first current limit signal from the plurality of current_signal caps as the maximum value of the -_xinsha_fresh_current Measure the switching cycle ratio of the power switch, when the switching cycle ratio is less than the preset L threshold value, 'turn the 帛-electric wrinkle system to the final current limit letter 5 201218595' when the switching cycle is larger than _ When the threshold value is set, the current limit number other than the current limit is used as the signal, and after the signal is selected according to the correction current, the first button signal is selected as the peak current. = signal. Since the final current limit signal changes according to the switching period of the power switch, when the fine-circumference is too large, the next cycle is selected to select the appropriate final current limit signal to avoid the switching cycle ratio being excessively large, thereby reducing the harmonic problem. 4 实施 [Embodiment] FIG. 3 is a fly-back power converter to which the present invention is applied, including a transformer η, a power switch m connected in series with a primary side coil of the transformer 12, a sense resistor Res connected in series with the power switch M1, and a controller 14 The switching of the power switch milk is controlled to convert the input voltage Vin into an output voltage v〇. The controller M includes a surge • 11 2〇 provides a clock CLK and a mineral tooth signal synchronized with the clock CLK
Vosc，SR正反器22根據時脈CLK觸發控制信號GATE ;比 較器24根據最終電流限制信號Vclf及信號Vcs產生信號si 以重置SR正反器22 ’其中信號Vcs與通過功率開關Ml的電 流Ip相關；以及改善次諧波的電路26偵測控制信號GATE的 開關週期比(duty ratio)，並據以改變最終電流限制信號Vdf。 改善次諧波的電路26在控制信號GATE的開關週期比大於預 設的臨界值時，將改變最終電流限制信號Vclf，以避免控制信 號GATE的開關週期比在下一個週期時發生劇烈變化，進而減 6 201218595 緩次諧波問題。 改善;人相波的電路26包括電流限制信號控制器π、選擇 - 11 30以及二電流限制信號產生器32及34，其中電流限制信 , 號產生器32提供鑛齒波的第-電流限制信號Vcl卜電流限制 信號產生器34提供定值的第二電流限制信號Vd2。提供鋸齒 波的第一電流限制信號Vcll的電流限制信號產生器幻是相當 常見的技術，目前也已經有許多相關的專利，例如美國專利號 第6,674,656號，故於此不再贅述。選擇器30包含開關SW1 及SW2，開M SW1連接在電流限制信號產生器32及改善次 諸波的電路26的輸出端Vclf之間’開關SW2連接在電流限 制信號產生H 34及改善次諧波的電路26的輸出端猜之間。 電流限制信號控制器28偵測控制信號GATE的開關週期比以 產生切換仏號CCL控制開關SW1及SW2，進而選擇第一電 流限制信號Vcl 1或第二電流限制信號Vd2作為最終電流限制 信號。 • ® 4係電流限制信號控制器28的實施例，其包括比較器 40比較參考電壓Vref及鋸齒波信號v〇sc產生信號敗，信號 DX具有固定的開關週期比；反相器42反相信號Dx產生信號 DX，D型正反器44根據其資料輸入端d的控制信號gate 及時脈端elk上的信號DX，產生信號S2 ;以及D型正反器奶 根據其資料輸入端D的信號S2及時脈端clk上的控制信號 GATE產生切換信號CCL。 圖5係控制器14内部的信號，其中波形5〇係最終電流限 制信號vdf。設定第一電流限制信號Vcll為一般操作狀況下 [S ] 201218595 的最終電流限制信號Vclf，參照圖3、圖4及圖5，在週期耵 ^控制域GATE的開關週期比大於預設的臨界值，所以信 ' 號DX轉為低準位時控制信號GATE仍為高準位，如圖5的時 n ^t5所不’因此D型正反器44將送出高準位的信號S2。接 者在週期T2期間’由於控制信號GATE轉為高準位時信號幻 為高準位，因此D型正反器46送出高準位的切換信號取， 、使k擇^ 3Gif擇第二電流神丨信號Vei2作為最終電流限制 U Vdf’如時間t6及波形50所示，進而避免功率開關Ml 的導通時間發生劇烈變化，減緩次諧波問題。由於在週期L ，月間控制4§號GATE的開關週期比未大於預設的臨界值，因 此，如時間t7所示，在信號DX轉為低準位時，信號幻也變 為低準位，故在週期T3期間，控制信號GATE轉為高準位時， 如時間t8所示，切換信號CCL變為低準位以使選擇器3〇再 次選擇第一電流限制信號Veil作為最終電流限制信號醫。 相反的’在週期12期間，如果控制信f虎GATE的開關職比 • 仍大於預設的臨界值時，選擇器如將維持電流限制信號VC12 作為最終電流關錢Vdf。在其他實補巾，第—電流限制 信號Veil不限定為鋸齒波’第二電流限制信號vd2也可以用 其他波形的電流限制信號取代。 圖3的改善次諧波的電路26也可以在週期Ή偵測到控制 #號GATE的開關週期比大於預設的臨界值時，於週期了2選 擇第-電流限制信號Vd2作為最終電流限制信號Vdf，接著 不論週期T2 _的控制信號GATE的開關週期比是否大於預 設的臨界值’在週期T3時都再次選擇第一電流限制健vdiVosc, SR flip-flop 22 triggers control signal GATE according to clock CLK; comparator 24 generates signal si according to final current limit signal Vclf and signal Vcs to reset SR flip-flop 22' where signal Vcs and current through power switch M1 The Ip correlation; and the circuit 26 for improving the subharmonic detects the switching duty ratio of the control signal GATE and accordingly changes the final current limit signal Vdf. The circuit 26 for improving the subharmonic will change the final current limit signal Vclf when the switching period ratio of the control signal GATE is greater than a preset threshold to prevent the switching period of the control signal GATE from drastically changing at the next period, thereby reducing 6 201218595 Slow harmonic problem. Improved; the phase wave circuit 26 includes a current limit signal controller π, a select - 11 30 and two current limit signal generators 32 and 34, wherein the current limit signal, the number generator 32 provides a first current limit signal of the mineral tooth wave The Vcl current limit signal generator 34 provides a fixed second current limit signal Vd2. A current limiting signal generator that provides a sawtooth first current limiting signal Vcll is a fairly common technique, and there are a number of related patents, such as U.S. Patent No. 6,674,656, which is hereby incorporated by reference. The selector 30 includes switches SW1 and SW2, and the open M SW1 is connected between the current limit signal generator 32 and the output terminal Vclf of the circuit 26 for improving the secondary waves. The switch SW2 is connected to the current limit signal to generate H 34 and improve the subharmonic. The output of circuit 26 is guessed between. The current limit signal controller 28 detects the switching cycle ratio of the control signal GATE to generate the switching nickname CCL control switches SW1 and SW2, thereby selecting the first current limit signal Vcl 1 or the second current limit signal Vd2 as the final current limit signal. • An embodiment of the ® 4 system current limit signal controller 28, which includes the comparator 40 comparing the reference voltage Vref and the sawtooth signal v〇sc to generate a signal loss, the signal DX having a fixed switching period ratio; and the inverter 42 inverting the signal The Dx generates a signal DX, and the D-type flip-flop 44 generates a signal S2 according to the control signal gate of the data input terminal d and the signal DX on the pulse end elk; and the signal S2 of the D-type flip-flop milk according to its data input terminal D The control signal GATE on the timely pulse end clk generates the switching signal CCL. Figure 5 is a signal internal to controller 14, where waveform 5 is the final current limit signal vdf. The first current limit signal Vc11 is set to be the final current limit signal Vclf of [S] 201218595 under normal operating conditions. Referring to FIG. 3, FIG. 4 and FIG. 5, the switching period ratio of the GATE in the period 耵^ is greater than a preset threshold. Therefore, when the signal DX turns to the low level, the control signal GATE is still at a high level, as shown in FIG. 5, n^t5 does not. Therefore, the D-type flip-flop 44 will send the high-level signal S2. During the period T2, the signal illusion is high level when the control signal GATE is turned to the high level, so the D-type flip-flop 46 sends the switching signal of the high level, so that k selects the 3Gif to select the second current. The oracle signal Vei2 is used as the final current limit U Vdf' as shown by time t6 and waveform 50, thereby avoiding a drastic change in the on-time of the power switch M1 and slowing down the subharmonic problem. Since the switching period of the 4th GATE in the period L and the month is not greater than the preset threshold value, as shown by the time t7, when the signal DX is turned to the low level, the signal illusion also becomes the low level. Therefore, during the period T3, when the control signal GATE is turned to the high level, as indicated by time t8, the switching signal CCL becomes a low level to cause the selector 3 to select the first current limiting signal Veil again as the final current limiting signal. . Conversely, during cycle 12, if the control signal of the control letter F GATE is still greater than the preset threshold, the selector will maintain the current limit signal VC12 as the final current switch Vdf. In other solid wipes, the first current limit signal Veil is not limited to a sawtooth wave. The second current limit signal vd2 may be replaced with a current limit signal of another waveform. The circuit 26 for improving the subharmonic of FIG. 3 can also select the first current limit signal Vd2 as the final current limit signal in the period 2 when the switching period ratio of the control ##GATE is detected to be greater than the preset threshold value. Vdf, then regardless of whether the switching period ratio of the control signal GATE of the period T2_ is greater than a preset threshold value, 'the first current limiting key vdi is selected again at the period T3
[SI 201218595 作為最終電流限制信號Vclf。 圖6係改善次諧波的電路26的另一實施例，其除了與圖 - 3的電路同樣具有電流限制信號控制器28、選擇器3〇以及電 ，流限制信號產生器32及34外，還包括電流限制信號產生器 36用以提供定值的第三電流限制信號Vd3，其中選擇器％除 了開關SW1及SW2外，還有開關SW3連接在電流限制信號 產生器36及改善次諧波的電路26的輸出端vclf之間。圖7 係圖6信號的波形，其中波形52為最終電流限制信號Vdf。 參照圖6及圖7，設定第一電流限制信號Vdl為一般操作狀 況下的最終電流限制信號Vclf，當電流限制信號控制器28偵 測到控制信號GATE關關週期比未大於預言史的臨界值時，維 持最終電流限制信號Vdf=Vcll。假設在週期T1時，電流限制 信號控制器28彳貞測到控制信號GATE的開關週期比大於預設 的臨界值，電流限制信號控制器28將送出切換信號CCL給選 擇器30,以使選擇器30在週期T2選擇第二電流限制信號德 • 作為最終電流限制信號Vclf，如波形52所示，接著，不論週 期T2時的控制信號GATE是否大於預設的臨界值，選擇器3〇 在週期T3時都將選擇第三電流限制信叙犯作為最終電流限 制仏號Vclf。同樣的’不論在週期T3時的控制信號GATE是 否大於預設的臨界值，選擇器3〇於下個週期將再次選擇第一 電流關信號vdi作為祕關信號Vd卜在其他實施 例中’第-電流限制信號Veil秘定為鑛齒波，第二電流限 制信號Vcl2及第三電流限制信號Vd3也可以用其他波形的電 流限制信號取代。 201218595 【圖式簡單說明】 圖1係典型的驰返式電源轉換器； 圖2用以說明習知馳返式電源轉換器的次諧波問題； 圖3係應用本發明的馳返式電源轉換器； 圖4係圖3中電流限制信號控制器的實施例； 圖5係控制器内部的信號； 圖6係改善次諧波的電路的另一實施例；以及 圖7係圖6信號的波形。 【主要元件符號說明】 10整流電路 12 變壓器 14控制器 20振盪器 22 SR正反器 24 比較器 26改善次諧波的電路 28電流限制信號控制器 30選擇器 32電流限制信號產生器 34電流限制信號產生器 36電流限制信號產生器 40 比較器 201218595 42反相器 44 D型正反器 46 D型正反器 50最終電流限制信號Vclf 52最終電流限制信號Vclf[SI 201218595 as the final current limit signal Vclf. 6 is another embodiment of a circuit 26 for improving subharmonics, which has a current limit signal controller 28, a selector 3A, and an electrical, flow limited signal generator 32 and 34, in addition to the circuit of FIG. The current limiting signal generator 36 is further configured to provide a fixed third current limiting signal Vd3, wherein the selector % is connected to the current limiting signal generator 36 and the improved subharmonic in addition to the switches SW1 and SW2. Between the output vclf of circuit 26. Figure 7 is a waveform of the signal of Figure 6, where waveform 52 is the final current limit signal Vdf. Referring to FIGS. 6 and 7, the first current limit signal Vd1 is set to be the final current limit signal Vclf under normal operating conditions, and the current limit signal controller 28 detects that the control signal GATE off period is not greater than the predicted threshold. At this time, the final current limit signal Vdf=Vc11 is maintained. It is assumed that at the period T1, the current limit signal controller 28 detects that the switching period ratio of the control signal GATE is greater than a preset threshold, and the current limit signal controller 28 will send the switching signal CCL to the selector 30 to make the selector 30 selects the second current limit signal DT in the period T2 as the final current limit signal Vclf, as shown by the waveform 52, and then, regardless of whether the control signal GATE at the period T2 is greater than a preset threshold value, the selector 3 〇 is in the period T3 The third current limit signal will be selected as the final current limit nickname Vclf. Similarly, whether or not the control signal GATE at the period T3 is greater than a preset threshold, the selector 3 will select the first current off signal vdi as the secret signal Vd again in the next cycle. - The current limit signal Veil is secreted as a mineral tooth wave, and the second current limit signal Vcl2 and the third current limit signal Vd3 can also be replaced by current limit signals of other waveforms. 201218595 [Simple diagram of the diagram] Figure 1 is a typical flyback power converter; Figure 2 is used to illustrate the subharmonic problem of the conventional flyback power converter; Figure 3 is the flyback power conversion using the present invention Figure 4 is an embodiment of the current limiting signal controller of Figure 3; Figure 5 is a signal internal to the controller; Figure 6 is another embodiment of a circuit for improving subharmonics; and Figure 7 is a waveform of the signal of Figure 6. . [Main component symbol description] 10 rectifier circuit 12 transformer 14 controller 20 oscillator 22 SR flip-flop 24 comparator 26 circuit for improving subharmonics 28 current limit signal controller 30 selector 32 current limit signal generator 34 current limit Signal generator 36 current limit signal generator 40 comparator 201218595 42 inverter 44 D-type flip-flop 46 D-type flip-flop 50 final current limit signal Vclf 52 final current limit signal Vclf