201136176 六、發明說明： 【發明所屬之技術領域】 本發明係關於電路設計’特別係關於鎖相迴路（phase lock loop ’ PLL )電路及其操作方法。 【先前技術】 鎖相迴路電路係一種可根據參考訊號產生輸出訊號之 控亲J電路，其中該產生之輪出訊號之頻率和相位皆同步於 該參考訊號。鎖相迴路電路不僅可產生穩定之輸出訊號， 其亦可用以恢復摻雜雜訊之傳輸訊號。因此，鎖相迴路電 路之應用範圍相當廣泛，例如頻率產生器或是無線通訊裝 置皆可見鎖相迴路電路之應用。 圖1顯示一習知的鎖相迴路電路的示意圖。如圖1所示 ’該鎖相迴路電路100包含一相位頻率偵測器丨丨0、一電荷 栗（charge pump)電路120、一迴路濾波器130、一電壓控 制振盪器140和一除頻器150。該鎖相迴路電路1〇0係根據一 輸入之參考訊號產生一輸出訊號，而該輸出訊號則在除頻 後作為該鎖相迴路電路100之另一輸入。據此，該鎖相迴路 電路100形成一負回饋系統以達到頻率鎖定之目的。該除頻 器1 5 0係用以提供該輸出訊號之除頻訊號。該相位頻率偵測 器110可用以比較該參考訊號和該除頻器輸出之除頻訊 號’用以輸出上升訊號和下降訊號。該電荷泵電路12〇根據 該上升訊號和該下降訊號輸出一控制電流。該迴路據波器 130根據該控制電流提供一控制電壓❶該電壓控制振盈器 140即根據該控制電壓提供該輸出訊號。 -4 - 201136176 〜鎖相迴路電路根據其電路特性具有不同之鎖定速度及 穩足度。具有較高鎖定速度之鎖相迴路電路可較快速地輸 出鎖疋之輸出訊號。然而，由於具有較高鎖定速度之鎖相 沿路電路對於輸入之參考訊號之反應較快，當參考訊號具 有擾動或雜訊時，其亦會反應至輸出訊號。換言之，具有 較向鎖定速度之鎖相迴路電路之穩定度較低。相反地，具 有較高穩定度之鎖相迴路電路對於輸入之參考訊號之反應 冑慢而可抑制輸出訊號之擾動’但卻需較長時間來輸出鎖 定之輸出訊號。 因此，該互相衝突之特性為鎖相迴路電路設計上之兩 難。然而，若能在相位鎖定前提供較高之鎖定速度，並在 相位鎖定後提供較佳的穩定度，即可同時達到上述兩種優 點。本發明即提供具備此種特性之鎖相迴路電路及其操作 方法。 【發明内容】 • 本發明揭示一種鎖相迴路電路，包含一相位頻率偵測 器、一鎖定偵測電路、一電荷泵電路、一迴路濾波器、一 電壓控制振盪器以及一除頻器。該相位頻率偵測器係設定 以根據一第一參考訊號和一除頻訊號以輸出一第一電荷泵 控制訊號和一第二電荷泵控制訊號。該鎖定偵測電路係設 定以根據該第一電荷泵控制訊號和一第二參考訊號輸出一 鎖定訊號，其中該鎖定訊號之值可為鎖定和非鎖定。該電 荷泵電路係設定以根據該第一電荷泵控制訊號和該第二電 荷泵控制訊號提供一控制電流，且當該鎖定訊號之值為非 201136176 鎖疋時’該電何泵電路之電流驅動能力較當該鎖定訊號之 值為鎖定時強。該迴路渡波器係設定以根據該控制電流提 供一控制電壓。該電壓控制振盪器係設定以根據該控制電 壓提供一輸出訊號。該除頻器係設定以根據該輸出訊號提 供該除頻訊號。 上文已經概略地敍述本發明之技術特徵，俾使了文之 詳細描述得以獲得較佳瞭解。構成本發明之申請專利範圍 標的之其它技術特徵將描述於下文。本發明所屬技術領域 中具有通常知識者應可瞭解，下文揭示之概念與特定實施 例可作為基礎而相當輕易地予以修改或設計其它結構或製 程而實現與本發明相同之目的。本發明所屬技術領域中具 有通常知識者亦應可瞭解，這類等效的建構並無法脫離後 附之申請專利範圍所提出之本發明的精神和範圍。 【實施方式】 本發明在此所探討的方向為一種鎖相迴路電路及其操 作方法。為了能徹底地瞭解本發明，將在下列的描述中提 出詳盡的步驟及組成。顯然地，本發明的施行並未限定於 本發明技術領域之技藝者所熟習的特殊細節。另一方面， 眾所周知的組成或步驟並未描述於細節中，以避免造成本 發明不必要之限制。本發明的較佳實施例會詳細描述如下 ’然而除了這些詳細描述之外，本發明還可以廣泛地施行 在其他的實施例中，且本發明的範圍不受限^，其以之後 的專利範圍為準。 圖2顯示根據本發明之一實施例之鎖相迴路電路之示 201136176 意圖。如圖2所示，該鎖相迴路電路2〇〇包含一相位頻率偵 測器210、一鎖定偵測電路220、一電荷泵電路23〇、一迴路 濾波器240、一電壓控制振盪器25〇和一除頻器26〇。該相位 頻率偵測器21 〇係設定以根據一第一參考時脈訊號和一除 頻時脈訊號以輸出一第一電荷泵控制訊號和一第二電荷泵 控制訊號。該鎖定偵測電路22〇係設定以根據該第一電荷泵 控制訊號和一第二參考時脈訊號輸出一鎖定訊號，其中該 鎖疋sfl號之值可為鎖定和非鎖定。該電荷泵電路230係設定 以根據該第一電荷泵控制訊號和該第二電荷泵控制訊號提 供一控制電流，且當該鎖定訊號之值為非鎖定時，該電荷 泵電路230之電流驅動能力較當該鎖定訊號之值為鎖定時 強。該迴路濾波器240係設定以根據該控制電流提供一控制 電壓。該電壓控制振盪器250係設定以根據該控制電壓提供 一輸出時脈訊號。該除頻器260係設定以根據該輸出時脈訊 號提供該除頻時脈訊號。 如上所述’該鎖相迴路電路200係利用該鎖定偵測電路 220決定該鎖相迴路電路2〇〇是否已鎖定。當該鎖相迴路電 路200未鎖定時，該電荷泵電路23〇之電流驅動能力較強。 因此’該鎖相迴路電路200對於輸入之參考訊號之反應較快 而能較快進入鎖定狀態。當該鎖相迴路電路2〇〇鎖定後，該 電荷泵電路230之電流驅動能力轉弱。因此，該鎖相迴路電 路200對於輸入之參考訊號之反應較慢，故其對於輸入之參 考sfl说具有較高之穩定性。 圖3顯示該電荷泵電路230之内部示意圖。如圖3所示， 201136176 該電荷泵電路230包含兩條電流驅動路徑31〇和32〇，其中該 電流驅動路徑310包含兩個電流源312和3 14及兩個開關316 和3 1 8，該電流驅動路徑320亦包含兩個電流源322和324及 兩個開關326和328。該等開關316和326係由該相位頻率偵 測器210所輸出之第一電荷泵控制訊號所控制，而該等開關 3 18和328係由該相位頻率偵測器210所輸出之第二電荷泵 控制訊號所控制。根據該第一電荷泵控制訊號和該第二電 荷泵控制訊號’該電荷泵電路230即可提供正電流或負電流 至該迴路濾波器240 ’以控制該迴路濾波器240之電壓。當 該鎖相迴路電路200未鎖定時，該等電流驅動路徑31〇和32〇 皆啟動。因此，該電荷泵電路230具有較強之電流驅動能力 。當該鎖相迴路電路200鎖定後，該鎖定偵測電路220所輸 出之鎖定訊號即關閉該電流驅動路徑320。此時，該電荷泵 電路2 3 0即降低其電流驅動能力。根據本發明之實施例之電 荷泵電路230不限於包含兩條電流驅動路徑，而可及於數條 電流驅動路徑，其中當該鎖定偵測電路220所輸出之鎖定訊 號之值為非鎖定時，該電荷栗電路230所開啟之電流驅動路 徑較當該當鎖定偵測電路220所輸出之鎖定訊號之值為鎖 定時多。 圖2之實施例係將該第一參考時脈訊號之一脈衝邊緣 同步於該第二參考時脈訊號之一脈衝邊緣。例如，可將該 第一參考時脈訊號之脈衝上升邊緣同步於該第二參考時脈 訊號之脈衝上升邊緣，或將該第一參考時脈訊號之脈衝下 降邊緣同步於該第二參考時脈訊號之脈衝下降邊緣。 201136176 圖4顯示根據圖2之實施例之部分訊號之時序圖。如圖4 所示，該第一參考時脈訊號之脈衝上升邊緣係同步於該第 二參考時脈訊號之脈衝上升邊緣，且該第一電荷泵控制訊 號之脈衝上升邊緣亦同步於該第二參考時脈訊號之脈衝上 升邊緣。 該第一電荷泵控制訊號代表該第一參考時脈訊號和該 除頻之輸出訊號之相位差。在該鎖相迴路電路2〇〇鎖定前， 該第一參考時脈訊號和該除頻之輸出訊號具有大相位差， 故該第一電荷泵控制訊號之工作週期較長，如圖4所示。在 該鎖相迴路電路200鎖定之過程中，該第一參考時脈訊號和 該除頻之輸出訊號之相位差逐漸縮小，故該第一電荷泵控 制訊號之工作週期亦逐漸縮短。待第一參考時脈訊號和該 除頻之輸出訊號同步後，該第一電荷系控制訊號之工作週 期即為其最小可能工作週期。根據圖4之圖示，本實施例即 利用該第二參考時脈訊號之脈衝下降邊緣作為鎖定前後之 • &界。當該第二參考時脈訊號之脈衝下降邊緣落後該第- 電荷系控制訊號之脈衝下降邊緣時，亦即該第一電荷系控 制訊號之工作週期縮小至一定程度時，即判定該鎖相迴路 電路20G已鎖定。該鎖定偵測電路22◦即輸出鎖定訊號以降 低該電荷泵電路230之電流驅動能力。較佳的，該第二參考 時脈訊號之工作週期可設定以略大於該第一電荷泉控制訊 號之最小可能工作週期，例如可將該第二參考時脈訊號之 工作週㈣定為該第-電荷系控制訊號之最小可能工作週 期之兩倍。 -9 - 201136176 圖4顯示之實施例係將該第一參考時脈訊號之脈衝上 升邊緣同步於該第二參考時脈訊號之脈衝上升邊緣。若將 該第一參考時脈訊號之脈衝下降邊緣同步於該第二參考時 脈訊號之脈衝下降邊緣’則判斷該鎖相迴路電路2〇〇之鎖定 標準為當該第二參考時脈訊號之脈衝上升邊緣領先該第一 電荷泵控制訊號之脈衝上升邊緣時，判斷該鎖相迴路電路 200已鎖定》 在鎖相迴路電路之操作上，可使該除頻之輸出訊號之 頻率逐漸增加以同步於該第一參考訊號，或是可使該除頻 之輸出訊號之逐漸降低以同步於該第一參考訊號。根據操 作上之不同，該第一電荷泵控制訊號可為上升訊號或下降 訊號，而該第二電荷泵控制訊號即為另一者。 圖2之實施例係將該第一參考時脈訊號之一脈衝邊緣 同步於該第二參考時脈訊號之一脈衝邊緣。一簡單之方法 係以該第一參考時脈訊號作為該第二參考時脈訊號。較佳 地，為使該第二參考時脈訊號之工作週期略大於該第一電 荷泵控制訊號之最小可能工作週期，亦可以一組合邏輯電 路根據該第一參考時脈訊號產生該第二參考時脈訊號。 圖5顯示根據本發明之一實施例之組合邏輯電路。如圖 5所示，δ亥組合邏輯電路5〇〇包含複數個緩衝器51〇和一互斥 或閘520。該等緩衝器510用以延遲該第一參考時脈訊號。 該互斥或閘520分別接收該第一參考時脈訊號及其延遲訊 號以產生該第二參考時脈訊號。如圖5所示，該第二參考時 脈訊號之工作週期即可藉由該等緩衝器51〇之數量調整。 201136176 圖6顯示該鎖定#測電路22〇之内部示意圖。如圖6所示 ，該鎖定偵測電路220係由一 〇型正反器6〇〇實現。該〇型正 反器600之訊號輸入端接地，時脈輸入端連接該第二參考時 脈訊號’該負設定端連接該第一電荷泵控制訊號，而該負 輸出端即作為鎖定訊號。對應圖4之訊號時序圖，當該第二 參考時脈訊號之脈衝下降邊緣領先該第一電荷泉控制訊號 ，脈衝下降邊緣時，該D型正反器_之正輸出端係輸出邏 輯〇，故該D型正反器600之負輸出端係輸出邏。待該第 二參考時脈訊號之脈衝下降邊緣落後該第一電荷泵控制訊 號之脈衝下降邊緣時，該D型正反器6〇〇即設定使其正輸出 端係輸出邏輯1，故其之負輸出端係輸出邏輯〇。據此，即 可根據該鎖定訊號控制該電荷泵電路23〇之電流驅動能力。 圖7顯示根據本發明之一實施例之鎖相迴路電路之操 作方法之流程圖。在步驟7〇2,根據一第一參考時脈訊號和 一除頻時脈訊號產生一第一電荷泵控制訊號和一第二電荷 泵控制訊號，並進入步驟704。在步驟704，根據該第一電 荷泵控制訊號和該第二電荷泵控制訊號產生一控制電流， 並進入步驟706。在步驟706，根據該第一電荷泵控制訊號 和一第一參考時脈訊號判斷是否一鎖相迴路電路已鎖定。 若判斷該鎖定訊號已鎖定，則進入步驟7〇8，否則進入步称 710。在步驟708，減少該控制電流之電流驅動能力，並進 入步驟710。在步驟710，根據該控制電流提供一控制電壓 ’並進入步驟712。在步驟712，根據該控制電壓提供一輸 出時脈訊號，並進入步驟714。在步驟714,根據該輸出時201136176 VI. Description of the Invention: [Technical Field] The present invention relates to circuit design', particularly to a phase lock loop PLL circuit and a method of operating the same. [Prior Art] A phase-locked loop circuit is a control J circuit that generates an output signal according to a reference signal, wherein the frequency and phase of the generated round-trip signal are synchronized with the reference signal. The phase-locked loop circuit not only produces a stable output signal, but it can also be used to recover the transmitted signal of the doped noise. Therefore, the application of the phase-locked loop circuit is quite extensive. For example, the frequency generator or the wireless communication device can be used for the phase-locked loop circuit. Figure 1 shows a schematic diagram of a conventional phase-locked loop circuit. As shown in FIG. 1 , the phase locked loop circuit 100 includes a phase frequency detector 丨丨0, a charge pump circuit 120, a loop filter 130, a voltage controlled oscillator 140, and a frequency divider. 150. The phase-locked loop circuit 1〇0 generates an output signal according to an input reference signal, and the output signal is used as another input of the phase-locked loop circuit 100 after frequency division. Accordingly, the phase locked loop circuit 100 forms a negative feedback system for frequency locking purposes. The frequency divider 150 is used to provide the frequency-divided signal of the output signal. The phase frequency detector 110 can be used to compare the reference signal and the demultiplexed signal output of the frequency divider to output a rising signal and a falling signal. The charge pump circuit 12 outputs a control current according to the rising signal and the falling signal. The loop data generator 130 provides a control voltage according to the control current. The voltage control oscillator 140 provides the output signal according to the control voltage. -4 - 201136176 ~ The phase-locked loop circuit has different locking speeds and stability according to its circuit characteristics. A phase-locked loop circuit with a higher locking speed can output the output signal of the lock faster. However, since the phase-locked circuit with a higher locking speed reacts faster to the input reference signal, it also reacts to the output signal when the reference signal has disturbance or noise. In other words, the phase-locked loop circuit with a relatively fast locking speed is less stable. Conversely, a phase-locked loop circuit with higher stability reacts slowly to the input reference signal and suppresses the disturbance of the output signal' but takes a long time to output the locked output signal. Therefore, the conflicting characteristics are two difficulties in the design of the phase-locked loop circuit. However, if you can provide a higher locking speed before phase locking and provide better stability after phase locking, you can achieve both of these advantages. The present invention provides a phase locked loop circuit having such characteristics and an operating method thereof. SUMMARY OF THE INVENTION The present invention discloses a phase locked loop circuit including a phase frequency detector, a lock detecting circuit, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a frequency divider. The phase frequency detector is configured to output a first charge pump control signal and a second charge pump control signal according to a first reference signal and a frequency division signal. The lock detection circuit is configured to output a lock signal according to the first charge pump control signal and a second reference signal, wherein the value of the lock signal can be locked and unlocked. The charge pump circuit is configured to provide a control current according to the first charge pump control signal and the second charge pump control signal, and when the value of the lock signal is not 201136176, the current drive of the pump circuit The ability is stronger than when the value of the lock signal is locked. The loop ferrator is configured to provide a control voltage based on the control current. The voltage controlled oscillator is configured to provide an output signal based on the control voltage. The frequency divider is configured to provide the frequency division signal based on the output signal. The technical features of the present invention have been briefly described above, so that a detailed description of the present invention can be better understood. Other technical features constituting the scope of the patent application of the present invention will be described below. It is to be understood by those of ordinary skill in the art that the conception and the specific embodiments disclosed herein may be modified or otherwise. It is to be understood by those of ordinary skill in the art that this invention is not limited to the scope of the present invention as set forth in the appended claims. [Embodiment] The direction of the present invention as discussed herein is a phase locked loop circuit and an operating method thereof. In order to thoroughly understand the present invention, detailed steps and compositions will be set forth in the following description. It is apparent that the practice of the invention is not limited to the specific details familiar to those skilled in the art. On the other hand, well-known components or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention will be described in detail below. However, the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited thereto. quasi. 2 shows the intent of a phase locked loop circuit in accordance with an embodiment of the present invention. As shown in FIG. 2, the phase locked loop circuit 2 includes a phase frequency detector 210, a lock detecting circuit 220, a charge pump circuit 23, a loop filter 240, and a voltage controlled oscillator. And a frequency divider 26〇. The phase frequency detector 21 is configured to output a first charge pump control signal and a second charge pump control signal according to a first reference clock signal and a frequency division pulse signal. The lock detection circuit 22 is configured to output a lock signal according to the first charge pump control signal and a second reference clock signal, wherein the value of the lock sfl number can be locked and unlocked. The charge pump circuit 230 is configured to provide a control current according to the first charge pump control signal and the second charge pump control signal, and the current drive capability of the charge pump circuit 230 when the value of the lock signal is not locked. It is stronger when the value of the lock signal is locked. The loop filter 240 is configured to provide a control voltage based on the control current. The voltage controlled oscillator 250 is configured to provide an output clock signal based on the control voltage. The frequency divider 260 is configured to provide the frequency division clock signal according to the output clock signal. As described above, the phase-locked loop circuit 200 uses the lock detect circuit 220 to determine whether the phase-locked loop circuit 2 is locked. When the phase locked loop circuit 200 is not locked, the charge pump circuit 23 has a strong current driving capability. Therefore, the phase-locked loop circuit 200 reacts faster to the input reference signal and can enter the locked state faster. When the phase locked loop circuit 2 is locked, the current driving capability of the charge pump circuit 230 is weakened. Therefore, the phase-locked loop circuit 200 reacts slowly to the input reference signal, so it has a high stability for the input reference sfl. FIG. 3 shows an internal schematic of the charge pump circuit 230. As shown in FIG. 3, 201136176 the charge pump circuit 230 includes two current drive paths 31A and 32A, wherein the current drive path 310 includes two current sources 312 and 314 and two switches 316 and 311. Current drive path 320 also includes two current sources 322 and 324 and two switches 326 and 328. The switches 316 and 326 are controlled by the first charge pump control signal output by the phase frequency detector 210, and the switches 3 18 and 328 are the second charge output by the phase frequency detector 210. Controlled by the pump control signal. The charge pump circuit 230 can provide a positive or negative current to the loop filter 240' to control the voltage of the loop filter 240 based on the first charge pump control signal and the second charge pump control signal. When the phase locked loop circuit 200 is unlocked, the current drive paths 31 〇 and 32 皆 are all activated. Therefore, the charge pump circuit 230 has a strong current driving capability. When the phase locked loop circuit 200 is locked, the lock signal outputted by the lock detecting circuit 220 turns off the current driving path 320. At this time, the charge pump circuit 230 lowers its current driving capability. The charge pump circuit 230 according to the embodiment of the present invention is not limited to including two current driving paths, and is applicable to a plurality of current driving paths, wherein when the value of the locking signal output by the locking detecting circuit 220 is not locked, The current driving path of the charge pump circuit 230 is more than when the value of the lock signal output by the lock detecting circuit 220 is locked. The embodiment of Figure 2 synchronizes one of the pulse edges of the first reference clock signal to one of the pulse edges of the second reference clock signal. For example, the pulse rising edge of the first reference clock signal may be synchronized to the pulse rising edge of the second reference clock signal, or the pulse falling edge of the first reference clock signal may be synchronized to the second reference clock. The pulse of the signal drops to the edge. 201136176 Figure 4 shows a timing diagram of a portion of the signal in accordance with the embodiment of Figure 2. As shown in FIG. 4, the pulse rising edge of the first reference clock signal is synchronized with the pulse rising edge of the second reference clock signal, and the pulse rising edge of the first charge pump control signal is also synchronized with the second Refer to the rising edge of the pulse of the clock signal. The first charge pump control signal represents a phase difference between the first reference clock signal and the divided output signal. Before the phase-locked loop circuit 2 is locked, the first reference clock signal and the frequency-divided output signal have a large phase difference, so that the first charge pump control signal has a longer duty cycle, as shown in FIG. . During the locking of the phase-locked loop circuit 200, the phase difference between the first reference clock signal and the frequency-divided output signal is gradually reduced, so that the duty cycle of the first charge pump control signal is gradually shortened. After the first reference clock signal is synchronized with the output signal of the frequency division, the working period of the first charge control signal is its minimum possible duty cycle. According to the illustration of FIG. 4, the pulse falling edge of the second reference clock signal is used as the front and rear boundaries of the lock. When the pulse falling edge of the second reference clock signal falls behind the pulse falling edge of the first charge control signal, that is, when the duty cycle of the first charge control signal is reduced to a certain extent, the phase locked loop is determined Circuit 20G is locked. The lock detect circuit 22 outputs a lock signal to reduce the current drive capability of the charge pump circuit 230. Preferably, the working period of the second reference clock signal can be set to be slightly smaller than the minimum possible working period of the first charge spring control signal. For example, the working week (4) of the second reference clock signal can be set as the first - The charge system controls the signal to twice the minimum possible duty cycle. -9 - 201136176 The embodiment shown in Figure 4 synchronizes the pulse rising edge of the first reference clock signal to the pulse rising edge of the second reference clock signal. If the pulse falling edge of the first reference clock signal is synchronized to the pulse falling edge of the second reference clock signal, the locking criterion of the phase locked loop circuit 2 is determined to be when the second reference clock signal is When the rising edge of the pulse leads the rising edge of the pulse of the first charge pump control signal, it is determined that the phase-locked loop circuit 200 is locked. In the operation of the phase-locked loop circuit, the frequency of the output signal of the frequency-divided signal is gradually increased to synchronize In the first reference signal, the output signal of the frequency division may be gradually decreased to be synchronized with the first reference signal. Depending on the operation, the first charge pump control signal can be a rising signal or a falling signal, and the second charge pump control signal is the other. The embodiment of Figure 2 synchronizes one of the pulse edges of the first reference clock signal to one of the pulse edges of the second reference clock signal. A simple method is to use the first reference clock signal as the second reference clock signal. Preferably, in order to make the working period of the second reference clock signal slightly larger than the minimum possible working period of the first charge pump control signal, a combination logic circuit may generate the second reference according to the first reference clock signal. Clock signal. Figure 5 shows a combinational logic circuit in accordance with an embodiment of the present invention. As shown in FIG. 5, the delta combination logic circuit 5A includes a plurality of buffers 51A and a mutex or gate 520. The buffers 510 are configured to delay the first reference clock signal. The mutex or gate 520 receives the first reference clock signal and its delay signal to generate the second reference clock signal. As shown in FIG. 5, the duty cycle of the second reference clock signal can be adjusted by the number of the buffers 51. 201136176 Figure 6 shows the internal schematic of the lock #测电路22〇. As shown in Fig. 6, the lock detecting circuit 220 is realized by a 正 type flip-flop 6 〇〇. The signal input terminal of the 正-type flip-flop 600 is grounded, and the clock input terminal is connected to the second reference clock signal. The negative set terminal is connected to the first charge pump control signal, and the negative output terminal is used as a lock signal. Corresponding to the signal timing diagram of FIG. 4, when the pulse falling edge of the second reference clock signal leads the first charge spring control signal, and the pulse falls edge, the positive output terminal of the D-type flip-flop _ outputs the logic 〇, Therefore, the negative output of the D-type flip-flop 600 is output logic. When the pulse falling edge of the second reference clock signal lags behind the pulse falling edge of the first charge pump control signal, the D-type flip-flop 6 is set to have its positive output output logic 1, so that The negative output is the output logic 〇. Accordingly, the current driving capability of the charge pump circuit 23 can be controlled based on the lock signal. Figure 7 is a flow chart showing the operation of a phase locked loop circuit in accordance with an embodiment of the present invention. In step 7〇2, a first charge pump control signal and a second charge pump control signal are generated according to a first reference clock signal and a frequency-divided clock signal, and the process proceeds to step 704. At step 704, a control current is generated based on the first charge pump control signal and the second charge pump control signal, and the process proceeds to step 706. At step 706, it is determined whether a phase locked loop circuit is locked according to the first charge pump control signal and a first reference clock signal. If it is determined that the lock signal is locked, then go to step 7〇8, otherwise go to step 710. At step 708, the current drive capability of the control current is reduced and the process proceeds to step 710. At step 710, a control voltage ' is supplied in accordance with the control current and proceeds to step 712. In step 712, an output clock signal is provided in accordance with the control voltage, and the flow proceeds to step 714. At step 714, according to the output
i i J •11- 201136176 脈訊號提供該除頻時脈訊號，並進入步驟716。在步驟714 ，再次判斷是否該鎖相迴路電路已鎖定。若判斷該鎖定訊 號已鎖定，則結束本方法，否則回到步驟702。如圓7所示 ，該鎖相迴路電路之操作方法即對應至圖2之鎖相迴路電路 200 〇 綜上所述，根據本發明之鎖相迴路電路及其操作方法 係偵測該鎖相迴路電路是否鎖定，以在該鎖相迴路電路鎖 定之前提供一較快之鎖定能力，並在該鎖相迴路電路鎖定 之後提供一較好之穩定度。 本發明之技術内容及技術特點已揭示如上，然而熟悉 本項技術之人士仍可能基於本發明之教示及揭示而作種種 不背離本發明精神之替換及修飾。因此，本發明之保護範 圍應不限於實施例所揭示者，而應包括各種不背離本發明 之替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 • 圖1顯示一習知的鎖相迴路電路的示意圖； 圖2顯示根據本發明之一實施例之鎖相迴路電路之内 部不意圖； 圖3顯示根據本發明之一實施例之電荷泵電路之示意 圖； 圖4顯示根據本發明之一實施例之部分訊號之時序圖； 圖5顯示根據本發明之一實施例之組合邏輯電路； 圖6顯示根據本發明之一實施例之鎖定偵測電路之内 部示意圖；以及 -12- i 201136176 圖7顯示根據本發明之一實施例之鎖相迴路電路之操 作方法之流程圖。 【主要元件符號說明】i i J •11- 201136176 The pulse signal provides the frequency division clock signal, and proceeds to step 716. At step 714, it is again determined if the phase locked loop circuit is locked. If it is determined that the lock signal is locked, the method ends, otherwise return to step 702. As shown by the circle 7, the operation method of the phase-locked loop circuit corresponds to the phase-locked loop circuit 200 of FIG. 2, and the phase-locked loop circuit and the operation method thereof according to the present invention detect the phase-locked loop. Whether the circuit is locked to provide a faster locking capability prior to locking of the phase locked loop circuit and to provide a better stability after the phase locked loop circuit is locked. The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is not limited by the scope of the invention, and the invention is intended to cover various alternatives and modifications. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a schematic diagram of a conventional phase-locked loop circuit; FIG. 2 shows an internal schematic of a phase-locked loop circuit according to an embodiment of the present invention; FIG. 3 shows an implementation according to one embodiment of the present invention. FIG. 4 shows a timing diagram of a portion of a signal in accordance with an embodiment of the present invention; FIG. 5 shows a combinational logic circuit in accordance with an embodiment of the present invention; FIG. 6 shows an embodiment of the present invention. Internal Schematic of Lock Detection Circuitry; and -12-i 201136176 FIG. 7 shows a flow chart of a method of operating a phase locked loop circuit in accordance with an embodiment of the present invention. [Main component symbol description]
100 鎖相迴路電路 110 相位頻率偵測器 120 電荷泵電路 130 迴路濾波器 140 電壓控制振盪器 150 除頻器 200 鎖相迴路電路 210 相位頻率偵測器 220 鎖定偵測電路 230 電荷泵電路 240 迴路濾波器 250 電壓控制振盪器 260 除頻器 310 電流驅動路徑 312 電流源 314 電流源 316 開關 318 開關 320 電流驅動路徑 322 電流源 324 電流源 326 開關 -13- 201136176 328 開關 500 組合邏輯電路 510 緩衝器 520 互斥或閘 600 D型正反器 702〜716 步驟 ί -14-100 phase-locked loop circuit 110 phase frequency detector 120 charge pump circuit 130 loop filter 140 voltage controlled oscillator 150 frequency divider 200 phase-locked loop circuit 210 phase frequency detector 220 lock detection circuit 230 charge pump circuit 240 circuit Filter 250 Voltage Control Oscillator 260 Frequency Demultiplexer 310 Current Drive Path 312 Current Source 314 Current Source 316 Switch 318 Switch 320 Current Drive Path 322 Current Source 324 Current Source 326 Switch-13- 201136176 328 Switch 500 Combinational Logic Circuit 510 Buffer 520 Mutually exclusive or gate 600 D-type flip-flops 702~716 Step ί -14-