201115659 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於—種背對 背晶片組堆疊的封裝方法與構造。 【先前技術】 由於電子產品之微小化以及南運作速度需求的描 加’現今產業上’為了提高單一半導體封裝結構之性能 與容量’以符合電子產品小型化之需求，半導體封裝结 構以多晶片模組化（Multi-chip Module)乃成一趨勢，俾藉 此將兩個或兩個以上之半導體晶片組合在單一封裝妹構 中’以縮減整體電路體積，並提升電性功能。目前於快 取§己憶體（Flash)產品的技術應用上，已達六層戍八層曰 片堆疊的階段。 然而，目前六層晶片堆疊產品是以正面朝上堆疊的方 式（即晶片主動面皆朝向遠離基板之方向）進行。一曰曰 曰日 片堆疊越高層，超過六層以上，例如八層，電性連接晶 片錄墊之銲線越長，並且銲線密度大幅提高，又六層或 更多層（特指八層）晶片堆疊產品之打線弧形非常難以控 制’在打線時則極容易發生甩線之情形而造成報廢。此 外 面朝上堆疊的方式進行封裝流程時，在黏著每一 個曰曰片之後皆需要進行一次打線，重覆進行黏晶與打線 氟程會達到八次以上，在作業性和污染源顆粒控制上都 具有一定的難度。 【發明内容】 201115659 為了解決上述之問顳 士 喊本發明之主要目的係在於一種 者對背晶片組堆疊的封裝古、土 & 方法與構造，在黏晶過程中能 控制六顆或更多晶片厚户& ^ 认 . 厚度的一致性，降低作業上的複雜 性，以減少發生晶片斷裂之情況。 本發明之次一目的係 的係在於k供一種背對背晶片組堆 疊的封裝方法與構造，±西处* 主要針對六顆或更多晶片堆疊 時’能控制打線製程之蠄抓古ώ 之線弧同度，以減少甩線情形之發 生。 本發明之再-目的係在於提供一種背對背晶片組堆 疊的封裝方法與構造，，要針對六顆或更多晶片堆叠 時，大巾δ地縮短製造過程，提升產能（υρΗ)。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種背對背晶片組堆疊的封裝 方法’主要包含以下步驟：提供一電路基板係具有一 第槽孔以及一第二槽，該電路基板在該第一槽孔與 該第二槽孔之間形成為一中央承載部以及在該第一槽孔 與該第二槽孔之外之一周邊板部。設置一面向晶片組於 :電路基板之該中央承載部’其中該面向晶片組係由「z」 子形堆疊之複數個第一晶片與一個或一個以上的第二晶 片所組成，其中該些第一晶片之主動面係朝向該電路基 板且偏向該第一槽孔，以使該些第一晶片之複數個第一 銲塾對準於該第-槽孔内，該些第二晶片之主動面係朝 向該電路基板且偏向該第二槽孔’以使該些第二晶片之 複數個第二銲墊對準於該第二槽孔内。進行一第一打線 201115659201115659 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a packaging method and structure for a back-to-back wafer stack. [Prior Art] Due to the miniaturization of electronic products and the description of the speed requirement of the south operation, 'in order to improve the performance and capacity of a single semiconductor package structure, in order to meet the demand for miniaturization of electronic products, the semiconductor package structure is multi-wafer mode. The Multi-chip Module is a trend whereby two or more semiconductor wafers can be combined in a single package to reduce the overall circuit size and enhance electrical functions. At present, in the technical application of fast-moving CMOS products, it has reached the stage of stacking six layers of eight layers. However, current six-layer wafer stack products are stacked face up (i.e., the active faces of the wafer are oriented away from the substrate). The higher the stack of the Japanese wafers, the more than six layers, for example, eight layers, the longer the soldering wire for electrically connecting the wafer recording pads, and the density of the bonding wires is greatly improved, and six or more layers (specifically eight layers) The arcing of the wafer stacking product is very difficult to control. 'When the wire is hit, it is extremely prone to smashing and causing scrapping. In addition, when the package process is carried out in a stack-up manner, it is necessary to perform a wire bonding after each die is adhered, and the process of repeating the die bonding and wire bonding will be more than eight times, in terms of workability and particle control of the pollution source. Has a certain degree of difficulty. SUMMARY OF THE INVENTION 201115659 In order to solve the above-mentioned problem, the main purpose of the present invention is to encapsulate the ancient, earth & method and structure of the back wafer stack, and control six or more in the die bonding process. Wafer thicker & ^ recognition. Thickness consistency, reducing operational complexity to reduce wafer breakage. The second object of the present invention is to provide a packaging method and structure for a back-to-back chip stack, and ± west is mainly for the case of six or more wafers stacked to control the wire arc of the wire-making process. Same degree to reduce the occurrence of the squall line. A further object of the present invention is to provide a method and structure for packaging a back-to-back wafer stack, which is designed to reduce the manufacturing process and increase the throughput (υρΗ) when stacking six or more wafers. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a method for packaging a back-to-back wafer stack [mainly] comprising the steps of: providing a circuit substrate having a first slot and a second slot, the circuit substrate being between the first slot and the second slot Formed as a central load-bearing portion and a peripheral plate portion outside the first slot and the second slot. Forming a chip-oriented group: the central carrier portion of the circuit substrate, wherein the facing chip group is composed of a plurality of first wafers stacked by a "z" sub-shape and one or more second wafers, wherein the An active surface of a wafer faces the circuit substrate and is biased toward the first slot, so that a plurality of first solder pads of the first wafers are aligned in the first slot, and active surfaces of the second wafers And facing the circuit substrate and biasing the second slot to align the plurality of second pads of the second wafers in the second slot. Conduct a first line 201115659
步驟’形成複數個第一銲線與複數個第二銲線，該些第 一銲線係通過該第一槽孔電性連接該些第一晶片之第一 銲墊至該電路基板，該些第二銲線係通過該第二槽孔電 性連接該些第二晶片之第二銲墊至該電路基板。設置一 背向晶片組於該面向晶片組之一晶片背面，其中該背向 晶片組係由「ζ」字形堆疊之複數個第三晶片與一個或一 個以上的第四晶片所組成，其中該些第三晶片之主動面 係遠離該電路基板且偏向該第二槽孔，以使該些第三晶 片之複數個第三銲墊與該些第二銲墊對齊，該些第四晶 片之主動面係遠離該電路基板且偏向該第一槽孔，以使 該些第四晶片之複數個第四銲墊與該些第一銲墊對齊。 進行一第二打線步驟，形成複數個第三銲線與複數個第 四銲線，該些第三銲線係電性連接該些第三晶片之第= “整至該電路基板’該些第四銲線係電性連接該些第四 晶片之第四銲墊至該電路基板。本發明另揭示依照該方 法所製成之構造。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之背對背晶片組堆疊的封裝方法中，該面向晶 片組與該背向晶片組之「Ζ」字形堆疊型態恰可為鏡像對 稱。 在前述之背對背晶片組堆疊的封裝方法中，該電路基 板係可具有複數個供該些第一銲線連接之第一接指、複 數個供該些第二銲線連接之第二接指、複數個供=些考 5 201115659 三銲線連接之第三接指以及複數個供 '、吟些第録 之第四接指，其中該些第-接指與該鮮線連接 ^第二接指得設置 於該中央承載部，該些第三接指盥 相竹成罝 ^ 二第四接指係設置 於該周邊板部。 在前述之背對背晶片組堆疊的封 可裝方法中，可另包含 之步驟為：形成一封膠體於該電路美 « ^ ^ . . 土 上與該第一槽孔 及第一槽孔内，以密封該面向晶片組、 ^ >ter 46 k者向晶片組、 該二第一紅線、該些第二銲線、該此 四銲線。 —第二銲線及該些第 在前述之背對背晶片組堆疊的封 万法中，可另包含 之步驟為：設置複數個銲球於該 ,.^ ^ , 电峪基板之顯露表面， 以構成固口型球柵陣列（wBGA)之封裝型熊 在前述之背對背晶片組堆叠的封裝方二，該些第一 的片、該些第二晶片、該歧第=曰 ^ —第—曰日片以及該些第四晶片 你J為實質相同之側排銲墊晶片。 由以上技術方案可以看出，本發明+北 晶认 不赞明之背對背晶片組堆 、封裴方法與構造，有以下優點與功效： - '可藉由先設置面向晶片組與第—打線步驟再設置 背向晶>1組與第二打線步驟作為其中一技術手段， 在點晶過程中能控制晶片厚度m降低作業 -上的複雜性，以減少發生晶片斷裂之情況。 -'可藉由先設置面向晶片組與第一打線步驟，再設置 =向阳>1組與第二打線步驟作為其中一技術手段， 控制打線製程之線弧高度’以減少甩線情形之發 201115659 生。 三、可藉由先設置面向晶片組與第一打線步驟，再設置 背向晶片組與第二打線步驟作為其中一技術手段， 可大幅地縮短製造過程，提升產能（Uph)。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是’該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 籲有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 清楚的描述，實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種背對背晶片組堆 疊的封裝方法與構造舉例說明於第1圖之流程方塊圖與 Φ 第2A至21圖在製程中之元件截面示意圖。該背詞背晶 片組堆疊的封裝方法根據第1圖，主要包含以下步驟： 「提供電路基板」之步驟丨、「設置面向晶片組於電路基 板之中央承栽部」之步驟2、「進行第一打線」之步驟3、 * 老向Ba片組於面向晶片組之晶片背面」之步驟 進行第一打線」之步驟5、「形成封膠體」之步驟6 以及設置銲球於電路基板之顯露表面」之步驟7，詳 細步驟請參閱第2A至21圖，說明如下所示。 首先，執行步驟1。如第2A圖所示，提供_電路基 r 201115659 板210 ’係具有一第一槽孔211以及一第二槽孔212。該 第一槽孔211與該第二槽孔212係為非中央設置。該電 路基板210在該第一槽孔211與該第二槽孔212之間形 成為一中央承載部213以及在該第一槽孔211與該第二 槽孔212之外之一周邊板部214。在一較佳實施例中， 該電路基板210係可為一印刷電路板（printed circuh board，PCB) ’並可具有兩面導通之線路結構。The step of forming a plurality of first bonding wires and a plurality of second bonding wires, the first bonding wires electrically connecting the first pads of the first wafers to the circuit substrate through the first slots, The second bonding wire is electrically connected to the second pad of the second wafer to the circuit substrate through the second slot. Having a backing wafer set on a back side of one of the wafer facing wafer groups, wherein the backing wafer group is composed of a plurality of third wafers stacked in a U shape and one or more fourth wafers, wherein the The active surface of the third wafer is away from the circuit substrate and is biased toward the second slot, so that a plurality of third pads of the third wafer are aligned with the second pads, and the active surfaces of the fourth wafers And being away from the circuit substrate and biased toward the first slot, so that a plurality of fourth pads of the fourth wafer are aligned with the first pads. Performing a second wire bonding step to form a plurality of third bonding wires and a plurality of fourth bonding wires, wherein the third bonding wires are electrically connected to the third semiconductor chip = "to the circuit substrate" The fourth bonding wire is electrically connected to the fourth bonding pad of the fourth wafer to the circuit substrate. The invention further discloses a configuration made according to the method. The object of the present invention and solving the technical problem thereof can also adopt the following technical measures. Further, in the foregoing packaging method of the back-to-back wafer stack, the "Ζ"-shaped stacked pattern of the wafer facing group and the back facing wafer group may be mirror symmetrical. In the above-mentioned package method of the back-to-back wafer stack, the circuit substrate may have a plurality of first fingers for connecting the first bonding wires, and a plurality of second fingers for connecting the second bonding wires, A plurality of supplies for the test 5 201115659 The third finger of the three wire bond connection and a plurality of the fourth finger for the ', the number of the fourth finger, wherein the first finger is connected with the fresh wire ^ the second finger The third connecting finger is disposed on the central carrying portion, and the third connecting fingers are disposed on the peripheral plate portion. In the foregoing method for sealing the back-to-back wafer stack, the method further comprises the steps of: forming a gel on the circuit and the first slot and the first slot to The wafer-facing, ^ > ter 46 k-direction wafer set, the two first red lines, the second solder lines, and the four bonding lines are sealed. The second bonding wire and the sealing method of the back-to-back wafer stack of the foregoing may further comprise the steps of: setting a plurality of solder balls on the exposed surface of the substrate, to form A package type bear of a solid-state ball grid array (wBGA) is packaged on the back-to-back chip stack of the foregoing, and the first piece, the second chip, and the second chip And the fourth wafers, which are substantially the same side row pad wafers. It can be seen from the above technical solution that the present invention + Beijing recognizes the back-to-back wafer stack, sealing method and structure, and has the following advantages and effects: - 'By setting the face-to-chip group and the first-line step first The reverse crystal > 1 group and the second wire bonding step are provided as one of the technical means for controlling the wafer thickness m to reduce the operational-on-complication during the spotting process to reduce the occurrence of wafer breakage. - 'By setting the face-to-chip group and the first wire-punching step, then setting the =sunward>1 group and the second wire-laying step as one of the technical means to control the wire arc height of the wire-making process to reduce the occurrence of the wire-line condition 201115659 Born. 3. The manufacturing process can be greatly shortened and the throughput (Uph) can be greatly improved by first setting the face-to-chip group and the first wire bonding step, and then setting the back-to-wafer group and the second wire bonding step as one of the technical means. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, in which Therefore, only the components and combinations related to this case are displayed. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. In order to provide a clearer description, the actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a method and structure for packaging a back-to-back wafer stack is illustrated in the flow block diagram of FIG. 1 and a cross-sectional view of the components of the Φ 2A through 21 process. According to the first diagram, the packaging method of the back-end chip stack is mainly composed of the following steps: "Providing a circuit board", "Steps of providing a central processing unit for a chipset on a circuit board" Step 3 of the "One-line" step, "Steps to perform the first bonding of the steps of the Wa chip group on the wafer facing the chipset", Step 6 of "Forming the encapsulant", and setting the exposed surface of the solder ball on the circuit substrate Step 7, for detailed steps, please refer to Figures 2A-21, as explained below. First, go to step 1. As shown in FIG. 2A, the circuit board r 201115659 is provided with a first slot 211 and a second slot 212. The first slot 211 and the second slot 212 are non-central. The circuit board 210 is formed as a central bearing portion 213 between the first slot 211 and the second slot 212, and a peripheral plate portion 214 outside the first slot 211 and the second slot 212. . In a preferred embodiment, the circuit substrate 210 can be a printed circuit board (PCB) and can have a two-sided conductive line structure.
接著，執行步驟2。如第2B與2C圖所示，設置一面 向晶片組220於該電路基板21〇之該中央承載部213， 其中該面向晶片組220係由複數個第一晶片22 j與一個 或一個以上的第二晶片222所組成。該些第一晶片22 i 與該第一日日片222為「Z」字形堆疊（zigZag)，或稱「之」 字形或是曲折堆疊。其中，該些第一晶片221之主動面 221B係朝向該電路基板21〇且偏向該第—槽孔2ΐι，以 使該些第一晶片221之複數個第一鋅墊221A對準於該 第一槽孔211内。該些第二晶片222之主動面222B係朝 向該電路基板210且偏向該第二槽孔212，以使該些第 二晶片222之複數個第二銲墊222A對準於該第二槽孔 212内。雖如第28圖所示，該些第一晶片221與該些第 二晶片222以由下往上的方式反向接合至該電路基板 210,將該些第一晶片221與該些第二晶片222係逐一黏 著於該電路基mo。實際上是在黏晶機台時該電路基 板210先旋轉180度由上往下設置該些第一晶片221與 該些第二晶片222。在移動到打線機台時，再將該電路 201115659 基板210轉土。在一較佳實施例中，該些第一晶片22ι 與該些第二晶片222之總數至少為四個晶片之組合。在 本實施例中，該些第二晶片222的數量為二，與該些第 一晶片221的數量相同’以達到八層晶片堆疊。 執行步驟3。如第2D圖所示，藉由—銲針1〇，進行 一第一打線少驟，形成複數個第一銲線23〇與複數個第 二銲線24〇，該些第一銲線230係通過該第一槽孔2ΐι 電性連接該些第一晶片221之第一銲墊221A至該電路 基板21〇,該些第二銲線240係通過該第二槽孔212電 性連接該些第二晶片222之第二銲墊222八至該電路基 板210。具體而言，在此步驟中可重覆進行打線作業， 能輕易地控制打線製程之線弧高度，以減少甩線情形之 發生。此外’在打線過程中’可藉由一加熱板2〇支擇該 些第一晶片221與該些第二晶片如，以抵抗該銲針1〇 對該些第-晶片221與該些第二晶片222所施加的作用 力降避免在打線過程中造成晶片斷裂或鲜不黏(n— ^月況。之後，180度翻轉該電路基板21〇,使該面向晶 片組-之第二…22之一晶片背面223朝上(如第 2E圖所不）’以利後續製程進行。 執行步驟4。如第_2F圖所示，設置一背向晶片 組250於該面向晶片組220之該晶片背面223 背向晶片組25〇係由「z〜 、該 、由z」子形堆疊之複數個第三 25 1與一個或—個 ^ 個以上的第四晶片252 些第三晶片251之##/|57 動面25 1Β係遠離該電路基板210 201115659 且偏向該第二槽孔212，以使該些第三晶片251之複數 個第三銲墊251 A與該些第二銲墊222A對齊，該些第四 晶片252之主動面252B係遠離該電路基板210且偏向Then, go to step 2. As shown in FIGS. 2B and 2C, a central carrier portion 213 facing the chip group 220 is disposed on the circuit substrate 21, wherein the wafer facing group 220 is composed of a plurality of first wafers 22j and one or more The two wafers 222 are composed of. The first wafer 22 i and the first day wafer 222 are a zigzag stack, or a zigzag or zigzag stack. The active surface 221B of the first wafer 221 is directed toward the circuit substrate 21 and is biased toward the first slot 2, so that the plurality of first zinc pads 221A of the first wafers 221 are aligned with the first Inside the slot 211. The active surface 222B of the second wafer 222 faces the circuit substrate 210 and is biased toward the second slot 212 to align the plurality of second pads 222A of the second wafers 222 with the second slots 212. Inside. As shown in FIG. 28, the first wafer 221 and the second wafers 222 are reverse-bonded to the circuit substrate 210 in a bottom-up manner, and the first wafers 221 and the second wafers are formed. The 222 series is adhered to the circuit base mo one by one. In fact, in the die bonding machine, the circuit substrate 210 is rotated 180 degrees to set the first wafer 221 and the second wafers 222 from top to bottom. When moving to the wire machine, the circuit 201115659 substrate 210 is transferred to the earth. In a preferred embodiment, the total number of the first wafers 22i and the second wafers 222 is at least four wafers. In this embodiment, the number of the second wafers 222 is two, which is the same as the number of the first wafers 221 to achieve an eight-layer wafer stack. Go to step 3. As shown in FIG. 2D, a first wire bonding step is performed by the welding pin 1 ,, and a plurality of first bonding wires 23 〇 and a plurality of second bonding wires 24 〇 are formed, and the first bonding wires 230 are The first pads 221A of the first wafers 221 are electrically connected to the circuit board 21A through the first slots 2ΐ, and the second solder lines 240 are electrically connected to the second slots 212. The second pad 222 of the second wafer 222 is connected to the circuit substrate 210. Specifically, in this step, the wire bonding operation can be repeated, and the wire arc height of the wire bonding process can be easily controlled to reduce the occurrence of the wire. In addition, during the wire bonding process, the first wafer 221 and the second wafers may be supported by a heating plate 2, for example, to resist the soldering pins 1 to the first wafers 221 and the second wafers. The force applied by the wafer 222 prevents the wafer from being broken or freshly sticky during the wire bonding process. After that, the circuit substrate 21 is flipped 180 degrees, so that the chip-to-chip group is the second... A wafer back side 223 faces upward (as shown in FIG. 2E) to facilitate subsequent processing. Step 4 is performed. As shown in FIG. 2F, a back wafer group 250 is disposed on the wafer back surface facing the wafer group 220. 223 facing away from the chip set 25 is a plurality of third 251 stacked by "z~, this, by z" sub-shape and one or more than four or more fourth chips 252 of the third wafer 251##/ The movable surface 25 1 is away from the circuit substrate 210 201115659 and is biased toward the second slot 212 to align the plurality of third pads 251 A of the third wafers 251 with the second pads 222A. The active surface 252B of the fourth wafer 252 is away from the circuit substrate 210 and biased
該第一槽孔211 ’以使該些第四晶片252之複數個第四 銲墊252A與該些第一銲墊221A對齊。在一較佳實施例 中’該些第三晶片251與該些第四晶片252之總數至少 為四個晶片之組合’故能與該面向晶片組220形成八層 堆疊之結構。此外’該些第一晶片221、該些第二晶片 222、該些第三晶片251以及該些第四晶片252係可為實 質相同之侧排銲墊晶片。詳細而言，如第2F圖所示，此 步驟係以正面設置該些第三晶片251與該些第四晶片 252，以由上往下的方式逐一堆疊於該面向晶片組22〇 上。在本實施例中，該面向晶片組22〇與該背向晶片組 250之「Z」字形堆疊型態恰可為鏡像對稱。更具體地， 該面向晶片組220與該背向晶片組25〇之間的黏著面即 可作為彼此的對稱面。 執行步驟5。如第2G圖所示，藉由該銲針1〇，進个 一第二打線步驟，形成複數個第三銲線26〇與複數個驾 四銲線270，該些第三銲線260係電性連接該些第三盖 片251之第三銲墊251A至該電路基板21〇，該些第四姿 252之第四銲墊252A ’該電路基板210係 230連接之第一接指 線270係電性連接該些第四晶片 至該電路基板210。在本實施例中 可具有複數個供該些第一銲線 215、複數個供該些第二銲線24〇連接 伐心弟一接指216、 Γ 10 201115659 複數個供該些第三銲線_連接之第三接指217以及複 數個供該些第四銲線270連接之第四接# 218，其中該 些第一接指215與該些第二接指216係設置於該中央承 載部213，該些第二接指217與該些第四接指us係設 置於該周邊板部214。因此’該面向晶片组22〇係電性 連接至該電路基板210之該中央承載部213 ’而該背向 晶片組250係電性連接至該電路基板21〇之該周邊板部 214。此外，該上述第二打線步驟中，可藉由一加熱板 30支撐該電路基板21〇,並且該加熱板係形成有複數 個鏤空區31，以避免該加熱板30碰觸至該些第一銲線 230、該些第二銲線24〇、該些第一接指215與該些第二 接指2 1 6。 執行步驟6。如第2H圖所示，形成一封膠體28〇於 該電路基板210上與該第一槽孔211及第二槽孔212 内’以密封該面向晶片組220、該背向晶片組25〇、該些 _ 第一銲線230、該些第二銲線24〇、該些第三銲線260 及該些第四銲線270。具體而言，該封膠體2 80並未完 全包覆該電路基板210，以使該電路基板210具有可供 外界連接之表面。 最後，執行步驟7。如第21圖所示，設置複數個銲 球290於該電路基板210之顯露表面，以構成窗口型球 柵陣列（window ball grid array, wBGA)之封裝型態，並藉 由該些銲球290提供充分數量之輸入/輸出連結端（I/〇 connecting terminal)，以符合高密度表面接合的需求。 11 201115659 在本發明中，利用先設置面向晶片組與進行第一打線 ㈣’再設置背向晶片組與進行第二打線步驟作為其中 -技術手段’在黏晶過程中，能控制晶片厚度的一致性, 降低作業上的複雜性’以減少發生晶片斷裂咖⑻ 之T況。此外’本發明為了能順利地堆疊六層' 八層或 數量更多的晶片’而將其區分為該面向晶片組22〇與該 背向晶片組250’並分別使該面向晶片組22()與該背向/ 晶片組250至少包含有三個晶片，再先後各別進‘兩次 打線製程，於每次打線製程中，皆為連續實施不需要有 黏晶動作，除了能輕易地控制線弧高度之外，亦毋須擔 心堆疊越高越容易發生甩線之情形而導致報廢。因此， 免除了以往六層以上堆疊使用正面堆疊的方式必項要 重覆進行六次以上的重覆黏晶與打線的繁璃步驟，：幅 地縮短了封裝流程，更提升整體的產能（upH)。 本發明還揭示使用前述方法所製成之背對背晶片组 堆疊的封裝構造舉例說㈣第21圖。該背對背晶片組堆 疊的封裝構造係主要包含一電路基板21〇、—面向晶片 組220、複數個第一銲線230、複數個第二銲線240的一 背向晶片、组250、複數個第三銲線26〇以及 銲線270 〇 ^ 該電路基板210係具有一第—槽孔2ιι以及一第二槽 孔⑴，該電路基板210在該第一槽孔2ιι與該第: 孔川之間形成為一中央承載部213以及在該 2U與該第二槽孔212之外之—周邊板部214。在^佳 12 201115659 實施例中，該電路基板210係可為一印刷電路板（pHnted circuit board，PCB)。 該面向晶片組220係設置於該電路基板21〇之該中央 承載部213,其中該面向晶片組22〇係由「z」字形堆疊 之複數個第一晶片221與一個或一個以上的第二晶片 222所組成’其中該些第一晶片221之主動面係朝向該 電路基板210且偏向該第一槽孔211，以使該些第一晶 片221之複數個第一銲墊221A對準於該第一槽孔 内’該些第二晶片222之主動面係朝向該電路基板21〇 且偏向該第二槽孔212，以使該些第二晶片222之複數 個第二銲墊222A對準於該第二槽孔212内。 該些第一銲線230係通過該第一槽孔211電性連接該 些第一晶片221之第一銲墊221A至該電路基板2ι〇,該 些第二銲線240係通過該第二槽孔212電性連接該些第 二晶片222之第二銲墊222A至該電路基板21〇β 該背向晶片組250係設置於該面向晶片組22〇之一晶 片背面，其中該背向晶片组25〇係由「ζ」字形堆叠之複 數個第三晶月251與一個或一個以上的第四晶片252所 組成’其中該些第三晶片251之主動面係遠離該電路基 板210且偏向該第二槽孔2丨2,以使該些第三晶片ay 之複數個第三銲墊25 1Α與該些第二銲墊222Α對齊該 些第四晶片252之主動面係遠離該電路基板21〇且偏向 該第一槽孔211，以使該些第四晶片252之複數個第四 銲墊252Α與該些第一銲墊221Α對齊。具體而言，該面 13 201115659 向晶片組220與該背向晶片組250之「Zj字形堆疊型態 恰可為鏡像對稱。此外，該些第一晶片2 21、該些第二 晶片222 '該些第三晶片251以及該些第四晶片252係 可為實質相同之側排銲墊晶片。 該些第三銲線260係電性連接該些第三晶片251之第 二銲墊251A至該電路基板210,該些第四銲線270係電 性連接該些第四晶片252之第四銲墊252A至該電路基 板210。在本實施例中，該電路基板210係可具有複數 個供該些第一銲線230連接之第一接指215、複數個供 該些第二銲線240連接之第二接指216、複數個供該些 第三銲線260連接之第三接指217以及複數個供該些第 四銲線270連接之第四接指218’其中該些第一接指215 與該些第一接指216係設置於該中央承載部213，該些 第二接指217與該些第四接指218係設置於該周邊板部 214 ° • 此外’可另包含一封膠體280,係形成於該電路基板 210上與該第一槽孔211及第二槽孔212内，以密封該 面向晶片組220 '該背向晶片組250、該些第一銲線23〇、 該些第二銲線240、該些第三銲線260及該些第四銲線 270。並且’可另包含複數個銲球290，係設置於該電路 基板210之顯露表面，以構成窗口型球柵陣列 ball grid array, wBga)之封裝型態。 以上所述，僅是本發明的較佳實施例而已，並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 14 201115659 揭露如上，辦^、 、、、 α限定本發明，任何熟悉本項技 術者’在不脫離本發明 技術範圍内，所作的任何簡單 L改 等效性變化盘修你 ,, 內〇 >、仏飾，均仍屬於本發明的技術範圍 【圖式簡單說明】 第1圖.依據本發明之—具體實施例的一種背對背β曰片 組堆疊的封裝方法之方塊流程圖。 日日The first slot 211' is such that a plurality of fourth pads 252A of the fourth wafers 252 are aligned with the first pads 221A. In a preferred embodiment, the third wafer 251 and the fourth wafer 252 have a total of at least four wafers combined to form an eight-layer stacked structure with the wafer-facing wafer 220. Further, the first wafer 221, the second wafers 222, the third wafers 251, and the fourth wafers 252 may be substantially identical side row pad wafers. In detail, as shown in FIG. 2F, the third wafer 251 and the fourth wafers 252 are disposed on the front side to be stacked one by one on the wafer facing group 22 from top to bottom. In the present embodiment, the "Z"-shaped stacked pattern of the wafer-facing wafer stack 22 and the back-facing wafer stack 250 may be mirror-symmetrical. More specifically, the adhesive faces between the wafer-facing wafer set 220 and the back-facing wafer set 25A can serve as symmetry planes to each other. Go to step 5. As shown in FIG. 2G, by the soldering pin 1 〇, a second wire bonding step is formed to form a plurality of third bonding wires 26 〇 and a plurality of driving four bonding wires 270, and the third bonding wires 260 are electrically connected. The third pad 251A of the third cover 251 is connected to the circuit substrate 21A, and the fourth pad 252A of the fourth posture 252 is connected to the first finger line 270 of the circuit substrate 210. The fourth wafers are electrically connected to the circuit substrate 210. In this embodiment, there may be a plurality of the first bonding wires 215, a plurality of the second bonding wires 24, and the connecting wires 216, Γ 10 201115659, and the plurality of the third bonding wires. The third connecting finger 217 and the fourth connecting terminal 218 for connecting the fourth bonding wires 270, wherein the first connecting fingers 215 and the second connecting fingers 216 are disposed on the central carrying portion 213. The second fingers 217 and the fourth fingers are disposed on the peripheral plate portion 214. Therefore, the facing wafer set 22 is electrically connected to the central carrying portion 213' of the circuit substrate 210, and the backing wafer set 250 is electrically connected to the peripheral plate portion 214 of the circuit substrate 21A. In addition, in the second wire bonding step, the circuit substrate 21 is supported by a heating plate 30, and the heating plate is formed with a plurality of hollow regions 31 to prevent the heating plate 30 from touching the first The bonding wire 230, the second bonding wires 24, the first fingers 215 and the second fingers 2 16 . Go to step 6. As shown in FIG. 2H, a glue body 28 is formed on the circuit substrate 210 and the first slot 211 and the second slot 212 to seal the wafer facing group 220 and the back wafer group 25, The first bonding wires 230, the second bonding wires 24, the third bonding wires 260, and the fourth bonding wires 270. Specifically, the encapsulant 280 does not completely cover the circuit substrate 210 such that the circuit substrate 210 has a surface that can be connected to the outside. Finally, perform step 7. As shown in FIG. 21, a plurality of solder balls 290 are disposed on the exposed surface of the circuit substrate 210 to form a package type of a window ball grid array (WBGA), and the solder balls 290 are formed by the solder balls 290. A sufficient number of I/〇 connecting terminals are provided to meet the requirements of high density surface bonding. 11 201115659 In the present invention, the wafer thickness can be controlled by first setting the facing wafer group and performing the first bonding (4) 'resetting the backing wafer group and performing the second wiring step as the technical means' in the die bonding process. Sex, reduce the complexity of the job 'to reduce the occurrence of wafer breakage coffee (8) T condition. In addition, the present invention divides the six-layer 'eight layers or a larger number of wafers' into the wafer-facing group 22 and the back-to-wafer group 250' and makes the wafer-facing group 22() The back/wafer set 250 includes at least three wafers, and then successively enters the 'two-line processing process. In each of the wire-bonding processes, continuous implementation does not require a die-bonding action, except that the line arc can be easily controlled. Beyond the height, there is no need to worry about the fact that the higher the stack, the more likely it is to be smashed and the result is scrapped. Therefore, it is necessary to repeat the process of re-adhesive bonding and wire-laying for more than six times in the past six or more layers of stacking. The width of the package shortens the packaging process and improves the overall capacity (upH). . The present invention also discloses a package structure of a back-to-back wafer stack formed by the foregoing method, which is illustrated in Fig. 21 (4). The package structure of the back-to-back chip stack is mainly composed of a circuit substrate 21, a wafer facing group 220, a plurality of first bonding wires 230, a plurality of second bonding wires 240, a back wafer, a group 250, and a plurality of The third bonding wire 26 〇 and the bonding wire 270 〇 ^ The circuit substrate 210 has a first slot 2 ιι and a second slot (1), the circuit substrate 210 between the first slot 2 ιι and the first: Kongchuan Formed as a central carrying portion 213 and a peripheral plate portion 214 outside the 2U and the second slot 212. In the embodiment of the present invention, the circuit substrate 210 can be a printed circuit board (PCB). The wafer facing group 220 is disposed on the central carrying portion 213 of the circuit substrate 21, wherein the facing wafer group 22 is a plurality of first wafers 221 and one or more second wafers stacked in a zigzag shape. The 222 is formed by the active surface of the first wafers 221 facing the circuit substrate 210 and biased toward the first slot 211, so that the plurality of first pads 221A of the first wafers 221 are aligned with the first The active surface of the second wafer 222 in a slot is directed toward the circuit substrate 21 and is biased toward the second slot 212 to align the plurality of second pads 222A of the second wafers 222. The second slot 212 is inside. The first bonding wires 230 are electrically connected to the first pads 221A of the first wafers 221 to the circuit substrate 2 ι through the first slots 211 , and the second bonding wires 240 pass through the second slots The hole 212 is electrically connected to the second pad 222A of the second wafer 222 to the circuit substrate 21β. The back wafer group 250 is disposed on the back surface of the wafer facing the wafer group 22, wherein the back wafer group The 〇 is composed of a plurality of third crystal 251 stacked in a "ζ" shape and one or more fourth wafers 252. The active surfaces of the third wafers 251 are away from the circuit substrate 210 and are biased toward the first Two slots 2丨2, such that the plurality of third pads 25 1Α of the third wafer ay are aligned with the second pads 222 该, and the active surfaces of the fourth wafers 252 are away from the circuit substrate 21 and The first slot 211 is biased to align the plurality of fourth pads 252 该 of the fourth wafers 252 with the first pads 221 . Specifically, the "Zj-shaped stacked pattern of the surface 13 201115659 to the wafer set 220 and the back-facing wafer set 250 may be mirror-symmetrical. In addition, the first wafers 2 21 and the second wafers 222 ' The third wafer 251 and the fourth wafer 252 are substantially the same side row pad wafers. The third bonding wires 260 are electrically connected to the second pads 251A of the third wafers 251 to the circuit. The fourth bonding wire 270 is electrically connected to the fourth pad 252A of the fourth die 252 to the circuit substrate 210. In this embodiment, the circuit substrate 210 can have a plurality of a first finger 215 connected to the first bonding wire 230, a plurality of second fingers 216 connected to the second bonding wires 240, a plurality of third fingers 217 connected to the third bonding wires 260, and plural The fourth finger 218 ′ is connected to the fourth bonding wires 270 , wherein the first fingers 215 and the first fingers 216 are disposed on the central bearing portion 213 , and the second fingers 217 are The fourth fingers 218 are disposed on the peripheral plate portion 214 ° • In addition, a further colloid 280 may be included, which is formed in The circuit board 210 is disposed on the first slot 211 and the second slot 212 to seal the facing chip set 220', the backing chip set 250, the first bonding wires 23, and the second bonding wires 240. The third bonding wires 260 and the fourth bonding wires 270, and 'may additionally include a plurality of solder balls 290 disposed on the exposed surface of the circuit substrate 210 to form a window grid array. wBga) The package type described above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, although the present invention has been disclosed in the preferred embodiment 14 201115659, And α define the present invention, and any person skilled in the art 'receives any simple L-change equivalence changes made by the present invention without departing from the technical scope of the present invention, and 〇 〇 仏 仏 仏 仏 仏Technical Field of the Invention [Simplified Description of the Drawings] FIG. 1 is a block flow diagram of a packaging method of a back-to-back β-chip stack according to an embodiment of the present invention.
第2Α至21圖：依據本發明之-具體實施例的背辦背晶 片組堆疊的封裝方法之元件截面示意圖。 【主要元件符號說明】 步驟1提供電路基板 步驟2設置面向晶片組於電路基板之中央承 步驟3料第-打線 步驟4設置背向晶片組於面向晶片組之晶片背面 步驟5進行第二打線 步驟6形成封膠體 ^ m 7 設置銲球於電路基板之顯露表面 20加熱板 31鏤空區 10 銲針 30 加熱板 210電路基板 211第一槽孔 213中央承載部 2 1 5第一接指 2 1 7第三接指 212 214 216 218 第二槽孔 周邊板部 第二接指 第四接指 15 201115659 " 220面向晶片組 ' 221第一晶片 221B 主動面 222第二晶片 222B 主動面 223 晶片背面 230 第一銲線 250背向晶片組 # 251第三晶片 251B 主動面 252第四晶片 252B 主動面 260 第三銲線 280 封膠體 221A第一銲墊 222A第二銲墊 240 第二銲線 251 A第三銲墊 252A第四銲墊 270 第四銲線 290銲球2 to 21 are schematic cross-sectional views showing the components of the package method of the backing wafer stack according to the embodiment of the present invention. [Description of main component symbols] Step 1 provides a circuit substrate. Step 2: Set a chip-oriented group to the center of the circuit substrate. Step 3: Step-to-wire step 4: Set the back-to-wafer group on the chip-facing wafer-side back side Step 5 to perform a second wire bonding step 6 forming a sealant ^ m 7 setting the solder ball on the exposed surface of the circuit substrate 20 heating plate 31 hollowing area 10 soldering pin 30 heating plate 210 circuit substrate 211 first slot 213 central carrying portion 2 1 5 first finger 2 1 7 Third finger 212 214 216 218 second slot peripheral plate portion second finger fourth finger 15 201115659 " 220 facing the chip set '221 first wafer 221B active surface 222 second wafer 222B active surface 223 wafer back surface 230 The first bonding wire 250 faces away from the wafer set # 251, the third wafer 251B, the active surface 252, the fourth wafer 252B, the active surface 260, the third bonding wire 280, the sealing body 221A, the first bonding pad 222A, the second bonding pad 240, the second bonding wire 251 A Three pads 252A fourth pad 270 fourth wire 290 solder balls
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