201007734 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種記憶體裝置，特別是有關於一種具有訊號轉換模組 • 之快閃記憶體控制裝置。 * 【先前技術】 隨著快閃記憶體的快速發展，各種快閃記憶體規格(例如 NAND(Not ❹AND)快閃記憶體)經常被使用。為了提高ναν〇快閃記憶體的效能另一 種開放式NAND快閃記憶體架構(open nand flash interface，〇nfi)亦被使 用。然而其規格無法與傳統NAND快閃記憶體架構相容，特別是該傳統 NAND純】6己憶趙架構的腳位定義與開放式ΝΑΝ〇快閃記艘架構(〇顺)不 同因此’虽使用傳、统NAND快閃記憶體架構之產品欲改採用開放式nand 快閃記趙架構之規格時必須重新設計，耗時且成本較冑。有蓉於此確有 必要發展一種新式的快閃記憶體裝置，以解決上述問題。 ❹ 【發明内容】 本發明之目触於提供—齡有職轉難組之,_罐體控制裝 置’該訊號轉換模組轉換一快閃記憶體介面至另一快閃記憶體介面，例如 開放式NAND快閃記體架構(ONFI)。 為達成上述目的，本發明提供一種具有訊號轉換模組之快問記憶趙控 制裝置。該快閃_艘控制裝置包括主要控制胃、訊號轉換模組、資料緩 衝器以及次要控制器。 主要控制器依據-第-控制介面，以產生一第一组控制訊號，其中該 201007734 第一組控制訊號包括一讀取致能訊號以及一寫入致能訊號。訊號轉換模組 接收該讀取致能訊號以及該寫入致能訊號，並且依據一第二控制介面，將 該讀取致能訊號以及該寫入致能訊號轉換成為一寫入/讀取訊號。在一實施 例中，當寫入/讀取訊號為高準位時，將資料傳送至快閃記憶體；當寫入/ 讀取訊號為低準位時，將資料由快閃記憶體輸出。 資料緩衝器依據該第一控制介面’以儲存來自該主要控制器的資料， 並且依據該第二控制介面，以儲存來自該快閃記憶體的資料。次要控制器 ¥ 依據該第二控制介面’用以產生第二組控制訊號，其中該第二組控制訊號 包括一時脈訊號以及一栓鎖訊號’並且該次要控制器依據該第二控制介面 傳送該寫入/讀取訊號、該時脈訊號以及該栓鎖訊號，用以讀取來自該快閃 記憶體的資料或是將該資料寫入至該快閃記憶體。 該第一組控制訊號係依據該第一控制介面選自於一命令栓鎖致能訊號 (SCLE)、一晶片致能訊號(/SCE)、一位址栓鎖致能訊號(SALE)以及一寫入 保護訊號(/WP)所組成的族群。該第二組控制訊號係依據該第二控制介面選 自於一命令栓鎖致能訊號(SCLE)、一晶片致能訊號(/SCE)、一位址栓鎖致能 訊號(SALE)以及一寫入保護訊號(/WP)所組成的族群。該次要控制器更包括 依據該第二控制介面接收來自該快閃記憶體之一備妥/忙碌訊號_) 〇該主 要控制器更包括依據該第一控制介面接收來自該次要控制器之該備妥/忙碌 訊號(R/B)。在一實施例中，該第一控制介面係相容於NAND快閃記憶體標 準協定，該第二控制介面係相容於開放式NAND快閃記體架構(ONFI)之標 準協定。 201007734 為讓本發明之上述内容能更明顯易僅，下文特舉較佳實施例，並配合 所附圖式，作詳細說明如下： 【實施方式】 第1圖係依據本發明-實施辦具有訊號轉換模組1〇4之快閃記憶體 控制裳置100之方塊圖。該快閃記憶想控制裝置100包括主要控制器1〇2、 訊號轉換模組104、資料緩衝器106以及次要控制器1〇8。在一實施例中， ❿該快閃記憶體控制裝置1〇〇，用以控制一 ΝΑΝ〇快閃記憶趙。訊號轉換模 組1〇4耦接於該主要控制器102與該次要控制器1〇8之間。資料緩衝器1〇6 麵接該主要控網1G2至該次要控繼1〇8,該次要控網1G8#接至該快 閃記憶體110。 主要控制器102依據-第-控制介面，以產生一第一組控制訊號，其 中該第一組控制訊號包括一讀取致能訊號以及一寫入致能訊號。訊號轉換 模組104接收該讀取致能訊號以及該寫入致能訊號，並且依據一第二控制 〇 介面’將該讀取致能訊號以及該寫入致能訊號轉換成為一寫入/讀取訊號。 在實施例中，當寫入/讀取訊號為高準位時，將資料傳送至快閃記憶體 110，w寫入/讀取訊號為低準位時’將資料由快閃記憶體11〇輸出。 資料緩衝器106依據該第一控制介面，以儲存來自該主要控制器1〇2 的資料，並且依據該第二控制介面，以儲存來自該快閃記憶體11〇的資料。 次要控制器108依據該第二控制介面，用以產生第二組控制訊號，其中該 第二組控制訊號包括一時脈訊號以及一栓鎖訊號，並且該次要控制器108 依據該第二控制介面傳送該寫入/讀取訊號、該時脈訊號以及該栓鎖訊號， 201007734 用以讀取來自該快閃記憶體110的資料或是將該資料寫入至該快閃記憶體 110。在一實施例中，該時脈訊號用以栓鎖命令以及位址。在資料傳收處理 期間，該栓鎖訊號的上升緣以及下降緣例如是相對應於一資料位元。 該第一組控制訊號係依據該第一控制介面選自於一命令栓鎖致能訊號 (SCLE)、一晶片致能訊號(/SCE)、一位址栓鎖致能訊號(SALE)以及一寫入 保護訊號(/WP)所組成的族群。該第二組控制訊號係依據該第二控制介面選 自於一命令栓鎖致能訊號(SCLE)、一晶片致能訊號(/SCE)、一位址栓鎖致能 訊號(SALE)以及一寫入保護訊號(/WP)所組成的族群。該次要控制器ι〇8更 包括依據該第二控制介面接收來自該快閃記憶體110之一備妥/忙碌訊號 (R/B)。該主要控制器102更包括依據該第一控制介面接收來自該次要控制 器108之該備妥/忙碌訊號(R/B)。在一實施例中，該第一控制介面係相容於 NAND快閃記憶體標準協定，該第二控制介面係相容於開放式NAND快閃 記體架構(ONFI)之標準協定。 參考第1圖以及第2圖，第2圖係依據本發明實施例中基於第一控制 介面利用快閃記憶體控制裝置1〇〇執行非同步讀取程序之時序圖。快閃記 憶想110的第一組控制訊號包括命令栓鎖致能訊號(c〇mmand iatch enable signal，SCLE)、晶片致能訊號(chip enable signal，/SCE)、寫入致能訊號(write enable signal，/SWE)、位址致能訊號(address latch enable signal，SALE)、讀取 致能訊號(read enable signal, /SRE)、輸入/輸出(input/output signal, I/O)訊號、 一寫入保護訊號(WP)以及備妥/忙碌訊號(ready/bUSy signai，r/b) 〇本發明之 非同步係指在執行寫入程序時’利用寫入致能訊號(/SWE)栓鎖資料，而當 201007734 執行讀取程序時，利用讀取致能訊號(/SRE)栓鎖資料。 晶片致能訊號(/SCE)表示當快閃記憶體ι10受到快閃記憶體控制器1〇〇 的次要控制器108激發時’該快閃記憶體no處於致能(active)狀態。例如 當晶片致能訊號(/SCE)處於低準位時，該快閃記憶體110處於致能(active) 狀態。寫入致能訊號(/SWE)表示當寫入致能訊號(/SWE)處於低準位時，該 快閃記憶體控制器100的次要控制器108將資料寫入至該快閃記憶體11〇。 讀取致能訊號(/SRE)表示當讀取致能訊號(/SRE)被激發(例如是低準位) 時’該快閃記億體控制器100的次要控制器108讀取該快閃記憶體11〇内 的資料。當該命令栓鎖致能訊號(SCLE)被激發時，該命令在寫入致能訊號 (/SWE)的上升緣形成栓鎖。當該位址致能訊號巧从玛被激發時，該位址在 寫入致能訊號(/SWE)的上升緣栓鎖。輸入/輸出(1/〇)訊號表示資料傳輸於該 快閃記憶體110與該資料暫存器之間。該預備/忙碌訊號(R/B)表示將該快閃 記憶體的狀態報告給該快閃記憶體控制裝置100之狀態訊號。 參考第1圖以及第3圖，第3圖係依據本發明實施例中基於第二控制 介面利用快閃記憶體控制裝置100執行同步讀取程序之時序圊。快閃記憶 艘110的控制訊號包括命令栓鎖致能訊號(command latch enable signal, SCLE)、晶片致能訊號(chip enable signal，/SCE)、寫入/讀取訊號/(W/R)、位 址致能訊號(address latch enable signal，SALE)、資料栓鎖訊號(DQS)、DQ 訊 號、時脈訊號(CLK)、一寫入保護訊號(/WP)以及備妥/忙碌訊號(ready/busy signal，R/B)。本發明之同步係指在資料被栓鎖時該資料栓鎖訊號(DQS)栓鎖 該資料，亦即該資料栓鎖訊號(DQS)可視為一資料匯流排之控制位元。 201007734 在一實施例中’當寫入/讀取訊號/(W/R)處於低準位時’該次要控制器 108驅動該資料栓鎖訊號(DQS)以及DQ訊號，亦即在同步狀態下之命令、 位址、資料的有效期間(cycle)。當寫入/讀取訊號/(W/R)處於低準位時’該次 要控制器108使該資料栓鎖訊號(DQS)以及DQ訊號禁能(disable)。 時脈訊號用以作為資料同步傳輸介面的控制時脈，例如分享使用第一 控制介面的寫入致能訊號(/SWE)，寫入保護訊號(/WP)用以使該快閃記憶體 的程式化(program)或是抹除(erase)#作禁能。該預備/忙碌訊號(R/B)表示將 ❹201007734 IX. Description of the Invention: [Technical Field] The present invention relates to a memory device, and more particularly to a flash memory control device having a signal conversion module. * [Prior Art] With the rapid development of flash memory, various flash memory specifications (such as NAND (Not ❹ AND) flash memory) are often used. In order to improve the performance of ναν〇 flash memory, another open NAND flash memory architecture (〇nfi) is also used. However, its specifications cannot be compatible with the traditional NAND flash memory architecture. In particular, the traditional NAND pure 6-remembered Zhao architecture has different pin definitions than the open-type flash-flash architecture (〇顺). The products of the NAND flash memory architecture must be redesigned when using the specifications of the open nand flash memory architecture, which is time consuming and costly. It is indeed necessary for Rong to develop a new type of flash memory device to solve the above problems. ❹ 发明 发明 本 本 本 本 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ NAND flash record architecture (ONFI). In order to achieve the above object, the present invention provides a quick memory memory control device having a signal conversion module. The flash control device includes a main control stomach, a signal conversion module, a data buffer, and a secondary controller. The primary controller is configured to generate a first set of control signals according to the -th control interface, wherein the 201007734 first set of control signals includes a read enable signal and a write enable signal. The signal conversion module receives the read enable signal and the write enable signal, and converts the read enable signal and the write enable signal into a write/read signal according to a second control interface. . In one embodiment, when the write/read signal is at a high level, the data is transferred to the flash memory; when the write/read signal is at a low level, the data is output from the flash memory. The data buffer is configured to store data from the primary controller in accordance with the first control interface and to store data from the flash memory in accordance with the second control interface. The secondary controller is configured to generate a second group of control signals according to the second control interface, wherein the second group of control signals includes a clock signal and a latch signal and the secondary controller is configured according to the second control interface Transmitting the write/read signal, the clock signal, and the latch signal for reading data from the flash memory or writing the data to the flash memory. The first group of control signals is selected from the group consisting of a command latch enable signal (SCLE), a chip enable signal (SCE), an address latch enable signal (SALE), and a first control interface. Write the group of protection signals (/WP). The second control signal is selected from the group consisting of a command latch enable signal (SCLE), a chip enable signal (SCE), a bit latch enable signal (SALE), and a second control interface. Write the group of protection signals (/WP). The secondary controller further includes receiving, according to the second control interface, a ready/busy signal from the flash memory. The primary controller further includes receiving, according to the first control interface, the secondary controller. The ready/busy signal (R/B). In one embodiment, the first control interface is compatible with a NAND flash memory standard protocol that is compatible with the standard protocol of the Open NAND Flash Recorder Architecture (ONFI). 201007734 In order to make the above description of the present invention more obvious, the following description of the preferred embodiments, together with the accompanying drawings, will be described in detail as follows: [Embodiment] FIG. 1 is based on the present invention - the implementation has a signal The flash memory of the conversion module 1〇4 controls the block diagram of the skirt 100. The flash memory control device 100 includes a main controller 1〇2, a signal conversion module 104, a data buffer 106, and a secondary controller 1〇8. In one embodiment, the flash memory control device is configured to control a flash memory. The signal conversion module group 1〇4 is coupled between the main controller 102 and the secondary controller 1〇8. The data buffer 1〇6 is connected to the primary control network 1G2 to the secondary control 1〇8, and the secondary control network 1G8# is connected to the flash memory 110. The primary controller 102 generates a first set of control signals according to the -th control interface, wherein the first set of control signals includes a read enable signal and a write enable signal. The signal conversion module 104 receives the read enable signal and the write enable signal, and converts the read enable signal and the write enable signal into a write/read according to a second control interface Take the signal. In the embodiment, when the write/read signal is at a high level, the data is transferred to the flash memory 110, and when the write/read signal is at a low level, the data is transmitted from the flash memory 11 Output. The data buffer 106 is configured to store data from the primary controller 1〇2 according to the first control interface, and to store data from the flash memory 11〇 according to the second control interface. The secondary controller 108 is configured to generate a second group of control signals according to the second control interface, wherein the second group of control signals includes a clock signal and a latch signal, and the secondary controller 108 is configured according to the second control The interface transmits the write/read signal, the clock signal, and the latch signal, and 201007734 is used to read data from the flash memory 110 or write the data to the flash memory 110. In an embodiment, the clock signal is used to latch a command and an address. During the data transmission process, the rising edge and the falling edge of the latching signal are, for example, corresponding to a data bit. The first group of control signals is selected from the group consisting of a command latch enable signal (SCLE), a chip enable signal (SCE), an address latch enable signal (SALE), and a first control interface. Write the group of protection signals (/WP). The second control signal is selected from the group consisting of a command latch enable signal (SCLE), a chip enable signal (SCE), a bit latch enable signal (SALE), and a second control interface. Write the group of protection signals (/WP). The secondary controller ι 8 further includes receiving a ready/busy signal (R/B) from the flash memory 110 in accordance with the second control interface. The primary controller 102 further includes receiving the ready/busy signal (R/B) from the secondary controller 108 in accordance with the first control interface. In one embodiment, the first control interface is compatible with the NAND flash memory standard protocol, which is compatible with the standard protocol of the Open NAND Flash Recorder Architecture (ONFI). Referring to Figures 1 and 2, FIG. 2 is a timing diagram of the execution of the asynchronous read program by the flash memory control device 1 based on the first control interface in accordance with an embodiment of the present invention. The first set of control signals for flash memory 110 include c〇mmand iatch enable signal (SCLE), chip enable signal (SCE), write enable signal (write enable) Signal, /SWE), address enable signal (SALE), read enable signal (SRE), input/output (I/O) signal, Write protection signal (WP) and ready/busy signal (ready/bUSy signai, r/b) 非 The non-synchronization of the present invention means that the write enable signal (/SWE) is latched when the write process is executed. Data, and when the 201007734 performs the reading process, the data is latched by the read enable signal (/SRE). The wafer enable signal (/SCE) indicates that the flash memory no is in an active state when the flash memory ι 10 is activated by the secondary controller 108 of the flash memory controller 1 。. For example, when the chip enable signal (/SCE) is at a low level, the flash memory 110 is in an active state. The write enable signal (/SWE) indicates that when the write enable signal (/SWE) is at a low level, the secondary controller 108 of the flash memory controller 100 writes data to the flash memory. 11〇. The read enable signal (/SRE) indicates that when the read enable signal (/SRE) is activated (eg, low level), the secondary controller 108 of the flash memory controller 100 reads the flash The data in the memory 11〇. When the command latch enable signal (SCLE) is activated, the command forms a latch on the rising edge of the write enable signal (/SWE). When the address enabling signal is activated from the horse, the address is latched at the rising edge of the write enable signal (/SWE). The input/output (1/〇) signal indicates that data is transmitted between the flash memory 110 and the data register. The preliminary/busy signal (R/B) indicates a status signal for reporting the status of the flash memory to the flash memory control device 100. Referring to Figs. 1 and 3, FIG. 3 is a timing chart for executing a synchronous read program by the flash memory control device 100 based on the second control interface in accordance with an embodiment of the present invention. The control signals of the flash memory boat 110 include a command latch enable signal (SCLE), a chip enable signal (SCE), a write/read signal/(W/R), Address latch enable signal (SALE), data latch signal (DQS), DQ signal, clock signal (CLK), a write protection signal (/WP), and ready/busy signal (ready/ Busy signal, R/B). The synchronization of the present invention means that the data latching signal (DQS) latches the data when the data is latched, that is, the data latching signal (DQS) can be regarded as a control bit of a data bus. 201007734 In an embodiment, when the write/read signal/(W/R) is at a low level, the secondary controller 108 drives the data latch signal (DQS) and the DQ signal, that is, in a synchronized state. The order, address, and period of the data. When the write/read signal/(W/R) is at a low level, the secondary controller 108 disables the data latching signal (DQS) and the DQ signal. The clock signal is used as a control clock of the data synchronous transmission interface, for example, sharing a write enable signal (/SWE) using the first control interface, and writing a protection signal (/WP) for the flash memory. Program or erase # is disabled. The preliminary/busy signal (R/B) indicates that 将
該快閃記憶體的狀態報告給該快閃記憶體控制裝置100之狀態訊號eDQO 至DQ7用於資料同步傳輸之介面，例如作為雙向傳輸埠，以傳輸命令、位 址以及資料。 雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，本 發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍内， 當可作各種之更動與满飾’因此本發明之保護範圍當視後附之申請專利範 園所界定者為準。 【圖式簡單說明】 第1圖係依據本發0月-實施例巾具有訊號轉換模組之快閃記憶體控制 裝置之方塊圖》 第2圖係依據本發明實施例巾基於第一控制介面利用快閃記憶體控制 裝置執行非同步讀取程序之時序圖。 ^ 、依據本發月實施例中基於第二控制介面利用快閃記憶體控制 裝置執行同步讀取程序之時序圖。 201007734 【主要元件符號說明】 主要控制器 資料緩衝器 100快閃記憶體控制裝置 102 104訊號轉換模組 106 108次要控制器 110 快閃記憶體裝置The status of the flash memory is reported to the status signals eDQO to DQ7 of the flash memory control device 100 for the interface for data synchronous transmission, for example, as a two-way transmission to transmit commands, addresses and data. While the present invention has been described above in terms of the preferred embodiments, the invention is not intended to be limited thereto, and the invention may be practiced otherwise without departing from the spirit and scope of the invention. The full scope of the invention is therefore subject to the definition of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a flash memory control device having a signal conversion module according to the present invention. The second embodiment is based on the first control interface according to an embodiment of the present invention. A timing diagram of the asynchronous read program is performed using the flash memory control device. ^. A timing diagram for executing a synchronous read program by using a flash memory control device based on a second control interface in the embodiment of the present month. 201007734 [Main component symbol description] Main controller Data buffer 100 Flash memory control device 102 104 signal conversion module 106 108 Minor controller 110 Flash memory device