201003899 九、發明說明： 【發明所屬之技術領域】 月疋有關於一種非揮發性記憶體⑽⑴e memory，簡稱 NVM)，特 H(RRAM)〇 制疋心—種非揮發性電阻式記憶 【先前技術】 近年來’移動式個人電子設備逐漸流行化，智慧型手 機、數位相機、筆記型電腦與消費型電子產品等的大量使 用’亦使得具備有低耗能及長時間記憶能力的記憶體之需 求量提高；因A，g晴性記憶體的使用量將大幅成長。 非揮發性記憶體是記憶體中的—類，其最主要的特色是當 外加電源關閉後’其記憶體中的資訊儲存内容並不會因此 而消失，可以如同硬碟一般’當力資訊儲存元件來使用。 電阻式記憶體的記憶元件，基本上是由一個可經由電 脈衝施加改變電阻之電阻器及一個電晶體（丨R1 τ)所組成。此 電阻器的結構主要為上電極/絕緣層/下電極，目前具有此可 變電阻特性之絕緣層所使用的材料可見有，呈鈣鈦礦結構 的氧化物（perovskite oxides)及過渡金屬氧化物（transhi〇n metal oxides)等。透過對具有可變電阻特性之絕緣層施加脈 衝偏壓訊號後所產生之立即性的電阻值改變[即，所謂的電 阻轉換效應（resistive switching effect)]，來達到寫入（write ;set)或拭除（erase ; reset)的功能。讀取資料時，則是給予 一小偏壓來讀取其電流值，而相對的高低阻態則可當作記 憶訊號的來源。因此，當抹除之高電阻狀態（HRS)對寫入之 5 201003899 -低電阻狀態（LRS)的比值越高時，便表示記憶體的辨識度越 高。 在呈鈣鈦礦結構的氧化物之RRAM當中，絕緣層可見 有使用镨鈣錳氧（PrCaMn03，簡稱PCMO)、鑭鈣錳氧 (LaCaMn03)，或鉻摻雜锆酸锶（Cr doped SrZr03)，而上、下 電極則可見有使用Pt，或釔鋇銅氧（YBa2Cu307_x，簡稱 YBCO)。雖然此種呈鈣鈦礦結構之氧化物的RRAM具備有 永久性記憶讀寫的功能；然而，鈣鈦礦氧化物屬多元氧化 物，不僅需仰賴高溫製程，此外，與二元氧化物（binary oxides)相比較之下，多元氧化物成分組成亦較難以精確控 制，並且不易在CMOS製程中被引入。 在過渡金屬氧化物之RRAM當中，絕緣層可見有使用 NiOx、CuO、Zr02、Ti02、Hf02等二元氧化物。目前應用 最常見者多以>^0\與CuO為主，而上、下電極則是使用Pt 。雖然此等二元氧化物所構成的RRAM較多元氧化物所構 成者容易控制；然而，二元氧化物所構成之RRAM，如一 " 般傳統的Pt/Ti02/Pt結構，其開啟電場（forming field)與轉 ' 換電壓[(switching voltage)，即，寫入電壓與抹除電壓]，分 別高達2〜3 MV/cm與4〜5 V ;此外，高低電阻狀態分布 較散亂，轉換電流亦高。因此，不僅耗損高、轉換電壓穩 定性不佳，而且辨識度仍有待改進。 經上述說明可知，追求低耗損、高穩定性的轉換電壓 與優異的辨識度，是非揮發性電阻式記憶體相關領域者所 待克服的難題。 6 201003899 【發明内容】 <發明概要> RRAM相關領域者皆知，燈絲理論（fiiarnentary m〇dei) 為目刖RRAM之工作機制的理論之一。燈絲理論主要是被201003899 IX. Description of the invention: [Technical field of invention] Lunar New Year has a non-volatile memory (10) (1)e memory (NVM), special H (RRAM), and a non-volatile resistive memory. In recent years, 'mobile personal electronic devices have become increasingly popular, and the use of smart phones, digital cameras, notebook computers, and consumer electronics products has also made it possible to have low-energy and long-term memory. The amount is increased; the use of A, g and clear memory will increase significantly. Non-volatile memory is a type of memory. Its main feature is that when the external power is turned off, the information stored in the memory will not disappear. It can be like a hard disk. Components are used. The memory element of the resistive memory is basically composed of a resistor that can change the resistance via an electric pulse and a transistor (丨R1 τ). The structure of the resistor is mainly the upper electrode/insulating layer/lower electrode. The materials used for the insulating layer having the variable resistance characteristic can be seen as perovskite oxides and transition metal oxides. (transhi〇n metal oxides) and the like. Writing (set; set) or by applying an immediate resistance value change (ie, a so-called resistive switching effect) generated by applying a pulse bias signal to an insulating layer having a variable resistance characteristic Erase (erase; reset) function. When reading the data, a small bias voltage is applied to read the current value, and the relative high and low resistance states can be used as the source of the memory signal. Therefore, the higher the ratio of the erased high resistance state (HRS) to the written 5 201003899 - low resistance state (LRS), the higher the memory identification. Among the RRAMs of perovskite-structured oxides, erbium-manganese-oxygen (PrCaMnO3, PCMO), lanthanum-manganese-oxygen (LaCaMnO3), or chromium-doped lanthanum zirconate (Cr doped SrZr03) can be found in the insulating layer. On the upper and lower electrodes, Pt, or yttrium copper oxide (YBa2Cu307_x, referred to as YBCO) can be seen. Although such an RRAM having an oxide of a perovskite structure has a permanent memory reading and writing function; however, a perovskite oxide is a multi-oxide, which depends not only on a high-temperature process but also on a binary oxide (binary Oxides) In contrast, the composition of the multi-element oxide is also difficult to precisely control and is not easily introduced in the CMOS process. Among the RRAMs of transition metal oxides, binary oxides such as NiOx, CuO, ZrO2, Ti02, and HfO 2 are used for the insulating layer. At present, the most common applications are mostly >>^0\ and CuO, while the upper and lower electrodes use Pt. Although the RRAM composed of these binary oxides is easier to control than the constituents of the multi-element oxide; however, the RRAM composed of the binary oxide, such as a conventional Pt/Ti02/Pt structure, has an electric field (forming) Field) and turn 'switching voltage, that is, write voltage and erase voltage>, respectively, up to 2~3 MV/cm and 4~5 V; in addition, the high and low resistance state distribution is scattered, switching current Also high. Therefore, not only is the loss high, the conversion voltage is not stable, and the degree of identification still needs to be improved. According to the above description, the pursuit of low-loss, high-stability conversion voltage and excellent identification is a problem to be overcome in the field of non-volatile resistive memory. 6 201003899 [Summary of the Invention] <Summary of the Invention> As is well known in the field of RRAM, filament theory (fiiarnentary m〇dei) is one of the theories for witnessing the working mechanism of RRAM. Filament theory is mainly
過為在氧化物層内具有某些可導電的細絲（filament)。rraM 所套用的燈絲理論之工作機制，是簡單地說明於下。 當氧化物被施予一外加電場時，將使得電流量因其内 部部分導電物質移動、聚集並連接導通而瞬間地激增，其 電阻態亦將因導電絲的傳導而形成低電阻態(LRS ;如)。另 ，在低阻態時提供外加電場，大量電流傳輸通過導電絲亦 酼之產生大量的熱能，將使得導電絲因過熱而斷裂；因此 電阻怨因電流量的驟降而又變回高電阻態（HRS ; 。 此電阻轉換又分為兩类員’ 一為單極型㈣p〇la。，即高電阻 態轉換是由相同極性但不同大小電壓所驅動；另一為雙極 型（bipolar)，其咼低電阻態的轉換是由不同極性電壓所驅動 〇 導電絲的形成主要是仰賴電流驅動離子（如，氧化物内 的陰離子或金屬陽離子）的移動。在一般隨機分佈的晶粒或 $晶質結構情況下，此種離子移動的路徑是散亂分佈，使 得導電4路;^之生成是呈樹枝狀。在每:欠實施寫人/抹除電 壓時所產生的導電絲路徑並非_致；因此，轉換偏壓的穩 定性不佳。 有鑑於前述因導電絲路徑呈樹枝狀散亂分布所致的轉 換偏壓不穩等問題，本發明主要是使用呈柱狀晶粒 7 201003899 (columnar grain)結構、具特定優選結晶性，與具有可變電阻 特性（variable resistanee)的氧化物來作為紀錄高低電阻態的 氧化物層。藉由柱狀晶粒間的平直晶界（grainbQun〜)來提 供電流驅動離子移動時的路徑，進而形成方向性傾向一致 化的導電絲路徑。 <發明目的〉 因此’本發明之目的，即在提供一種非揮發性電 記憶體。 於疋，本發明非揮發性電阻式記憶體，包含：一第— 電極、-形成於該第-電極的第二電極，及—夾置於該第 -、一電極之間的氧化物層。該氧化物層具有電流驅動之 可變電阻特性’且沿著-實質上垂直於其層面的方向是呈 柱狀晶粒結構。該氧化物層之部分柱狀晶粒是呈徑向相互 並列。藉相鄰之柱狀晶粒的晶界作為該氧化物層内之離子 在電流驅動時的移動路徑。 本發明之功效在於，降低非揮發性電阻式記憶體的耗 損，同時提昇其轉換電壓的穩定性與辨識度。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之兩個較佳實施例的詳細說明中，將可 清楚的呈現。 在本發明被詳細描述之前，要注意較，在以下的說 明内容中’類似的元件是以相同的編號來表示。 參閱圖1 ’本發明非揮發性電阻式記憶體之一第一較佳 201003899 實施例包含.一弟一電極2、—形成於該第一電極2的第 ::極二，及一爽置於該第一、二電極2'3之間的氧化物 曰“氣化物層4具有電流驅動之可變電阻特性，且、八著 一實質上垂直於制面的方向χ是呈柱狀晶粒結構。純 化物層4之柱狀晶粒是呈徑向相互並列。藉相鄰之柱狀晶 粒的晶界作為該氧化物層4内之離子在電流驅動時的移動 路徑。 較佳地，本發明該第-較佳實施例更包含-石夕基板5、 -形成於财基板5的鈦層6，及_夾置㈣_ W㈣ 基板5之間的氧㈣層7β適用於本發明該第—較佳實施例 之第一、二電極2、3是由麵（Pt)、Ti、Ag、導電氧化物（如 ’ Ru〇2、YBCO)’或氮化物(如㈣、蘭)所製成，且該第 -電極2是夾置於該氧化物層4與該欽層6之間。在本發 明該第-較佳實施例中，該第二電極3是—由pi製成之 直徑為220 μιη的圓形電極。 此處值得-提的是’本發明主要是利用相鄰柱狀晶粒 間的晶界來作為電流驅動氧空缺移動時的路徑以形成導電 絲’當柱狀晶粒之徑向晶粒尺寸過小時，較無法形成柱狀 晶粒；相對地，過大的柱狀晶粒之徑向晶粒尺寸，在奈米 級微型化的元件應用上，該氧化物層4將無法取得足夠量 的柱狀晶粒’並將因傾向為單一晶粒（single _η)結構而無 法提供來自平直晶界的導電絲路徑。因此，較佳地，該氧 化物層4之柱狀晶粒的徑向晶粒尺寸是介於5 nm〜1〇〇打瓜 之間。在本發明該第一較佳實施例中，該氧化物層4之柱 201003899 狀晶粒的徑向晶粒尺寸約25 nm。 適用於本發明之氧化物層4是由氧化辞(加)或氧化键 ⑺之六方晶結構（HCP則緣絲化物所製成；在本發 月該第-較佳實施财，該氧化物層4是在室溫與城3 W的工作壓力下’經由對一射頻磁控賤鍍系統时 mag崎。n sputteHng㈣叫内的2n〇輕材（圖未示）施予糾 w的輪出功率所完成。 另，當該氧化物層4的厚度不足時，則本發明之元件 整體將因漏電流問題而形成短路；反之，當該氧化物層4 料度過大時，則本發明之整體元件的耗損問題將因操作 時的寫入/抹除電壓過高而相對地增加。因此，較佳地，該 氧化物層4的厚度是介於5nm〜5〇〇nm之間。 此處值得一提的是’當該氧化物層4的厚度較薄時（例 如，100 nm以下），則適合用來作為雙極型電阻式記憶體； 反之，當該氧化物層4的厚度較大（例如，1〇〇 nm以上）時 ，則適合用來作為單極型電阻式記憶體。在本發明該第— 車乂佳實施例中，該氧化物層4的厚度是1〇〇 nm(即，適用於 單極型電阻式記憶體）。 、 參閱圖2，由本發明該第一較佳實施例之掃描式電子顯 微鏡（scanning electron microscope,簡稱 SEM)形貌截面圖 顯示可知，該氧化物層（即，Zn〇)4是呈柱狀晶粒結構。 參閱圖3 ,由本發明該第一較佳實施例之χ射線繞射能 4 圖（X-ray diffraction spectrogram，簡稱 XRD)顯示可知， 該第一較佳實施例之ZnO是具有（0〇2)[即，C軸優選取向 10 201003899 (orientation)]之六方晶相結構，其柱狀晶粒的成長方向是沿 者C轴指向成長。 參閱圖4，由本發明該第一較佳實施例之Zn〇的χ射 線光電子忐瑨圖（X-ray photoelectr〇n spectr〇gram，簡稱 xps)顯示可知，Zn 2p"2訊號峰與Zn 2心訊號峰的鍵能 (binding energy)是分別位於1〇45 3以與1〇22 3以，其兩 者間的鍵能差約23_0 eV，相當於鋅的全氧化態（即，Zn2+) 。因此’本發明該第一較佳實施例之Zn〇 {呈氧化態的絕 緣薄膜，可避免該第一較佳實施例之整體元件因部分金屬 態的鋅而導電，並致使元件因短路而無法使用。 參閱圖5，由本發明該第一較佳實施例之電流對電壓ον)曲 線圖顯示可知 ，在限制電流（咖加 eQmpHa叫為 ％ mA的插作條件下，本發明該第—較佳實施例之開啟電塵及 對應的開啟電場分別僅約3 v與Q 3 Mv/em;而寫人電壓（ 即，write或set)與抹除電壓（即，⑽化或⑻叫分別約為2 v與二、於1 v。與先前技術所提之傳統pt/Ti〇"p"吉構的開 啟電場(2〜3 MV/cm)相比較下’本發明該第一較佳實施例 之開啟電場相對減少許多。 參閱圖6,由本發明該第一較佳實施例之單軸向的W 曲線與電阻對反轉次數曲線圖顯示可知’寫人電壓與抹除 電壓分別集中於i.25 v〜2.35 v之間與請〜〇 75 v之間 ’且轉換電㈣、於2.0 V。顯示出本發明該第—較佳實施例 因呈柱狀晶粒結構@ Zn0而有效地提供了氧空缺在移動時 的均勾路徑，·因此，操作（寫入/抹除）電壓穩定。此外，與 11 201003899 先前技術所提之傳統Pt/TiC^/Pt結構的轉換電壓v)相比較 之下，本發明該第一較佳實施例之整體元件耗損較低。另 ，雖然本發明該第一較佳實施例於起始階段的高電阻態 (HRS)是呈現抖動的趨勢；然而，於第5〇次反轉後的高電 阻態則疋已趨於穩定，且，該第一較佳實施例在抹除的高 電阻態（HRS)對寫入的低電阻態（LRS)之比值已達3〜4個數 量級，亦顯示出整體元件於辨識度上的優異表現。 再參圖1，本發明非揮發性電阻式記憶體之一第二較佳 實施例大致上是相同於該第一較佳實施例。其不同處是在 於’該氧化物層4的厚度約25 nm(即，適用於雙極型電阻 式記憶體）。 參閱圖7,由本發明該第二較佳實施例之穿透式電子顯 微鏡（transmission electron microscope，簡稱 TEM)形貌截面 圖顯示可知’本發明該第二較佳實施例之氧化物層（即， ZnO)4的厚度約25 nm，且呈柱狀晶粒結構。 參閱圖8,由本發明該第二較佳實施例之雙軸向的pv 曲線與電壓對反轉次數曲線圖顯示可知，寫入電壓與抹除 電壓分別集中於0.6 V〜0.8 V之間與-0.4 V〜-0.8 V之間， 且轉換電壓小於1.0 V。此外，與先前技術所提之傳統 Pt/Ti〇2/Pt結構的轉換電壓（5 V)相比較之下，本發明該第二 較佳實施例之整體元件耗損較低。顯示出本發明該第二較 佳實施例因呈柱狀晶粒結構的ZnO而有效地提供了氧空缺 在移動時的均勻路控；因此’操作（寫入/抹除）電壓穩定。 综上所述’本發明非揮發性電阻式記憶體，不僅耗損 12 201003899 低，亦具備有操作電壓穩定度高與優異的辨識度等特點， 確實達到本發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾7皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一正視示意圖，說明本發明非揮發性電阻式記 憶體的一第一較佳實施例； 圖2是一 SEM形貌圖，說明本發明該第—較佳實施例 之橫截面形貌； 圖3是一 XRD分析數據，說明本發明該第—較佳實施 例之一氧化物層（ZnO)的晶體結構； 圖4是一 XPS能譜圖，說明本發明該第—較佳實施例 之ZnO的氧化態； 圖5是-W曲線圖，說明本發明該第—較佳實施例之 開啟電壓、寫入電壓與抹除電壓的狀態； 圖6是-！·ν曲線與電阻對反轉次數曲線圖，說明本發 明該第一較佳實施例之操作穩定性與辨識度； 圖7是一 ΤΕΜ形貌圖’說明本發明該第二較佳實施例 之橫載面形貌；及 圖8是- W曲線與電壓對反轉次數曲線圖，說明本發 明該第二較佳實施例之操作穩定性與辨識度。 13 201003899 【主要元件符號說明】 2 ..........第一電極 3 ..........第二電極 4 ..........氡化物層 5 ..........矽基板 6 ..........鈦層 7 ..........氧化矽層 X..........方向 14It is too much to have some conductive filaments in the oxide layer. The working mechanism of the filament theory applied by rraM is simply explained below. When the oxide is applied with an applied electric field, the amount of current will be instantaneously increased due to the movement, aggregation and connection of the conductive material in the internal portion, and the resistance state will also form a low resistance state (LRS due to conduction of the conductive wire; Such as). In addition, an external electric field is provided in a low-resistance state, and a large amount of current is transmitted through the conductive wire to generate a large amount of thermal energy, which causes the conductive wire to be broken due to overheating; therefore, the resistance is changed back to a high resistance state due to a sudden drop in current amount. (HRS; This resistance conversion is divided into two types of 'one unipolar type (four) p〇la. That is, high resistance state conversion is driven by voltages of the same polarity but different magnitudes; the other is bipolar type, The conversion of the low-resistance state is driven by voltages of different polarities. The formation of the conductive filaments is mainly dependent on the movement of the current-driven ions (eg, anions or metal cations within the oxide). Generally, randomly distributed grains or crystals In the case of a qualitative structure, the path of such ion movement is scattered and distributed, so that the conduction is 4; the formation of the ^ is dendritic. The path of the conductive wire generated when the write/erase voltage is not implemented is not Therefore, the stability of the switching bias is not good. In view of the above-mentioned problem that the switching bias is unstable due to the dendritic dispersion of the conductive wire path, the present invention mainly uses the columnar crystal grain 7 201003899 (columnar grain) structure, with specific preferred crystallinity, and an oxide having variable resistanee as an oxide layer for recording high and low resistance states. By straight grain boundaries between columnar grains (grainbQun ~) to provide a path for current-driven ion movement, and to form a conductive fiber path in which the directional tendency is uniform. <Object of the Invention> Therefore, the object of the present invention is to provide a non-volatile electrical memory. The non-volatile resistive memory of the present invention comprises: a first electrode, a second electrode formed on the first electrode, and an oxide layer interposed between the first electrode and the first electrode. The layer has a current-driven varistor characteristic 'and a columnar grain structure along a direction substantially perpendicular to its layer. Part of the columnar grains of the oxide layer are juxtaposed in a radial direction. The grain boundary of the columnar crystal grains serves as a moving path of ions in the oxide layer when driven by current. The effect of the present invention is to reduce the loss of the non-volatile resistive memory while improving the conversion thereof. The above-mentioned and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention. Before the present invention is described in detail, it is to be noted that in the following description, 'similar elements are denoted by the same reference numerals. Referring to FIG. 1 'The first preferred non-volatile resistive memory of the present invention is 201003899 The embodiment comprises: a first electrode, a second electrode formed on the first electrode 2: a second electrode, and an oxide layer 气 "vaporized layer 4" disposed between the first electrode and the second electrode 2'3. The current-driven variable resistance characteristic is a columnar grain structure in a direction substantially perpendicular to the plane of the plane. The columnar crystal grains of the pure chemical layer 4 are juxtaposed to each other in the radial direction. The grain boundary of the adjacent columnar crystal grains serves as a moving path of ions in the oxide layer 4 when driven by current. Preferably, the first preferred embodiment of the present invention further comprises: - a silicon substrate 5, a titanium layer 6 formed on the financial substrate 5, and an oxygen (four) layer 7β interposed between the (four) and the (four) substrates 5 The first and second electrodes 2, 3 of the first preferred embodiment of the invention are made of a surface (Pt), Ti, Ag, a conductive oxide (such as 'Ru〇2, YBCO)' or a nitride (such as (four), blue). The first electrode 2 is formed between the oxide layer 4 and the seed layer 6. In the first preferred embodiment of the invention, the second electrode 3 is a circular electrode having a diameter of 220 μm made of pi. It is worthwhile to mention that 'the invention mainly uses the grain boundary between adjacent columnar grains as the path when the current drives the oxygen vacancy to form the conductive wire'. When the radial grain size of the columnar grain exceeds In an hour, it is less likely to form columnar grains; in contrast, the radial grain size of excessively large columnar grains, in the application of nano-scale miniaturized elements, the oxide layer 4 will not be able to obtain a sufficient amount of columnar The grain 'will not provide a conductive wire path from the flat grain boundary due to the tendency to be a single grain (single_n) structure. Therefore, preferably, the radial grain size of the columnar grains of the oxide layer 4 is between 5 nm and 1 ram. In the first preferred embodiment of the present invention, the pillars of the oxide layer 4 have a radial grain size of about 25 nm. The oxide layer 4 suitable for use in the present invention is made of a hexagonal crystal structure of an oxidized (additional) or oxidized bond (7) (HCP is a marginal filament compound; this oxide layer is preferably used in the present month) 4 is at room temperature and the working pressure of the city 3 W. 'After a radio frequency magnetic control 贱 plating system, the magnification of the 2n 〇 light material (not shown) is called the round output power of the 2n 〇putteHng (4) Further, when the thickness of the oxide layer 4 is insufficient, the element of the present invention as a whole will be short-circuited due to a leakage current problem; conversely, when the oxide layer 4 is excessively large, the overall element of the present invention The loss problem will be relatively increased due to the excessive write/erase voltage during operation. Therefore, preferably, the thickness of the oxide layer 4 is between 5 nm and 5 〇〇 nm. It is suitable for use as a bipolar resistive memory when the thickness of the oxide layer 4 is thin (for example, 100 nm or less); conversely, when the thickness of the oxide layer 4 is large (for example, When it is 1 〇〇 nm or more, it is suitable for use as a unipolar resistive memory. In the embodiment of the rut, the thickness of the oxide layer 4 is 1 〇〇 nm (that is, suitable for a unipolar resistive memory). Referring to FIG. 2, the scanning method of the first preferred embodiment of the present invention A scanning electron microscope (SEM) topographical cross-sectional view shows that the oxide layer (ie, Zn〇) 4 has a columnar grain structure. Referring to FIG. 3, the first preferred embodiment of the present invention The X-ray diffraction spectrogram (XRD) shows that the ZnO of the first preferred embodiment has (0〇2) [ie, the C-axis preferred orientation 10 201003899 (orientation)] In the hexagonal crystal phase structure, the growth direction of the columnar crystal grains is directed and grown along the C axis. Referring to Fig. 4, the X-ray photoelectron diagram of the Zn〇 of the first preferred embodiment of the present invention (X-ray photoelectr〇) n spectr〇gram, abbreviated as xps) shows that the binding energy of the Zn 2p"2 signal peak and the Zn 2 heart signal peak are located at 1〇45 3 and 1〇22 3 respectively, between The bond energy difference is about 23_0 eV, which is equivalent to the total oxidation state of zinc (ie, Zn2+). The Zn〇{ in the oxidation state of the first preferred embodiment of the present invention prevents the integral component of the first preferred embodiment from being electrically conductive due to part of the metallic zinc and causes the component to be unusable due to a short circuit. Referring to FIG. 5, the current versus voltage ον) graph of the first preferred embodiment of the present invention shows that the first preferred embodiment of the present invention is provided under the condition of limiting the current (the add-on eQmpHa is called % mA). For example, the opening of the electric dust and the corresponding opening electric field are only about 3 v and Q 3 Mv/em respectively; and the writing voltage (ie, write or set) and the erasing voltage (ie, (10) or (8) are respectively about 2 v. With two, at 1 v. Compared with the conventional pt/Ti〇&p;p" Referring to FIG. 6, the uniaxial W curve and the resistance pair reversal frequency graph of the first preferred embodiment of the present invention show that the write voltage and the erase voltage are respectively concentrated between i.25 v and 2.35 v. Between ~ 〇 75 v 'and convert electricity (four), at 2.0 V. It is shown that the first preferred embodiment of the present invention effectively provides a uniform hook path for oxygen vacancies during movement due to the columnar grain structure @ Zn0. Therefore, the operation (write/erase) voltage is stabilized. Furthermore, the overall component of the first preferred embodiment of the present invention consumes less power than the conversion voltage v) of the conventional Pt/TiC^/Pt structure proposed in the prior art of 2010038038. In addition, although the high resistance state (HRS) of the first preferred embodiment of the present invention exhibits a tendency to shake at the initial stage; however, the high resistance state after the fifth inversion is stable. Moreover, the first preferred embodiment has a ratio of the erased high resistance state (HRS) to the written low resistance state (LRS) of 3 to 4 orders of magnitude, and also shows excellent overall component identification. which performed. Referring again to Figure 1, a second preferred embodiment of the non-volatile resistive memory of the present invention is substantially identical to the first preferred embodiment. The difference is that the thickness of the oxide layer 4 is about 25 nm (i.e., suitable for bipolar resistive memory). Referring to FIG. 7, a cross-sectional view of a transmission electron microscope (TEM) of the second preferred embodiment of the present invention shows that the oxide layer of the second preferred embodiment of the present invention (ie, ZnO) 4 has a thickness of about 25 nm and has a columnar grain structure. Referring to FIG. 8, the biaxial pv curve and the voltage versus inversion number of the second preferred embodiment of the present invention show that the write voltage and the erase voltage are respectively concentrated between 0.6 V and 0.8 V. Between 0.4 V and -0.8 V, and the conversion voltage is less than 1.0 V. Furthermore, the overall component of the second preferred embodiment of the present invention consumes less power than the switching voltage (5 V) of the conventional Pt/Ti〇2/Pt structure proposed in the prior art. It is shown that this second preferred embodiment of the present invention effectively provides uniform routing of oxygen vacancies during movement due to the columnar grain structure of ZnO; therefore, the 'operation (write/erase) voltage is stable. In summary, the non-volatile resistive memory of the present invention not only consumes 12 201003899 low, but also has the characteristics of high operating voltage stability and excellent identification, and indeed achieves the object of the present invention. The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent change and modification of the patent application scope and the description of the invention are as follows. All remain within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a front elevational view showing a first preferred embodiment of the non-volatile resistive memory of the present invention; FIG. 2 is a SEM top view showing the first preferred embodiment of the present invention. Figure 3 is an XRD analysis data illustrating the crystal structure of an oxide layer (ZnO) of the first preferred embodiment of the present invention; and Figure 4 is an XPS energy spectrum illustrating the present invention. The oxidation state of ZnO of the first preferred embodiment; FIG. 5 is a -W graph illustrating the state of the turn-on voltage, the write voltage and the erase voltage of the first preferred embodiment of the present invention; FIG. 6 is -! The curve of the ν curve and the resistance versus the number of times of reversal, illustrating the operational stability and the identification of the first preferred embodiment of the present invention; FIG. 7 is a top view of the second preferred embodiment of the present invention. The cross-sectional surface topography; and FIG. 8 is a graph of the -W curve and the voltage versus inversion number, illustrating the operational stability and the identification of the second preferred embodiment of the present invention. 13 201003899 [Description of main component symbols] 2 ..... First electrode 3 ..........Second electrode 4 .......... Telluride layer 5 .......... 矽 substrate 6 .......... titanium layer 7 .......... yttrium oxide layer X......... . Direction 14