200950092 九、發明說明： 【發明所屬之技術領域】 ‘ 本發明涉及一種薄膜電晶體的製備方法，尤其涉及一 種基於奈米碳管的薄膜電晶體的製備方法。 【先前技術】 薄膜電晶體（Thin Film Transist()r，TFT )係現代微電 子技術中的-種關鍵性電子元件，目前已經被廣泛的應用 於平板顯示器等領域。薄膜電晶體主要包括閘極、絕緣層、 半導體層、源極和蹄。其中，源極和肺間隔設置並與 半導體層電連接’閘極通過絕緣層與半導體層及源極和沒 極間隔絕緣設置。所述半導體層位於所述源極和没極之間 的區域形成-通道區域。薄膜電晶體中的閘極、源極、没 極均由導電材料構成，該導電材料一般爲金屬或合金。當 於閘極上施加-電壓時’與閘極通過絕緣層間隔設置的; 導體層中的通道區域會積累載子，當載子積累到一定程 ❽與半導體層電連接的源極没極之間將導通，從而有電 流從源極流向沒極。於實際應用中’對薄膜電晶體的要求 2希望付到較大的開關電流比。影響上述開關電流比的因 素除薄膜電晶體的製備工藝外，薄膜電晶體半導體層 導體材料的載子移動率爲影響開關電流比的最重要:影響 因素之--200950092 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for preparing a thin film transistor, and more particularly to a method for preparing a thin film transistor based on a carbon nanotube. [Prior Art] Thin Film Transist (TFT, TFT) is a key electronic component in modern microelectronic technology and has been widely used in flat panel displays and the like. The thin film transistor mainly includes a gate, an insulating layer, a semiconductor layer, a source, and a hoof. Wherein, the source and the lung are spaced apart and electrically connected to the semiconductor layer. The gate is insulated from the semiconductor layer and the source and the gate by an insulating layer. The semiconductor layer is located in a region between the source and the gate to form a channel region. The gate, the source, and the gate of the thin film transistor are each composed of a conductive material, which is generally a metal or an alloy. When a voltage is applied to the gate, 'the gate is spaced apart by the insulating layer; the channel region in the conductor layer accumulates carriers, and when the carrier accumulates to a certain distance, the source electrode is electrically connected to the semiconductor layer. It will conduct, so that current flows from the source to the pole. In practical applications, the requirements for thin film transistors 2 are expected to pay a larger switching current ratio. Factors affecting the above-mentioned switching current ratio In addition to the preparation process of the thin film transistor, the carrier mobility of the thin film transistor layer conductor material is the most important factor affecting the switching current ratio: the influencing factor--
曰先前技術中，薄膜電晶體中形成半導體層的材料爲非 曰曰矽、多晶矽或有機半導體聚合物等（R E T Schmpp，B _wski，J. Κ· Rath，New challenges in thin fiim 200950092 transistor research, Journal 〇f Non-Crystalline Solids, 299-302, 1304.1310 (2002))。以非晶石夕作爲半導體層的非 晶石夕薄膜電晶體的製備技術較爲成熟，但於非晶梦薄膜電 晶體中’由於半導體層中通常含有大量的懸挂鍵，使得載 子的遷移率很低，從而導致薄膜電晶體的響應速度較慢。 以多晶石夕作爲半導體層的薄膜電晶體相對於以非晶石夕作爲 半導體層的薄膜電晶體，具有較高的載子移動率，故響應 ❹ 速度也較快。但多晶石夕薄膜電晶體低溫製備成本較高，方 法杈複雜，大面積製備困難，且多晶碎薄膜電晶體的關態 電μ較大。相較於上述傳統的無機薄膜電晶體，採用有機 半導體做半導體層的有機薄膜電晶體具有成本低、製備溫 度低的優點，且有機薄膜電晶體具有較高的柔物性。但由 於有機半導體聚合物於常溫下多爲跳躍式傳導，表現出較 =電阻率、較低的載子移動率，使得有機薄膜電 響應速度較慢。 ❿ 奈米碳管具有優異的力學及電學性能。並且，隨著太 米碳管螺旋方式的變化太丰溶 丁 俨性。本道心 現出金屬性或半導 、 導體性的奈米碳管具有較高的载子移動率（一妒 :達1000〜15〇〇cm2v-ls-1：)，係製備電晶體的理想材料。先 中已有報道採用半導體性奈米碳管形 作爲薄膜電晶體的半導和 ,.,^ ^ 靜居Μ “ 層述採用奈米碳管層作爲半 導：#膜電晶體的製備方法主要包括以下步驟：將太 米石反官粉末分散於有機溶叫中.通迠喰I 3 、不 卓β其命士 aw、另獨/合片1中，通過喷墨打印的方法將奈 ” L 4劑的混合液打印於絕緣基板上，待有機溶 7 200950092 ，劑揮發後，於絕緣基板的預定位置上形成一奈米 . 尤積及㈣金屬薄膜的方法於奈米碳管層上形成；極 ‘及沒極；於奈米碳管層上沈積一層氮化石夕形成-絕緣層. 及於絕緣層上沈積-金屬薄膜形成間極。然而，於方 法中，奈米碳管需要通過有機溶劑進行分散，奈米碳管易 圈聚，於半導體層中無法均勻分佈。且分散奈米 ^有^ 容劑易殘留於奈米碳管層中，影響薄膜電晶體的性 =。並且’於上述奈米碳管層中，奈米碳管隨機分 子於上述無序奈米碳管層中的傳導路徑較長，故上述 碳管層中奈米碳管的排列方式不能使奈求碳管的高^移 動率得到有效利用，進而不利於獲得具有較高載子移動率 的薄膜電晶體。另外，通過有機溶劑結合的奈来碳管層社 構鬆散，柔勒性差，不利於製備柔性的薄膜電晶體。… *有鑒於此，提供一種方法簡單、適於低成本大 的薄膜電晶體的製備方法實為必要。 Q 【發明内容】 一種薄膜電晶體的製備方法，包括以下步驟：提供一 奈米碳管陣列；採用一拉伸工具從奈米碳管陣列中拉取 ^至少-奈米碳管薄膜；鋪設上述至少—奈米碳管薄膜於 二絕緣基底表面’形成一奈米碳管層；間隔形成一源極及 一汲極，並使該源極及汲極與上述奈米碳管層電連接. 成-絕緣層於上述奈米碳管層表面；及形成一閉極於上^ 絕緣層表面，得到一薄膜電晶體。 一種薄膜電晶體的製備方法，包括以下步驟：提供一 8 200950092 . 奈米碳管陣列；採用一拉伸工具從奈米碳管陣列中拉取獲 得至少一奈米碳管薄膜；提供一絕緣基底；形成一閘極於 W 所述絕緣基底表面；形成一絕緣層覆蓋所述閘極；鋪設上 述至少一奈米碳管薄膜於絕緣層表面，形成一奈米碳管 層；及間隔形成一源極及一汲極，並使該源極及汲極與上 述奈米碳管層電連接。 一種薄膜電晶體的製備方法，包括以下步驟：提供一 ❹奈米碳管陣列；採用一拉伸工具從奈米碳管陣列中拉取獲 得至少一奈米碳管薄膜；鋪設上述至少一奈米碳管薄膜於 一絕緣基底表面，圖案化該奈米碳管薄膜，形成多個奈米 碳管層，間隔形成多個源極及多個汲極，並使上述每一奈 米碳官層均與一源極及一沒極電連接；於每一奈米碳管層 表面形成一絕緣層；及於每一絕緣層表面形成一閘極，得 到多個薄膜電晶體。 相較於先前技術’本技術方案實施例提供的薄膜電晶 ❹體及薄膜電晶體陣列的製備方法具有以下優點：其一，本 技術方案通過從奈米碳管陣列中直接拉取的方式獲得奈米 2管薄膜作爲半導體層’該奈米碳管薄膜中奈米碳管分佈 均句’且純度較高，避免了先前技術中形成的奈米碳管層 7奈米碳管易團聚，從而分佈不均，且奈米碳管層中易殘 邊2機溶劑的問題。其二，由於採用直接拉取的方式獲得 的不米奴官薄膜具有較大粘性，故，可以通過直接粘附的 方法將奈米碳管薄膜設置於所需位置，該方法簡單、成本 低且可以於較低溫度下進行，故，本技術方案提供的薄 9 200950092 ❹ !電1:製備方法具有成本低、環保及節能的優點。並 ’由U碳管薄膜可以直接_於任意材料的基底表 面’故，該基底的材料可以選擇不耐高溫的柔性 利於製備柔性的薄膜電晶體。其三，直接從奈米碳 中拉取的奈米碳管薄膜中，奈米碳管首尾相連並沿^一方 向排列，&’將該奈米碳管薄膜作爲半導體層時，可 過控制奈米碳f薄膜的設置方向進而㈣源極至汲極間太 =管的排列方向，從而使薄膜電晶體獲得較大的载子: 【實施方式】 以下將結合附圖詳細說明本技術方案實施例提供的薄 膜電晶體的製備方法。 請參閱圖1及圖2 ’本技術方案第一實施例提供一種 頂閘型薄膜電晶體10的製備方法，主要包括以下步驟： 步驟一：提供一奈米碳管陣列，優選地，該陣 ❹順排奈米碳管陣列。 赵 々本技術方案實施例提供的奈米碳管陣列爲單壁奈米碳 管陣列、雙壁奈米碳管或多壁奈米碳管陣列。本實施例中， 超順排奈米碳管陣列的製備方法採用化學氣相沈積法，其 具體步驟包括：（a)提供一平整基底，該基底可選用？型 或N型矽基底，或選用形成有氧化層的矽基底，本實施例 優選爲採用4英寸的矽基底；（b)於基底表面均勻形成一 催化劑層，該催化劑層材料可選用鐵（Fe)、鈷（c〇)、鎳 (Νι)或其任意組合的合金之一；（幻將上述形成有催化 200950092 . 劑層的基底於700〜900°C的空氣_退火約30分鐘〜90分 . 鐘；（d )將處理過的基底置於反應爐中，於保護氣體環境 . 下加熱到500〜74(TC ’然後通入碳源氣體反應約5〜3〇分 鐘’生長得到超順排奈米碳管陣列，其高度爲2〇〇〜4〇〇微 米。該超順排奈米碳管陣列爲多個彼此平行且垂直於基底 生長的奈米碳管形成的純奈米碳管陣列。通過上述控制生 長條件，該超順排奈米碳管陣列中基本不含有雜質，如無 定型碳或殘留的催化劑金屬顆粒等。該奈米碳管陣列中的 ❹奈米碳管彼此通過凡德瓦爾力緊密接觸形成陣列。該奈米 碳管陣列與上述基底面積基本相同。 本實施例中奴源氣可選用乙块、乙婦、甲烧等化學性 質較活潑的碳氫化合物，本實施例優選的碳源氣爲乙炔； 保護氣體爲氮氣或惰性氣體，本實施例優選的保護氣體爲 氬氣。 ’ ，可以理解，本實施例提供的奈米碳管陣列不限於上述 製備方法，也可爲石墨電極恒流電弧放電沈積法、雷射蒸 ❿發沈積法等。 步驟二：採用一拉伸工具從奈米碳管陣列中拉取獲得 至少-奈米碳管薄膜。其具體包括以下步驟：（&)從上述 不米石厌g陣列中選定一定寬度的多個奈米碳管片斷，本實 2 !!優f爲採用具有-定寬度的膠帶接觸奈米碳管陣列以 ^ 寬度的夕個奈米碳管片斷；（b)以一定速度沿基 本垂直於奈米碳管陣列生長方向拉伸該多個奈米碳管片 斷，以形成-連續的奈米碳管薄膜。 於上述拉伸過程中，該多個奈米碳管片段於拉力作用 11 200950092 •下沿拉伸方向逐漸脫離基底的同時，由於凡德瓦爾力作 •用，該選定的多個奈米碳管片斷分別與其它奈米碳管片斷 •首尾相連地連續地被拉出，從而形成一奈米碳管薄膜。該 奈米碳管薄臈包括多個首尾相連且定向排列的奈米碳管 束。該奈米碳管薄膜中奈米碳管的排列方向基本平行於奈 米碳管薄膜的拉伸方向。 ^請參閱圖3’該奈米碳管薄膜爲擇優取向排列的多個奈 米碳管束首尾相連形成的具有一定寬度的奈米碳管薄膜。 ❹該奈米碳管薄财奈米碳㈣㈣方向基本平行於奈米碳 管薄膜的拉伸方向。該直接拉伸獲得的擇優取向排列的奈 米碳管薄膜比無序的奈米碳管薄膜具有更好的均勻性，即 具均勻的厚度及具有均勻的半導體性能。並且，該奈 米碳管薄膜具有良好的柔勃性及透明度。同時該直接 獲得奈米碳f薄膜的方法簡單快速，適宜進行玉業化應用。 步驟三：鋪設上述至少一奈米碳管薄膜於一絕緣基底 110表面，形成一奈米碳管層14〇作爲薄膜電晶體的半 ❿導體層。其具體包括以下步驟：提供一、絕緣基底110 :將 上述奈米碳管薄膜鋪設於該絕緣基底no表面。 所述絕緣基底110的材料可選用大規模集成電路中 ,,的材料。所述絕緣基底110形狀不限，可爲方形 何形狀。所述絕緣基底110的大小尺寸不限，具體 β根據實際情况而定。所述絕緣基底110具有一平敕 面。具體地，所述絕緣基底110的材料可以爲硬性粗 如ρ型或Ν型矽、形成有氧化層的矽、透明石英拟 有氧化層的透明石英。另外，該絕緣基底11G的材 12 200950092 以係塑料或樹脂材料，如一 PET薄膜。 由於本實施例超順排奈米碳管陣列中的奈米碳管非常 純淨，且由於奈米碳管本身的比表面積非常大，故該奈米 碳管薄膜本身具有較强的m可直接將上述奈米碳 管薄膜粘附於絕緣基底丨丨0表面作爲半導體層。另外，可 以通過重複步驟二從奈米碳管陣列中拉取多個奈米碳管薄 膜，並將該多個奈米碳管薄膜重叠粘附於絕緣基底1忉表 面，形成一奈米碳管層14〇。該奈米碳管薄膜的重叠方向 不限，多個奈米碳管薄膜間通過凡德瓦爾力緊密結合。 ❹ ❹ 另外，可使用有機溶劑處理上述粘附於絕緣基底ιι〇 ^的奈米碳管| 14〇。具體地，可通過試管將有機溶劑滴 洛於奈米碳管層140表面浸潤整個奈米碳管層14〇。該 機溶劑爲揮發性有機溶劑，如乙醇、曱醇、丙酮、二氣乙 烧或氯仿，本實施例中採用乙醇。該奈米碳管層^經有 機溶劑浸潤處理後，於揮發性有機溶劑的表面張力的作用 下，該奈米碳管層140可牢固地貼附於絕緣基底u〇表面， 且表面體積比减小，粘性降低，具有良好的機械强度及韌 步驟四：間隔形成一源極151及一汲極152，並使該 極151及汲極152與上述奈米碳管層14〇電連接。 該源極151及汲極152的材料應具有較好的導電性。 具體地，該源極151及汲極152的材料可以爲金屬、合金°、 銦錫氧化物（ΙΤΟ )、銻錫氧化物（ΑΤ〇 )、導電銀膠、導- 聚合物及金屬性奈米碳管薄膜等導電材料。根據形 = 151及汲極152的材料種類的不同，可以摄二 刼用不同方法形 13 200950092 • 成該源極151及汲極152。具體地，當該源極151及汲極 • 152的材料爲金屬、合金、ITO或ΑΤΟ時，可以通過蒸鍍、 濺射、沈積、掩模及蝕刻等方法形成源極151及汲極丨52。 »· 當該源極151及汲極152的材料爲導電銀膠、導電聚合物 或奈米碳管薄膜時，可以通過印刷塗附或直接粘附的方 法’將該導電銀膠或奈米碳管薄臈塗附或粘附於絕緣基底 U0或奈米碳管層140表面，形成源極151及汲極152。一 般地’該源極151及汲極152的厚度爲〇·5奈米〜1〇〇微米， ❹源極151至汲極152之間的距離爲}〇〇微米。 虽奈米碳管層140中的奈米碳管薄膜沿基本相同的方 向重，!f，該源極151及汲極152應沿奈米碳管層140中 奈米妷官的排列方向間隔形成於奈米碳管層14〇上，從而 使奈米碳管層14Q中的奈求碳管的排列方向均沿源極151 至汲極152的方向排列。 本實施例中’該源極151及汲極152材料爲金屬。上 述步驟四具體可通過兩種方式進行。第一種方式且體包括 ::㈣：首先’於上述奈米碳管層H0表面均句塗覆一 ;成=j I，通過曝光及顯影等光刻方法於光刻膠上 區域露出該奈米碳管層二Γ亥源極151及沒極152 濺射或電子束、11過真空蒸鍍、磁控 丁不為發沈積等沈積方法 151及沒極152區域表 4九料、源極 錄金屬層；最後，===!層，優選爲把、鈦或 的金屬層，即得到开乂成於太4有機，谷劑去除光刻膠及其上 沒極m。第奈米碳管層140上的源極151及 第一種方式具體包括以下步驟：首先’於奈米 14 200950092 碳s層140表面沈積一金屬層；其次，於該金屬層表面塗 覆一層光刻膠；再次，通過曝光及顯影等光刻方法去除源 極151區域及及極152區域外的光刻膠；最後，通過電漿 飯刻等方法去除源極151區域及沒極152區域外的金屬 層，並以丙酮等有機溶劑去除源極151區域及汲極152區 域上的光刻膠，即得到形成於奈米碳管層14〇上的源極i5i 及沒極。本實施例中，該源極151及錄152的厚度 爲1微米，源極151至汲極152之間的距離爲5〇微米。In the prior art, a material for forming a semiconductor layer in a thin film transistor is a non-antimony, a polysilicon or an organic semiconductor polymer (RET Schmpp, B _wski, J. Κ Rath, New challenges in thin fiim 200950092 transistor research, Journal 〇f Non-Crystalline Solids, 299-302, 1304.1310 (2002)). The preparation technique of amorphous austenitic thin film transistor with amorphous austenite as a semiconductor layer is relatively mature, but in amorphous amorphous thin film transistor, 'the mobility of the carrier is caused by the fact that the semiconductor layer usually contains a large number of dangling bonds. Very low, resulting in a slower response of the thin film transistor. A thin film transistor having a polycrystalline as a semiconductor layer has a higher carrier mobility than a thin film transistor having a semiconductor layer as an amorphous layer, so that the response enthalpy is also faster. However, the preparation cost of the polycrystalline slab thin film transistor is high, the method is complicated, the large-area preparation is difficult, and the off-state electric μ of the polycrystalline thin film transistor is large. Compared with the above-mentioned conventional inorganic thin film transistor, the organic thin film transistor using an organic semiconductor as a semiconductor layer has the advantages of low cost and low preparation temperature, and the organic thin film transistor has high softness. However, since the organic semiconductor polymer is mostly skipped at normal temperature, it exhibits a lower resistivity and a lower carrier mobility, making the organic film have a slower electrical response speed. ❿ Nano carbon tubes have excellent mechanical and electrical properties. Moreover, as the spiral pattern of the carbon nanotubes changes too much, it is too soluble. The metal core or semi-conductive, conductive carbon nanotubes have a high carrier mobility (one 妒: 1000~15〇〇cm2v-ls-1:), which is an ideal material for preparing crystals. . It has been reported that the semiconductor nanocarbon tube shape is used as the semiconducting phase of the thin film transistor, and ^^ is still in the Μ" layer using the carbon nanotube layer as the semiconducting: #膜膜晶晶方法The method comprises the following steps: dispersing the terracotta anti-official powder in an organic solvent. The 迠喰I 3 , the ββ 其 士 士, the other 独/合片1, by inkjet printing method will be "N" The mixed solution of 4 doses is printed on the insulating substrate, and after the solvent is volatilized, a nanometer is formed on the predetermined position of the insulating substrate, and the method of forming the metal film is formed on the carbon nanotube layer; Pole 'and immersed; deposited a layer of nitride on the carbon nanotube layer to form an insulating layer. And deposited on the insulating layer - the metal film forms the interpole. However, in the method, the carbon nanotubes need to be dispersed by an organic solvent, and the carbon nanotubes are easily trapped and cannot be uniformly distributed in the semiconductor layer. And the dispersion of nanometers has a positive agent that remains in the carbon nanotube layer, affecting the properties of the thin film transistor. And in the above-mentioned carbon nanotube layer, the conduction path of the random carbon nanotubes in the disordered carbon nanotube layer is long, so the arrangement of the carbon nanotubes in the carbon nanotube layer cannot be made. The high mobility of the carbon tube is effectively utilized, which is disadvantageous for obtaining a thin film transistor having a high carrier mobility. In addition, the carbon nanotube layer structure bonded by the organic solvent is loose and has poor flexibility, which is disadvantageous for preparing a flexible thin film transistor. ... In view of the above, it is necessary to provide a method for preparing a thin film transistor which is simple in method and suitable for low cost. Q [Survey] A method for preparing a thin film transistor, comprising the steps of: providing a carbon nanotube array; using a stretching tool to pull a film of at least a carbon nanotube from the array of carbon nanotubes; laying the above At least a carbon nanotube film forms a carbon nanotube layer on the surface of the two insulating substrates; a source and a drain are formed at intervals, and the source and the drain are electrically connected to the carbon nanotube layer. - an insulating layer on the surface of the carbon nanotube layer; and a surface which is closed to the upper insulating layer to obtain a thin film transistor. A method for preparing a thin film transistor comprises the steps of: providing an 8 200950092 . carbon nanotube array; using a stretching tool to extract at least one carbon nanotube film from the carbon nanotube array; providing an insulating substrate Forming a gate on the surface of the insulating substrate; forming an insulating layer covering the gate; laying the at least one carbon nanotube film on the surface of the insulating layer to form a carbon nanotube layer; and forming a source by spacing a pole and a drain, and electrically connecting the source and the drain to the carbon nanotube layer. A method for preparing a thin film transistor, comprising the steps of: providing a tantalum carbon nanotube array; using a stretching tool to extract at least one carbon nanotube film from the carbon nanotube array; laying at least one nanometer The carbon tube film is patterned on the surface of an insulating substrate to pattern the carbon nanotube film to form a plurality of carbon nanotube layers, and a plurality of sources and a plurality of drain electrodes are formed at intervals, and each of the carbon nanolayers is formed An insulating layer is formed on a surface of each of the carbon nanotube layers; and a gate is formed on the surface of each of the insulating layers to obtain a plurality of thin film transistors. Compared with the prior art, the method for preparing a thin film transistor and a thin film transistor array provided by the embodiments of the present technical solution has the following advantages: First, the technical solution is obtained by directly pulling from a carbon nanotube array. The nano tube 2 film as a semiconductor layer 'the carbon nanotubes in the carbon nanotube film distribution is uniform' and the purity is high, avoiding the agglomeration of the carbon nanotube layer 7 carbon nanotubes formed in the prior art, thereby Uneven distribution, and the problem of solvent in the carbon nanotube layer. Secondly, since the non-nano film obtained by the direct pulling method has a large viscosity, the carbon nanotube film can be placed at a desired position by a direct adhesion method, which is simple and low in cost. It can be carried out at a lower temperature, so the thinning method provided by the technical solution is 200950092. The preparation method has the advantages of low cost, environmental protection and energy saving. And the U carbon tube film can be directly applied to the substrate surface of any material. Therefore, the material of the substrate can be selected to be flexible against high temperature, which is advantageous for preparing a flexible film transistor. Third, in the carbon nanotube film directly pulled from the nano carbon, the carbon nanotubes are connected end to end and arranged along the direction of the ^, and the carbon nanotube film can be controlled as a semiconductor layer. The arrangement direction of the nano-carbon f film is further (4) the source-to-drainage too = the arrangement direction of the tube, so that the thin film transistor obtains a large carrier: [Embodiment] Hereinafter, the implementation of the technical solution will be described in detail with reference to the accompanying drawings. The preparation method of the thin film transistor provided by the example. Please refer to FIG. 1 and FIG. 2 'The first embodiment of the present invention provides a method for preparing a top gate type thin film transistor 10, which mainly includes the following steps: Step 1: providing a carbon nanotube array, preferably, the array Align the array of carbon nanotubes. The carbon nanotube array provided by the embodiment of the present invention is a single-walled carbon nanotube array, a double-walled carbon nanotube or a multi-walled carbon nanotube array. In this embodiment, the method for preparing the super-sequential carbon nanotube array adopts a chemical vapor deposition method, and the specific steps include: (a) providing a flat substrate, the substrate being selectable? a type or N-type germanium substrate, or a germanium substrate formed with an oxide layer, preferably a 4-inch germanium substrate is used in the embodiment; (b) a catalyst layer is uniformly formed on the surface of the substrate, and the catalyst layer material may be iron (Fe) One of the alloys of cobalt (c), nickel (Νι) or any combination thereof; (the above-mentioned substrate formed with the catalyst 200950092. The layer of the agent layer is annealed at 700~900 ° C for about 30 minutes to 90 minutes) (d) The treated substrate is placed in a reaction furnace and heated to a temperature of 500 to 74 in a protective gas atmosphere (TC 'and then passed through a carbon source gas for about 5 to 3 minutes to grow to obtain a super-aligned line. The carbon nanotube array has a height of 2 〇〇 4 4 μm. The super-sequential carbon nanotube array is a pure carbon nanotube array formed by a plurality of carbon nanotubes which are parallel to each other and grow perpendicular to the substrate. Through the above controlled growth conditions, the super-sequential carbon nanotube array contains substantially no impurities, such as amorphous carbon or residual catalyst metal particles, etc. The carbon nanotubes in the carbon nanotube array pass each other. Devalli is in close contact with the array to form the carbon nanotube The column has substantially the same area as the above-mentioned substrate. In this embodiment, the slave source gas may be a chemically active hydrocarbon such as a block B, a b-wheat or a ketone, and the preferred carbon source gas in this embodiment is acetylene; the shielding gas is nitrogen. Or an inert gas, the preferred shielding gas in this embodiment is argon. ', it can be understood that the carbon nanotube array provided in this embodiment is not limited to the above preparation method, and may also be a graphite electrode constant current arc discharge deposition method, laser Steaming deposition method, etc. Step 2: Using a stretching tool to extract at least a carbon nanotube film from the carbon nanotube array, which specifically includes the following steps: (&) from the above-mentioned non-meter stone Selecting a plurality of carbon nanotube segments of a certain width in the array, the present is a good carbon nanotube segment with a width of tape contacting the carbon nanotube array with a width of width; (b) Extending the plurality of carbon nanotube segments in a direction substantially perpendicular to the growth direction of the carbon nanotube array at a certain speed to form a continuous carbon nanotube film. The plurality of carbon nanotubes during the stretching process Fragment in tension 11 200950092 • At the same time as the lower direction of the stretching direction is gradually separated from the substrate, the selected plurality of carbon nanotube segments are continuously pulled out from the other carbon nanotube segments, end to end, due to the use of the van der Waals force. Forming a carbon nanotube film. The carbon nanotube thin layer comprises a plurality of end-to-end aligned carbon nanotube bundles. The arrangement of the carbon nanotubes in the carbon nanotube film is substantially parallel to the carbon nanotubes. The stretching direction of the film. ^ Please refer to Figure 3'. The carbon nanotube film is a carbon nanotube film with a certain width formed by connecting a plurality of carbon nanotube bundles arranged in a preferred orientation. The direction of the carbon (4) (4) is substantially parallel to the stretching direction of the carbon nanotube film. The preferred orientation of the carbon nanotube film obtained by direct stretching has better uniformity than the disordered carbon nanotube film. It has a uniform thickness and uniform semiconductor properties. Moreover, the carbon nanotube film has good flexibility and transparency. At the same time, the method for directly obtaining the nano-carbon f film is simple and rapid, and is suitable for jade application. Step 3: laying the at least one carbon nanotube film on the surface of an insulating substrate 110 to form a carbon nanotube layer 14 as a semi-turned conductor layer of the thin film transistor. Specifically, the method includes the following steps: providing an insulating substrate 110: laying the carbon nanotube film on the surface of the insulating substrate no. The material of the insulating substrate 110 can be selected from a large-scale integrated circuit. The shape of the insulating substrate 110 is not limited and may be a square shape. The size of the insulating substrate 110 is not limited, and the specific β is determined according to actual conditions. The insulating substrate 110 has a flat surface. Specifically, the material of the insulating substrate 110 may be a hard rough such as a p-type or a bismuth-type germanium, a germanium formed with an oxide layer, and a transparent quartz pseudo-oxidized transparent quartz. Further, the material 12 200950092 of the insulating substrate 11G is made of a plastic or resin material such as a PET film. Since the carbon nanotube in the super-sequential carbon nanotube array of the embodiment is very pure, and since the specific surface area of the carbon nanotube itself is very large, the carbon nanotube film itself has a strong m and can directly The above carbon nanotube film is adhered to the surface of the insulating substrate 丨丨0 as a semiconductor layer. In addition, a plurality of carbon nanotube films can be pulled from the carbon nanotube array by repeating step two, and the plurality of carbon nanotube films are overlapped and adhered to the surface of the insulating substrate to form a carbon nanotube. Layer 14〇. The stacking direction of the carbon nanotube film is not limited, and the plurality of carbon nanotube films are closely combined by the van der Waals force. ❹ ❹ In addition, the above-mentioned carbon nanotubes adhered to the insulating substrate ιι〇^ can be treated with an organic solvent. Specifically, the organic solvent may be dropped on the surface of the carbon nanotube layer 140 by a test tube to infiltrate the entire carbon nanotube layer 14〇. The solvent of the machine is a volatile organic solvent such as ethanol, decyl alcohol, acetone, ethylene bromide or chloroform, and ethanol is used in this embodiment. After the carbon nanotube layer is treated by the organic solvent, the carbon nanotube layer 140 can be firmly attached to the surface of the insulating substrate under the action of the surface tension of the volatile organic solvent, and the surface volume ratio is reduced. Small, low viscosity, good mechanical strength and toughness. Step 4: A source 151 and a drain 152 are formed at intervals, and the pole 151 and the drain 152 are electrically connected to the carbon nanotube layer 14 上述. The material of the source 151 and the drain 152 should have good electrical conductivity. Specifically, the material of the source 151 and the drain 152 may be metal, alloy, indium tin oxide (ΙΤΟ), antimony tin oxide (ΑΤ〇), conductive silver paste, conductive polymer and metallic nano. Conductive material such as carbon tube film. According to the type of material of shape = 151 and drain 152, it can be formed by different methods. 13 200950092 • The source 151 and the drain 152 are formed. Specifically, when the material of the source electrode 151 and the drain electrode 152 is metal, alloy, ITO or germanium, the source electrode 151 and the drain electrode 52 may be formed by evaporation, sputtering, deposition, masking, etching, or the like. . »· When the material of the source 151 and the drain 152 is a conductive silver paste, a conductive polymer or a carbon nanotube film, the conductive silver paste or nano carbon can be printed or adhered directly. The thin tube is coated or adhered to the surface of the insulating substrate U0 or the carbon nanotube layer 140 to form a source 151 and a drain 152. Generally, the thickness of the source 151 and the drain 152 is 〇·5 nm to 1 μm, and the distance between the source 151 and the drain 152 is 〇〇μm. Although the carbon nanotube film in the carbon nanotube layer 140 is heavy in substantially the same direction, the source 151 and the drain 152 should be formed along the arrangement direction of the nanotubes in the carbon nanotube layer 140. The carbon nanotube layer 14 is disposed so that the arrangement direction of the carbon nanotubes in the carbon nanotube layer 14Q is aligned in the direction from the source 151 to the drain 152. In the present embodiment, the source 151 and the drain 152 are made of metal. The above step 4 can be specifically performed in two ways. The first method and the body include: (4): Firstly, the surface of the above-mentioned carbon nanotube layer H0 is uniformly coated with one; the film is =j I, and the surface is exposed on the photoresist by photolithography such as exposure and development. Carbon nanotube layer 2 Γ 源 source 151 and immersed 152 sputtering or electron beam, 11 vacuum evaporation, magnetic control ding is not for deposition and other deposition methods 151 and No. 152 area table 4 nine materials, source recorded The metal layer; finally, the layer of ===!, preferably a metal layer of titanium, or titanium, which is obtained by opening the organic material, removing the photoresist and the upper electrode m thereof. The source 151 on the first carbon nanotube layer 140 and the first manner specifically include the following steps: first, a metal layer is deposited on the surface of the carbon s layer 140 of the nanometer 14 200950092; secondly, a layer of light is coated on the surface of the metal layer. The photoresist is removed; again, the photoresist in the region of the source 151 and the region outside the region 152 is removed by photolithography such as exposure and development; finally, the source 151 region and the region outside the gate 152 are removed by plasma or the like. The metal layer is removed with an organic solvent such as acetone to remove the photoresist on the source 151 region and the drain 152 region, thereby obtaining the source i5i and the electrodeless electrode formed on the carbon nanotube layer 14〇. In this embodiment, the source 151 and the recording 152 have a thickness of 1 μm, and the distance between the source 151 and the drain 152 is 5 μm.
❹ 可以理解，爲得到具有更好的半導體性的奈米碳管層 140,於形成源極151及汲極152之後，可以進一步包括一 去除奈米碳管層14〇中的金屬性奈米碳管的步驟。具體包 括以下步驟：首先’提供一外部電源，其次，將外部電源 的正負兩極連接至源極151及汲極152 ;最後，通過外部 電源於源極151及汲極152兩端施加一電壓，使金屬性^ 奈米碳管發熱並燒蝕，獲得一半導體性的奈米碳管層 140。該電壓於1〜l〇〇Q伏範圍内。 曰 另外，上述去除奈米碳管層140中金屬性奈米碳管的 方法也可以使用氫電漿、微波、太赫兹（THZ)、紅 (IR)、紫外線（UV)或可見光（Vis)照射該奈米碳管層 140’使金屬性的奈米碳管發熱並燒蝕，獲得— 奈米碳管層140。 守體性的 步驟五：於上述奈米碳管層140上形成一絕緣層13〇。 該絕緣層130的材料可以爲氣化石夕、氧化石夕 料或本並環丁烯（BCB)、聚酯或丙烯酸樹脂等柔性材才、 根據絕緣層13 0的材料種類的不同，可以採用不门^ 方 /^" 15 200950092 成該絕緣層130。具體地，當該絕緣層13〇 .石夕或氧切時，可以通過沈積的方法形成絕緣層13〇 = ST:的材料爲苯並環丁烯(⑽)、聚酿或两稀: ί月曰時，可以通過印刷塗附的方法形成絕緣層13〇。— 地，該絕緣層130的厚度爲〇.5奈米〜1〇〇微米。 又 本實施方式中採用電漿化學氣相沈積等沈積方 一氮化石夕絕緣層130覆蓋於奈米碳管層140及形成於太平 =管層140上的源極151及汲極152表面。絕緣層二 ❹厚度約爲1微米。 可以理解，根據薄膜電晶體1〇的不同應用，可以採 與形成源極⑸錢極152相㈣光刻絲刻的方法將所 述源極151及汲極152的一部分暴露於絕緣層13〇外。 步驟六：形成一閘極12〇於所述絕緣層13〇表面， 到一薄膜電晶體10。 e亥閘極120的材料應具有車交好的導電性。具體地，該 開極m的材料可以爲金屬、合金、IT〇、AT〇、導電銀膠: ❹導電聚合物及奈米碳管薄膜等導電材料。該金屬或合金材 料可以爲鋁、銅、鎢、鉬、金或它們的合金。具體地，當 該閘極120的材料爲金屬、合金、IT〇或AT〇時，可以二 過蒸鑛、減射、沈積、掩模及姓刻等方法形成閉極120。 當該閘極120的材料爲導電銀膠、導電聚合物或奈米碳管 薄膜時’可以通過直接枯附或印刷塗附的方法形成間極 120。一般地，該閘極12〇的厚度爲〇 5奈米〜1〇〇微米。 本技術方案實施例中通過與形成源極丨5丨及汲極152 相似的方法於絕緣層130表面且與半導體層相對的位置形 200950092 成一導電溥獏作爲閘極12〇。該閘極120通過絕緣層130 /、半導體層電絕緣。本技術方案實施例中，所述閘極1 的材::爲鋁’閘極120的厚度約爲！微米。 «月參閱圖4及圖5,本技術方案第二實施例提供一種 底，型薄膜電晶體2Q的製備方法，其與第—實施例中薄膜 :體0㈤製備方法基本相同。主要區別在於，本實施例 t成的薄膜電晶體2G爲—底閘型結構。本技術方案第二 實施例薄臈電晶體20的製備方法包括以下步驟： 〇 纟冑·提供一奈米碳管陣列’優選地，該陣列爲超 順排奈米碳管陣列。 步驟 採用一拉伸工具從奈米碳管陣列中拉取獲得 至少一奈米碳管薄膜。 步驟三：提供一絕緣基底210。 步驟四：形成一閘極22〇於所述絕緣基底21〇表面。 步驟五：形成—絕緣層23()覆蓋所述閘極，。 步驟八舖°又上述至少一奈米碳管薄臈於絕緣層23〇 鬌表面，形成一奈米碳管層24〇。 〆驛七.間隔形成-源極252及—汲極Μ，並使該 源極251及汲極252與上述奈米碳管層24〇電連接。 上述至少一奈米碳管薄膜枯附於絕緣層23〇表面，從 =與閘極22G電絕緣，並與閘極220相對。上述源極251 及及極252直接形成於上述奈米碳管層24〇表面。可以理 解’上述步驟七可以先於步驟推 “ 進订，即上述源極251及 ，極252形成於絕緣層230表面後，舖設上述奈米碳管薄 臈於絕緣層230表面並覆蓋源極251及汲極。 200950092 請參閱圖6,本技術方案第三實施例提供-種薄膜電 .晶體的製備方法，其與第一實施例薄膜電晶體10的製備方 .法基本相同。主要區別在於，本實施例於同一絕緣基底上 形成多個薄膜電晶體’從而形成一薄膜電晶體陣列。本 施例薄膜電晶體的製備方法具體包括以下步驟·· 步驟一：提供一奈米碳管陣列，優選地，該陣列爲趙 順排奈米碳管陣列。 超 步驟二：㈣一拉伸工具從奈米碳管陣射拉取 ❹至少一奈米碳管薄膜。 步驟三··鋪設上述至少一奈米碳管薄膜於一絕緣基底 表面，圖案化該奈米碳管薄膜，形成多個奈米碳管層。_ 上述多個奈米碳管層可以根據需要形成於絕緣基底表 面的特疋位置。當應用於液晶顯示器中時， 太 層可以按行及㈣方式形成於上述絕緣基底表^具炭: ，，該步驟三進一步包括以下步驟K a)將至少一奈米碳 &溥膜粘附於上述絕緣基底表面。該多個奈米碳管薄膜相 互重叠粘附於絕緣基底表面。（b)採用雷射 刻等方法對該至少一奈米剩膜進行切割 案化’於絕緣基底的表面形成多個奈米碳管層。 步驟四：間隔形成多個源極及多個汲極，並使上述每 奈米碳管層均與一源極及一汲極電連接。 與第一實施例薄膜電晶體10中源極151及汲極152 的形成方法相似，本實施例可以先於形成有多個奈米碳管 層的整個絕緣基底表面沈積一金屬薄膜，再通過蝕刻等方 去圖案化該金屬薄膜，從而於預定位置上一次形成多個源 200950092 極及多㈣極。上述源極及沒極的材料也可爲ιτ〇薄膜 • ΑΤΟ薄膜、導電聚合物薄膜、導電銀膠或奈米碳管薄膜。 步驟五：於每—奈来碳管層上形成-絕緣層。與第一 實施例薄膜電晶體10中絕緣層的製備方法相似地的，可以 先於整個絕緣基底的表面沈積一氮化石夕薄膜，再通過敍刻 等方法圖案化該氮化石夕薄膜，從而於預定位置上一次 多個絕緣層。上述絕緣層的材料也可爲氧化石夕等硬性材料 或苯並環丁稀（BCB)、聚醋或丙烯酸樹脂等柔性材料。 ❹ ㈣六：於每—絕緣層表㈣成-祕，得到一薄膜 電晶體陣列，該薄膜電晶體陣列包括多個薄膜電晶體。本 技術領域的技術人員應該明白，上述步驟三中採用雷射姓 刻或電聚餘刻等方法切割上述奈米碳管薄膜的步驟也可以 於步驟四至步驟六中的任意步驟中進行。 、可以理解，通過與第二實施例相似的方法，也可以形 成一薄膜電晶體陣列，其具體包括以下步驟： 步驟.提供一奈米碳管陣列，優選地，該陣列爲超 ❿順排奈米碳管陣列。 … 步驟二：採用一拉伸工具從奈米碳管陣列中拉取獲得 至少一奈米碳管薄膜。 步驟三：提供一絕緣基底。 步驟四：形成一多個閘極於所述絕緣基底表面。 步驟五：形成至少一絕緣層覆蓋所述多個閘極。 步驟六·鋪設上述至少一奈米碳管薄膜於絕緣層表 面，圖t Ί该奈米碳管薄膜，形成多個奈米碳管層，該多 個不米奴g層與上述多個閘極通過絕緣層相對並絕緣設 200950092 . 步驟七：間隔形成多個源極及多個沒極，並使上述每 . 不米碳管層均與一源極及一汲極電連接。 本技術方案實施例提供的薄膜電晶體及薄膜電晶體 列的製備方法具有以下優點：其一，本技術方案通過從夺 米碳管陣列中直接拉取的方式獲得奈米碳管薄膜作爲半導 體層，、這種半導體層的形成方法比先前技術中的嘴墨打印 2形成薄膜電晶體半導體層的方法簡單，無需經過於有機 ❹溶劑中分散奈米碳管的步驟。得到的奈米碳管薄膜中太米 m::，且純度較高，避免了先前技術中形成二 未碳官層中奈米碳管易團聚，從而分佈不均，且 層中易殘留有機溶劑的問題。其二，由於採用直接拉取二 方式獲得的奈米碳管薄膜具有較大枯性，故，可以通過直 ，枯附的方法將奈米碳管薄膜設置於所需位置，該方法簡 早、成本低，且可以於較低溫度下進行，故，本技術方案 提供的薄臈電晶體的製備方法具有成本低、環保及節能的 ❹優點。並且，由於奈米碳管薄膜可以直接枯附於任意材料 的基底表面，故，該基底的材料可以選擇不耐高溫的柔性 材料，有利於製備柔性的薄膜電晶體。其三，直接從夺米 碳管陣列中拉取的奈米碳管薄膜中，奈米碳管首尾相連並 沿同一方向排列，故，將該奈米碳管薄膜作爲半導體層時， 可以通過控制奈米碳管薄膜的設置方向進而控制源極至汲 極間奈米石反官的排列方向，從而使薄膜電晶體獲得較 載子移動率。 综上所述，本發明確已符合發明專利之要件，遂依法 20 200950092 提出專利申請。惟，以上所述者僅為本 自不能以此限制本案之申請專利範園 ？佳實施例’ ，人士援依本發明之精神所作之等效修；：本：：二 盍於以下申請專利範圍内。 飞受化，ό應涵 【圖式簡單說明】 的流程圖 圖1係本技術方案第一實施例薄 i游圖。 力κ關㈣電晶體的製備方法 ❹ 流程圖 圖/係本技術方案第—實施例薄膜電晶體的製備工藝 係本技術方案第—實施例薄膜電日體中太半磁芦 溥臈的掃描電鏡照片。 眠€曰曰體中奈未石厌管 的流程圖系本技術方案第二實施例薄骐電晶體的製備方法 圖5係本技術方案 流程圖。 ^ 圖6係本技術方案 的流程圖。 〃 【主要元件符號說明】 薄獏電晶體 絕緣基底 閘極 絕緣層 奈米碳管層 源極❹ It can be understood that, in order to obtain the carbon nanotube layer 140 having better semiconductivity, after forming the source electrode 151 and the drain electrode 152, the metal carbon nanotube in the carbon nanotube layer 14 can be further removed. The steps of the tube. Specifically, the method includes the following steps: firstly, 'providing an external power supply, and secondly, connecting the positive and negative poles of the external power supply to the source 151 and the drain 152; finally, applying a voltage across the source 151 and the drain 152 through the external power source, so that The metallic carbon nanotubes are heated and ablated to obtain a semiconducting carbon nanotube layer 140. The voltage is in the range of 1 to 1 〇〇 Q volts. Further, the above method of removing the metallic carbon nanotubes in the carbon nanotube layer 140 may also be performed using hydrogen plasma, microwave, terahertz (THZ), red (IR), ultraviolet (UV) or visible (Vis) irradiation. The carbon nanotube layer 140' heats and ablates the metallic carbon nanotube to obtain a carbon nanotube layer 140. Step 5: An insulating layer 13 is formed on the carbon nanotube layer 140. The material of the insulating layer 130 may be a gasification stone, an oxidized stone or a flexible material such as a naphthacene (BCB), a polyester or an acrylic resin, and may be used depending on the material type of the insulating layer 130. The door ^ square / ^ " 15 200950092 into the insulating layer 130. Specifically, when the insulating layer 13 is argon or oxygen cut, the insulating layer 13 can be formed by deposition. The material of the 〇=ST: is benzocyclobutene ((10)), poly or two: ί月In the case of ruthenium, the insulating layer 13A can be formed by a printing and coating method. The ground layer has a thickness of 〇5 nm to 1 〇〇 micrometer. Further, in the present embodiment, a deposition of a nitride-on-silicon oxide layer 130 such as plasma chemical vapor deposition is applied to the surface of the carbon nanotube layer 140 and the source electrode 151 and the drain electrode 152 formed on the Taiping = tube layer 140. The insulating layer has a thickness of about 1 micron. It can be understood that, depending on the different applications of the thin film transistor, a part of the source 151 and the drain 152 may be exposed to the insulating layer 13 by a method of forming a source (5) and a lithography. . Step 6: Form a gate 12 on the surface of the insulating layer 13 to a thin film transistor 10. The material of the e-thropole 120 should have good electrical conductivity. Specifically, the material of the open electrode m may be a conductive material such as a metal, an alloy, an IT crucible, an AT crucible, or a conductive silver paste: a conductive polymer and a carbon nanotube film. The metal or alloy material may be aluminum, copper, tungsten, molybdenum, gold or alloys thereof. Specifically, when the material of the gate 120 is metal, alloy, IT〇 or AT〇, the closed pole 120 can be formed by steaming, subtraction, deposition, masking, and surname. When the material of the gate 120 is a conductive silver paste, a conductive polymer or a carbon nanotube film, the interpole 120 can be formed by direct drying or printing. Generally, the thickness of the gate 12 is 〇 5 nm to 1 μm. In the embodiment of the present technical solution, a conductive 溥貘 is formed as a gate 12 于 on the surface of the insulating layer 130 and opposite to the semiconductor layer by a method similar to the formation of the source 丨5 丨 and the drain 152. The gate 120 is electrically insulated by the insulating layer 130 / and the semiconductor layer. In the embodiment of the technical solution, the material of the gate 1 is: the thickness of the aluminum 'gate 120 is about! Micron. Referring to FIG. 4 and FIG. 5, the second embodiment of the present invention provides a method for preparing a bottom-type thin film transistor 2Q, which is basically the same as the method for preparing a film: body 0 (5) in the first embodiment. The main difference is that the thin film transistor 2G of this embodiment is a bottom gate type structure. The second embodiment of the present invention provides a method for preparing a thin germanium transistor 20 comprising the steps of: 〇 providing a carbon nanotube array. Preferably, the array is a super-sequential carbon nanotube array. Steps A tensile tool is used to extract at least one carbon nanotube film from the array of carbon nanotubes. Step 3: Provide an insulating substrate 210. Step 4: Form a gate 22 on the surface of the insulating substrate 21. Step 5: Forming - the insulating layer 23 () covers the gate. Step 8 and then at least one of the carbon nanotubes is thinned on the surface of the insulating layer 23 to form a carbon nanotube layer 24〇. 7. The spacers are formed - source 252 and - drain Μ, and the source 251 and the drain 252 are electrically connected to the carbon nanotube layer 24 上述. The at least one carbon nanotube film is adhered to the surface of the insulating layer 23, electrically insulated from the gate 22G and opposed to the gate 220. The source electrode 251 and the electrode 252 are formed directly on the surface of the carbon nanotube layer 24 . It can be understood that the above step 7 can be pushed in advance, that is, after the source 251 and the pole 252 are formed on the surface of the insulating layer 230, the carbon nanotube is laid on the surface of the insulating layer 230 and covers the source 251. Referring to FIG. 6 , a third embodiment of the present technical solution provides a method for preparing a thin film transistor, which is basically the same as the method for preparing the thin film transistor 10 of the first embodiment. The main difference is that In this embodiment, a plurality of thin film transistors are formed on the same insulating substrate to form a thin film transistor array. The method for preparing the thin film transistor specifically includes the following steps: Step 1: providing a carbon nanotube array, preferably Ground, the array is a Zhaoshun row of carbon nanotube arrays. Ultra-step 2: (4) A stretching tool pulls at least one carbon nanotube film from the carbon nanotube array. Step 3 · Laying at least one of the above The carbon nanotube film is patterned on the surface of an insulating substrate to pattern the carbon nanotube film to form a plurality of carbon nanotube layers. _ The plurality of carbon nanotube layers can be formed on the surface of the insulating substrate as needed. When applied to a liquid crystal display, the eutectic layer may be formed on the insulating substrate according to the row and (4) manner, and the step 3 further includes the following steps: k a) at least one nanocarbon & Adhering to the surface of the insulating substrate, the plurality of carbon nanotube films are adhered to each other on the surface of the insulating substrate. (b) cutting the at least one nanometer remaining film by laser engraving or the like on the insulating substrate Forming a plurality of carbon nanotube layers on the surface. Step 4: forming a plurality of sources and a plurality of drains at intervals, and electrically connecting each of the carbon nanotube layers to a source and a drain. The method for forming the source electrode 151 and the drain electrode 152 in the thin film transistor 10 is similar. In this embodiment, a metal film may be deposited on the surface of the entire insulating substrate on which a plurality of carbon nanotube layers are formed, and then etched or the like. The metal film is patterned to form a plurality of sources 200950092 poles and multiple (four) poles at a predetermined position. The source and the electrodeless material may also be an ITO film, a conductive polymer film, a conductive silver paste or Nano carbon Step 5. Forming an insulating layer on each of the carbon nanotube layers. Similar to the method of preparing the insulating layer in the thin film transistor 10 of the first embodiment, a nitride may be deposited on the surface of the entire insulating substrate. The thin film is patterned by lithography or the like to pattern the plurality of insulating layers at a predetermined position. The material of the insulating layer may also be a hard material such as oxidized stone or benzocyclobutene (BCB). ), a flexible material such as polyester or acrylic resin. 四 (4) 6: In each of the insulating layer table (4), a thin film transistor array is obtained, the thin film transistor array comprising a plurality of thin film transistors. It should be understood that the step of cutting the carbon nanotube film by laser or the like in the above step 3 may also be performed in any of steps 4 to 6. It can be understood that a thin film transistor array can also be formed by a method similar to that of the second embodiment, which specifically includes the following steps: Step. Providing an array of carbon nanotubes, preferably, the array is super-shun Carbon tube array. Step 2: At least one carbon nanotube film is obtained by pulling from the carbon nanotube array using a stretching tool. Step 3: Provide an insulating substrate. Step 4: forming a plurality of gates on the surface of the insulating substrate. Step 5: forming at least one insulating layer to cover the plurality of gates. Step 6: laying the at least one carbon nanotube film on the surface of the insulating layer, and forming the plurality of carbon nanotube layers, the plurality of non-Mino layers and the plurality of gates The insulating layer is opposite and insulated by 200950092. Step 7: forming a plurality of sources and a plurality of poles at intervals, and electrically connecting each of the carbon nanotube layers to a source and a drain. The method for preparing a thin film transistor and a thin film transistor array provided by the embodiments of the present technical solution has the following advantages: First, the technical solution obtains a carbon nanotube film as a semiconductor layer by directly pulling from a carbon nanotube array. The method of forming such a semiconductor layer is simpler than the method of forming the thin film transistor semiconductor layer in the ink jet printing 2 of the prior art, and does not require the step of dispersing the carbon nanotube in the organic hydrazine solvent. The obtained carbon nanotube film has too m::, and the purity is high, which avoids the easy agglomeration of the carbon nanotubes in the formation of the second uncarbonized layer in the prior art, and thus the distribution is uneven, and the organic solvent is easily left in the layer. The problem. Secondly, since the carbon nanotube film obtained by the direct drawing method has a large dryness, the carbon nanotube film can be placed at a desired position by a straight and dry method. The method is low in cost and can be performed at a relatively low temperature. Therefore, the preparation method of the thin tantalum transistor provided by the technical solution has the advantages of low cost, environmental protection and energy saving. Moreover, since the carbon nanotube film can be directly adhered to the surface of the substrate of any material, the material of the substrate can be selected from a flexible material which is not resistant to high temperatures, and is advantageous for preparing a flexible thin film transistor. Third, in the carbon nanotube film pulled directly from the carbon nanotube array, the carbon nanotubes are connected end to end and arranged in the same direction, so when the carbon nanotube film is used as the semiconductor layer, it can be controlled. The arrangement direction of the carbon nanotube film further controls the alignment direction of the source-to-dip nanocrystal reversal, so that the thin film transistor obtains a relatively low carrier mobility. In summary, the present invention has indeed met the requirements of the invention patent, and filed a patent application according to law 20 200950092. However, the above mentioned is only a patent application park that cannot limit this case. The preferred embodiment ', the person assisted in the spirit of the present invention, equivalent modification;: this:: 2 is within the scope of the following patent application. Fig. 1 is a thin diagram of the first embodiment of the present technical solution. κ 关 ( 四 四 四 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图 流程图photo. The flow chart of the nano-electrode tube in the sleepy body is the flow chart of the second embodiment of the present invention. FIG. 5 is a flow chart of the technical solution. ^ Figure 6 is a flow chart of the technical solution. 〃 [Main component symbol description] Thin germanium transistor Insulation base Gate Insulation Nanocarbon layer Source
第二實施例薄媒電晶體的製備工藝 第三實施例薄骐電晶體的製備方法 10, 20 110, 210 120, 220 130, 230 140, 240 151, 251 21 200950092 152,252 汲極Second Embodiment Preparation Process of Thin Transistor Crystal Third Embodiment Method for Preparing Thin Tantalum Electrode 10, 20 110, 210 120, 220 130, 230 140, 240 151, 251 21 200950092 152,252 Bungee
22twenty two