200923671 a/UOid.lW 2^851twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種多處理器系統的開機異常解決 技術’且制是有關於-種切換CPU以管理義異常問題 的技術。 【先前技術】 /兩個或多個微處理H—起工作來完成某個任務的系 ，稱為“多處理器系統（Multiprocessorsystem)，，，它是為 高端工作站或·Μ設計的L里器祕具有至少兩 個中央處理單元(CPU)，藉由多個CPU聯合作#以提高系 統整體處理效能。 一般而吕，多處理器系統開機時，首先由指定單一的 開機 CPU (稱為 CPU0)作為 Boot Strap Processor (BSP， 啟動捆綁處理器），其通過北橋耦接至南橋；接著，cpu〇 提供啟動資訊，如：初始化中斷控制器、記憶體控制器、 pci控制器與串口，負責處理開機時基本輸入輸出系統 (BIOS)的指令，以進行系統初始化作業並載入作業系統 (〇S)。而開機時被定義為應用 CPU(application pr〇cessors) 的其他cpu，被設定處於等待狀態(wait state)。而藉由通 用輸入輸出埠（GPIO)耦接至多處理器系統的基板管理控 制器（baseboard management controller，BMC)主要用於檢 測多處理器系統是否啟動，其檢測過程為：首先系統上電， BMC開始計時，同時，讀取電平的變化情況，該電平變化 由夕處理器糸統中的BIOS ( Basic Input/Output System，基 200923671 υ/υο10.1νν zj>851twf.doc/p 本輪入輸出系統）進行改變，當系統無法正常啟動時，該 ，平不會發生變化’當ΒΜ。計時到一個預訂的值時，‘ 平仍然不發生變化’則可以觸系統沒有啟動。 -般情況下，當多處理器系統用久或操作不當時， CPU0可I會損壞或線路部分出現，而 換多處理器系統令的CPU。 而要切 專利號為TW00439025的臺灣專利，提出—種具有多 f) 數的CPU之夕處理㈣電腦’特別關於根據電腦的驅動電 源而能夠動態地控制驅動之cpu的數量之電腦，以實現對 而要電，動作之手提電腦最適合的多處理器構成。咖(〇#) 〜CPU(3 )之4個CPU ’將分別根據並聯度切換部控制轉 作，停止動作，根據電源供給源的種類、發熱量、動作中 =CPU的貞荷’或者依照❹者之系統軟體之動作環境設 定’而設定同時動作W CPU之數，亦即CPU並聯度。 土述方法通過改變CPU的驅動電源，使之並聯來動 ⑮控制驅狀CPU的數量，而不能解決t CPUG不能正常 G 工作採賴取另-顆CPU的技術問題。在cpu内集成有 北橋功此的夕處理為系統中認定只要通過超傳送標準匯流 排（HT匯流排）與南橋相連的就是CPU0,如果CPU0的 插座（SOCKET)或線路部分壞了，那麼整個多處理器系 „法正常工作了，需要將整個主板進行報廢。以麟 夕^為為例，來說明在cpu内集成北橋功能的多處理系 統存在的技術缺陷。AMD處理器與Intel處理器搭建的多 處理器系統的-個报大不同：刪處理器是通過前段匯流 200923671 O/UOib.l W z^851twf.doc/p 排共用一個北橋控制器，任意—顆CPU都能作為CPUO工 作；AMD處理器内建了北橋控制器，所以在多處理器系 統中各個cpu都有獨立的北橋。參照圖〗，其為習知αμ〇 多處理器系統的結構示意圖。；DRAM (動態隨機存取記憶 體）Π1 分別耦接至 CPU101、CPU103、CPU1〇5 以 ^ CPU107 ’各CPU相互連接，由於硬體線路的限制，如圖， 只有一顆CPU即CPU101能夠作為CPU〇通過HT Bus (Hyper Transport BUS，超傳送標準匯流排）直接跟南橋 (SB) 109連接。因此上述方法並不能達到切換多處理器 系統中的CPU的目的，當作為啟動多處理器系統的cpU〇 或者線路部分發生故障時’整個系統就無法工作，系統就 報廢了，增加了整個系統的成本。 【發明内容】 本發明的目的之一在提供一種多處理器系統，以解決 現有技術只有一顆CPU能啟動系統，當這顆CPU或者線 路部分發生故障時’整個系統就無法工作而導致系統報廢 而增加了整個系統的成本的問題。 本發明的另一目的在提供一種切換CPU方法，以解 決現有技術只有一顆CPU能啟動系統，當這顆CPU或者 線路部分發生故障時，整個系統就無法工作而導致系統報 廢而增加了整個系統的成本的問題。 本發明提出一種多處理器系統，包括：第一 CPU、第 二CPU、南橋以及超傳送標準匯流排中心。第一 CPU包 括北橋以及至少一超傳送標準匯流排。第二CPU包括北橋 200923671 u/ι/υιυ.χ w ltwf.doc/p 以及至少一超傳送標準匯流排。 排。超傳送標準匯流排中心執接^匕括超傳送標準匯流 及南橋的超傳送標準匯流排，用以 —cpu 流排連接至第-CPU的超傳_ =的祕送標準匯 - CPU及其巾的db橋—起運作 雨橋/、第 的超傳送標準匯流排連接“橋的 CPU本另提出—種多處理器系統，其包括：多個 、南橋以及超舰鮮_射心 CPU包括北橋以及至少一超傳糸 '、充t的母 U士MA、、，、 义得迗铽準匯流排，而南橋也包 ：5紅二讀賴流排，#南橋的超傳補準匯流排連接 CPU的超傳送標準M流排時，南橋與被連接的 :ί 橋—起運作，來啟動多處理器系統。前述200923671 a/UOid.lW 2^851twf.doc/p IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a booting abnormality solving technique for a multiprocessor system, and the system is related to switching The CPU is a technique for managing abnormality problems. [Prior Art] / Two or more microprocessors that work to accomplish a certain task, called "Multiprocessorsystem", which is an L-processor designed for high-end workstations or The secret has at least two central processing units (CPUs), which cooperate with multiple CPUs to improve the overall processing performance of the system. Generally, when the multi-processor system is powered on, it first specifies a single boot CPU (called CPU0). As the Boot Strap Processor (BSP), it is coupled to the south bridge through the north bridge; then, the cpu provides boot information, such as: initialization interrupt controller, memory controller, pci controller and serial port, responsible for processing boot Basic input/output system (BIOS) instructions for system initialization and loading of the operating system (〇S). Other CPUs defined as application CPUs (application pr〇cessors) at boot time are set to wait ( Wait state). The baseboard management controller (BMC), which is coupled to the multiprocessor system by general purpose input/output port (GPIO), is mainly used for Check whether the multi-processor system is started. The detection process is as follows: First, the system is powered on, the BMC starts timing, and at the same time, the read level changes. The level change is caused by the BIOS in the processor (Basic Input/Output). System, base 200923671 υ/υο10.1νν zj> 851twf.doc/p This round-in output system) changes, when the system can not start normally, the flat will not change 'when ΒΜ. Time to a reserved value , 'Ping still does not change' can touch the system does not start. - Under normal circumstances, when the multi-processor system is used for a long time or improper operation, CPU0 can be damaged or the line part appears, and the multi-processor system is replaced. CPU. To cut the Taiwan patent with the patent number TW00439025, propose a CPU with multiple f) numbers (4) Computers, especially for computers that can dynamically control the number of CPUs driven according to the computer's driving power. It is the multi-processor that is suitable for the laptop, which is the most suitable for the mobile computer. The four CPUs of the CPU (3) and the CPU (3) will be switched according to the parallel degree switching unit and stopped. According to the type of power supply source, the amount of heat generated, the load of the CPU = the load of the CPU, or the setting of the operating environment of the system software of the latter, the number of simultaneous operation W CPUs, that is, the CPU parallelism is set. Change the drive power of the CPU, make it parallel to control the number of drive CPUs, and can not solve the technical problem that the CPUG can't work normally. In the cpu, the integration of the Northbridge function is considered as the CPU in the system. As long as the super-transfer standard bus (HT bus) is connected to the south bridge, it is CPU0. If the CPU0 socket (SOCKET) or the line part is broken, then the whole The processor system works normally, and the entire motherboard needs to be scrapped. Take Lin Xi ^ as an example to illustrate the technical defects in the multi-processing system that integrates the North Bridge function in the CPU. The AMD processor and the Intel processor are built. The multi-processor system has a big difference: the deleted processor is shared by a front-end sink 200923671 O/UOib.l W z^851twf.doc/p, and any CPU can work as a CPUO; AMD The processor has a built-in North Bridge controller, so each CPU has a separate North Bridge in the multiprocessor system. Referring to the figure, it is a schematic diagram of a conventional αμ〇 multiprocessor system. DRAM (Dynamic Random Access Memory) Π1 is respectively coupled to CPU101, CPU103, CPU1〇5 to ^CPU107' CPUs are connected to each other. Due to the limitation of hardware lines, as shown in the figure, only one CPU, CPU101, can pass as CPU. The HT Bus (Hyper Transport BUS) is directly connected to the South Bridge (SB) 109. Therefore, the above method does not achieve the purpose of switching the CPU in a multiprocessor system, when it is used as a cpU to start a multiprocessor system or When the line part fails, the whole system cannot work, and the system is scrapped, which increases the cost of the entire system. SUMMARY OF THE INVENTION One object of the present invention is to provide a multi-processor system to solve the prior art with only one CPU. The system can be started, and when the CPU or the line portion fails, the whole system cannot work and the system is scrapped, which increases the cost of the entire system. Another object of the present invention is to provide a method for switching CPUs to solve the existing problem. There is only one CPU that can start the system. When the CPU or line part fails, the whole system can't work and the system is scrapped, which increases the cost of the whole system. The present invention proposes a multi-processor system, including: First CPU, second CPU, south bridge, and super transfer standard bus center. First CPU Including the North Bridge and at least one super-transfer standard bus. The second CPU includes North Bridge 200923671 u/ι/υιυ.χ w ltwf.doc/p and at least one over-transfer standard bus. Row. Hyper-Transfer Standard Bus Center Center ^ Included in the super-transport standard convergence and the South Bridge's super-transport standard bus, used to connect the cpu bus to the super CPU of the CPU - _ = the secret standard sink - the CPU and its db bridge - to operate the rain bridge / The first super-transfer standard bus connection "the bridge CPU is proposed separately - a multi-processor system, including: multiple, south bridge and super-ship fresh _ shooting CPU including the North Bridge and at least one super-transmission 糸', charge t The mother U, MA,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The South Bridge and the connected: ί Bridge operate to start the multiprocessor system. The foregoing
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J °迟‘準匯流排中心耦接至每一 CPU的超傳送標準匯 流排以及南橋的超傳送標準匯流排，用以選擇任一個CPU 的超傳送標準賴排，使其連接至南橋的超傳送標準匯流 排、’、,t被選擇的cpu無法正常工作或線路部分損壞時，超 傳达標準匯流排中心選擇另一個CPU的超傳送標準匯流 排’使其連接至南橋的超傳送標準匯流排。 '依照本發明的實施例所述之多處理器系統，上述超傳 运標準匯流排中心為多路開關。 依照本發明的實施例所述之多處理器系統，其中的 CPU的數目共有四個，且多路開關為四路開關。 200923671 υ/υοι〇.ι w zj851tw£doc/p 依照本發明的實施例所述之多處理器系統，上述多處 理器系統更包括週邊電路，外設於多處理器系統的機箱面 板之上且耦接至超傳送標準匯流排中心，用以通過手動來 控制超傳送標準匯流排中心，切換選擇c p U之超傳送標準 匯流排與南橋之超傳送標準匯流排連接。 依照本發明的實施例所述之多處理器系統，上述多處 理器系統更包括基板管理控彻。基板管理控·通過通 用輪讀出埠（GPI0) _接至超傳送標準匯流排中心。此 基板管理控㈣包括：軟體自動控制單元以及檢測單元。 軟體自動控制單元用以自動控制超傳送標準匯流排中心， 切換選擇m；之超傳送標雜流排與南橋之 =理=元用以檢測多處理器系統是否啟動以 CPU本方法，其步驟之一為提供第- ΟThe J ° late 'quasi-bus center is coupled to the super-transport standard bus of each CPU and the super-transfer standard bus of the south bridge to select the super-transmission standard of any CPU to connect it to the super-transmission of the south bridge. When the standard bus, ',, t selected cpu is not working properly or the line is partially damaged, the super-conveying standard bus center selects another CPU's super-transfer standard bus' to connect it to the south bridge's super-transfer standard bus. . According to the multiprocessor system of the embodiment of the present invention, the super-transport standard bus center is a multiplexer. According to the multiprocessor system of the embodiment of the present invention, the number of CPUs is four, and the multiplexer is a four-way switch. According to the multiprocessor system of the embodiment of the invention, the multiprocessor system further includes a peripheral circuit, and the peripheral device is above the chassis panel of the multiprocessor system and It is coupled to the super-transfer standard bus center to manually control the super-transfer standard bus center, and switch to select the cp U ultra-transfer standard bus to connect with the south bridge super-transfer standard bus. In accordance with a multiprocessor system in accordance with an embodiment of the present invention, the multiprocessor system further includes substrate management control. Substrate management control • Read through the universal wheel (GPI0) _ to the super transfer standard bus center. The substrate management control (4) includes: a software automatic control unit and a detection unit. The software automatic control unit is used for automatically controlling the super-transfer standard bus center, and switching the selection m; the super-transmission standard chute and the south bridge are used to detect whether the multi-processor system is started by the CPU, and the steps thereof are One is to provide the first -
橋以及及第二哪皆包括北 準匯-排…流排’且南橋也包括超傳送標 至第二CPU⑽二、驟為使南橋的超傳送標準匯流排連接 及標準排’而使南橋與® — CPU 步驟：當第:理11线°其還包括 一 rpTT认 …、 吊工作或線路部分損壞時，倭篦 ί排。…送標準匯流排連接至南橋的超傳送標準匯 、甬、二明用多處理器系統及切換cpu方法，因此可 通過超傳4準匯流排中心自由選擇_哪來作為= 200923671 vy z,J851twf.doc/p 系統的CPU使用。或者如果作為啟動系統的CPU出現問 題’不用打開機箱就可以按照手冊切換另一顆CPU來啟動 系統繼續工作。啟動系統的CPU不能正常工作或者線路部 分壞了’整塊主板也不用報廢，可以切換另一顆CPU繼續 使用’減少了更換整塊主板的費用，降低了整個系統的成 本。 為讓本發明之上述和其他目的、特徵和優點能更明顯 r、 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 ‘ 1 明如下。 【實施方式】 本發明的特徵之一在於設置超傳送標準匯流排中 心，可以選擇任一顆CPU啟動，從而減少了更換整塊主板 的費用，降低了整個系統的成本。 參照圖2，其繪示為本發明實施例的一種多處理器系 統的結構示意圖。它包括：CPU101、CPU103、南橋109 以及超傳送標準匯流排中心20PCPU101包括北橋以及至 ϋ 少一超傳送標準匯流排。CPU103包括北橋以及至少一超 傳送標準匯流排。本實施例中，CPU101與CPU103其實 可以具有3個超傳送標準匯流排，但只使用到其中的2個。 南橋109也包括有超傳送標準匯流排。超傳送標準匯流排 中心201耗接至CPU101、CPU103及南橋1〇9的超傳送標 準匯流排，用以將南橋1〇9的超傳送標準匯流排連接至 CPU101的超傳送標準匿流排’而使南橋1〇9與cpui〇i 及其中的北橋一起運作，來啟動多處理器系統2〇〇，當 200923671 υ /υυισ. ι w z.j851twf.d〇c/p CPU101無法正常工作或線路部分損壞時’超傳送標準匯 流排中心201使CPU103的超傳送標準匯流排連接至南橋 109的超傳送標準匯流排。 參照圖3，其繪示為本發明實施例的一種多處理器系 統的具體的結構示意圖。本實施例以4個CPU為例，它包 ΟThe bridge and the second one include the North Quasi-Recharge-Routine' and the South Bridge also includes the Super-Transfer to the second CPU (10). The second bridge is used to make the South Bridge's super-transport standard busbar connection and standard row'. — CPU Step: When the first: Line 11 ° also includes an rpTT recognize..., when the crane is working or the line is partially damaged, 倭篦ί 排. ...to send the standard bus to the South Bridge's super-transport standard sink, 甬, 明明 multi-processor system and switch cpu method, so you can freely choose through the super-pass 4 quasi-convergence center _ which as = 200923671 vy z, J851twf .doc/p system CPU usage. Or if there is a problem with the CPU as the boot system, you can switch the other CPU to start the system and continue working without opening the chassis. The CPU of the booting system does not work properly or the line part is broken. 'The whole motherboard does not need to be scrapped, and another CPU can be switched to continue to use', reducing the cost of replacing the entire motherboard and reducing the cost of the entire system. The above and other objects, features and advantages of the present invention will become more <RTIgt; obvious</RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] One of the features of the present invention is that a super-transfer standard bus center is provided, and any one of the CPUs can be selected to be started, thereby reducing the cost of replacing the entire motherboard and reducing the cost of the entire system. Referring to FIG. 2, a schematic structural diagram of a multiprocessor system according to an embodiment of the present invention is shown. It includes: CPU 101, CPU 103, south bridge 109, and super transfer standard bus center 20PCPU 101 including a north bridge and at least one super transfer standard bus. The CPU 103 includes a north bridge and at least one super transfer standard bus. In the present embodiment, the CPU 101 and the CPU 103 may actually have three super transfer standard bus bars, but only two of them are used. Southbridge 109 also includes a super-transport standard bus. The super-transfer standard bus center 201 is connected to the super-transmission standard bus of the CPU 101, the CPU 103, and the south bridge 1 to 9 to connect the super-transmission standard bus of the south bridge 1 to 9 to the super-transmission standard bus of the CPU 101. Make South Bridge 1〇9 work with cpui〇i and its North Bridge to start multiprocessor system 2〇〇, when 200923671 υ /υυισ. ι w z.j851twf.d〇c/p CPU101 is not working properly or the line part In the event of damage, the 'Super Transfer Standard Bus Center 201 connects the super transfer standard bus of the CPU 103 to the super transfer standard bus of the South Bridge 109. Referring to FIG. 3, a specific structural diagram of a multiprocessor system according to an embodiment of the present invention is shown. This embodiment takes four CPUs as an example, and it includes
括：CPUKH、CPU103、CPU105、CPU107、南橋 109 以 及超傳送標準匯流排中心201。各CPU之間相互連接，且 每個CPU都包含有北橋以及3組HT匯流排。每個CPU 都能作為啟動CPU來啟動多處理器系統200。如圖， CPU103 通過 HT2 耦接至 CPU101 的 ΗΤ0，CPU105 通過 HT2麵接至CPU103的HT1 ’ CPU107通過ΗΤ0耦接至 CPU103的HT1以及通過HT1耦接至CPU101的HT2。其 中’ ΗΤ0、HT1以及HT2僅為各CPU的HT匯流排控制器 的代號’其主要作為連接之用，故本發明使用Ητο、HT1 以及HT2來代表CPU的連接端點。本實施例中，各cpu 都具有3組HT匯流排，且透過這些Ητ匯流排來兩兩連 接，但並非用以限疋本發明，任何其他型式的cpu只要具 有至少一組HT匯流排皆在本發明的保護範圍内。 南橋109也包財超舰縣匯簡。超傳送標準匯 流排中心201耗接至各個CPU，同樣地，通過HT匯流排 ,、各個CPU進行連接，用以將南橋ω 排連接至CPUHH的超傳送標準匯 ：二:早匯： rprnm ^ ^ , τ丁千匯机排，而使南橋109與 Π 橋一起運作，來啟動多處理器季统 2〇〇，當CPU101益法正當工柞弋始& -示、兄 ·、、、次止㊉工作或線路部分損壞時，超傳送 11 200923671 v / v/wi.v. x vv x.j85 ltwf.doc/p 標準匯流排中心201使其餘CPU中的任一顆CPU的超傳 送標準匯流排連接至南橋109的超傳送標準匯流排。在超 傳送標準匯流排中心201上還連接有週邊電路303，外接 於多處理為糸統200之機箱面板之上且耦接至超傳送標準 匯流排中心201，用以通過手動來控制超傳送標準匯流排 中心201，切換選擇一 CPU之一超傳送標準匯流排與南橋 之超傳送標準匯流排連接。 參照圖4，其繪示為本發明實施例的超傳送標準匯流 〇 排中心的結構示意圖。它包括多個輸入端匯流排和一個輸 出端匯流排，其中，每個輪入端匯流排4〇1以及輸出端匯 流排403都為80pin，且都是單向傳輸，因此，每個匯流 排共包含的傳輸線為： CADIN_DP[15..0], CADIN_DN[15..〇], CADOUT_DP[15..〇], CADOUT—DN[15..0]，CLKIN_DP[l..〇]，CLKIN—DN[l..〇]， CLKOUT—DP[l..〇]，CLKOUT—DN[l..〇]，CTLIN—DP[l..〇]， CTLIN_DN[l..〇]，CTLOUT—DP[l..〇]，CTLOUT_DN[1..0]。 U 因本發明採用單向傳輸，所以可保證資料傳輸時帶 寬足夠大。如圖，本發明實施例選用4路開關，其4個輸 入端匯流排401可分別連接最多4個CPU，另一個輸出端 匯流排403連接南橋’可通過選擇一 cpu之一超傳送標準 匯流排與南橋之超傳送標準匯流排連接，使連接南橋的 CPU啟動系統。圖中的多路開關為4路開關，但並非限定 本發明，其可以是大於4路的多路開關，也可以是2路或 者3路開關（用於兩顆CPU或者三顆CPU的多處理器系 12 200923671 υ/wuiu. i w ^J851twf.d〇c/p 統）其主要是做為選擇CPU之用。 參照圖5，其繪示為本發明實施例的另一種多處理器 系統的具體的結構示意圖。仍以4個CPU為例，它包括： CPU101、CPU103、CPU105、CPU107、南橋 109 以及超 傳送標準匯流排中心201。各CPU之間相互連接，且每個 CPU都包含北橋以及至少三個超傳送標準匯流排。每個 CPU都能作為啟動CPU來啟動多處理器系統200。南橋 109包括超傳送標準匯流排。超傳送標準匯流排中心2〇1 f 搞接至各個CPU，用以將南橋109的超傳送標準匯流排連 接至CPU101的超傳送標準匯流排，而使南橋1〇9與 CPU101及其中的北橋一起運作，來啟動多處理器系統 200，當CPU101無法正常工作或線路部分損壞時，超傳送 標準匯流排中心201使其餘CPU中的一顆CPU的超傳送 標準匯流排連接至南橋109的超傳送標準匯流排。各Qpu 以及超傳送標準匯流排中心201的連接關係及工作原理和 圖3中各CPU以及超傳送標準匯流排中心2〇1相同，此處 〇 不再贅述。本發明的多處理器系統200還包括基板管理控 制器501 ’通過通用輸入輸出埠（Gpi〇)耦接至該超傳送 標準匯流排中心201，它包括：軟體自動控制單元5〇3以 及檢測單元505。軟體自動控制單元5〇3用以自動控制該 超傳送標準匯流排中心2〇1，切換選擇任一 cpU2一超傳 送標準匯流排與該南橋1G9之超傳送標準匯流排連接。上 述軟體自動控制單元503通過軟體編程對超傳送標準匯流 排中心201進行控制。檢測單元5〇5用以檢測多處理器系 13 200923671 J851twf.d〇c/p 統是l啟動以及重啟多處理器系統。 田上述夕處理器系統2〇〇工作時，首先由默認的一顆 CPU啟，多處埋器系統2GG，同時，基板管理控制器501 的k測士兀5〇5開始計時並察看電平是否變化，當基板管 里控制為達到—預訂的值，如2分鐘，如果電平未發生變 化時’則可判斷多處理器系統2〇0沒有啟動，這時，可根 作手冊手動控制週邊電路3〇3，使超傳送標準匯流排 Π 中心201切換到另一顆CPU，接著重啟多處理器系統200。 或者’可由軟體自動控制器503根據預先軟體編程設定的 參數，如没定為不導通，“丨，，為導通，則可根據“〇1”數 位來確疋超傳送標準匯流排中心中的一路導通，該些 參數通過GPIO控制超傳送標準匯流排中心2〇1，使超傳 运標準匯流排中心2〇1切換到另一顆cpu，接著重啟多處 理器土統200。此處設定的參數僅為一實施例，也可通過 如设定電磁閥開關的打開角度使其中一路導通等方式，並 不局限于本實施例所表現的此種方式。 U 蒼照圖6,其繪示為本發明實施例的一種切換cpu方 法的流程圖。由上述系統之敘述，可得一種切換cPU方 法，包括： 首先’提供第一 CPU、第二CPU及南橋，第一 CPU 及第二CPU皆包括北橋以及至少一超傳送標準匯流排，且 南橋也包括超傳送標準匯流排。 接著’使南橋的超傳送標準匯流排連接至第一 CPU 的超傳送標準匯流排，而使南橋與第一 CPU及其中的北橋 14 200923671 V / W 1 V- i ** ^851twf,doc/p 一起運作，來啟動多處理器系統。 橋的超傳送標 最後，當第一 CPU無法正常工作或綠 使第二CPU的超傳送標準匿流排連接 4刀才貝裘守 準匯流排。 其具體為：The CPUKH, the CPU 103, the CPU 105, the CPU 107, the south bridge 109, and the super transfer standard bus center 201 are included. Each CPU is connected to each other, and each CPU includes a north bridge and three sets of HT bus bars. Each CPU can start the multiprocessor system 200 as a boot CPU. As shown in the figure, the CPU 103 is coupled to the IO0 of the CPU 101 through the HT2, and the CPU 105 is coupled to the HT1 of the CPU 103 via HT0 through the HT2 and the HT2 coupled to the CPU 101 via the HT1 via HT1. Where ’0, HT1 and HT2 are only the code of the HT bus controller of each CPU', which is mainly used for connection, the present invention uses Ητο, HT1 and HT2 to represent the connection endpoint of the CPU. In this embodiment, each CPU has three sets of HT bus bars, and the two busses are connected through the two bus bars, but are not limited to the present invention. Any other type of cpu has at least one set of HT bus bars. Within the scope of protection of the present invention. South Bridge 109 also Baocai Chaozhou County Huijian. The super transfer standard bus center 201 is connected to each CPU. Similarly, through the HT bus, each CPU is connected to connect the south bridge ω row to the CPUHH super transfer standard sink: 2: early sink: rprnm ^ ^ , τ Ding Qianhui machine row, and the South Bridge 109 and the 桥 bridge work together to start the multi-processor season 2 〇〇, when the CPU101 benefits the righteous work start & - show, brother,,, and When the tenth work or the line is partially damaged, the super transfer 11 200923671 v / v/wi.v. x vv x.j85 ltwf.doc/p The standard bus center 201 makes the super transfer standard bus of any of the remaining CPUs Supertransmission standard busbar connected to Southbridge 109. A peripheral circuit 303 is further connected to the super-transmission standard bus bar center 201, and is externally connected to the multi-processing chassis panel of the system 200 and coupled to the super-transfer standard bus bar center 201 for manually controlling the super-transmission standard. The bus center 201 switches and selects one of the CPUs to transmit the standard bus and the south bridge to the super-transport standard bus. Referring to FIG. 4, it is a schematic structural diagram of a super-transport standard convergence center according to an embodiment of the present invention. The utility model comprises a plurality of input terminal bus bars and an output terminal bus bar, wherein each of the wheel terminal bus bars 4〇1 and the output terminal bus bar 403 are both 80 pins, and all are one-way transmission, therefore, each bus bar The total transmission lines are: CADIN_DP[15..0], CADIN_DN[15..〇], CADOUT_DP[15..〇], CADOUT-DN[15..0],CLKIN_DP[l..〇],CLKIN— DN[l..〇], CLKOUT-DP[l..〇], CLKOUT-DN[l..〇], CTLIN-DP[l..〇], CTLIN_DN[l..〇], CTLOUT-DP[ L..〇], CTLOUT_DN[1..0]. U Since the present invention uses one-way transmission, it is ensured that the bandwidth of the data transmission is sufficiently large. As shown in the figure, the 4-way switch is selected in the embodiment of the present invention. The four input bus bars 401 can be connected to a maximum of four CPUs, and the other output bus bar 403 is connected to the south bridge. It is connected with the South Bridge's super-transfer standard bus, so that the CPU connected to the South Bridge starts the system. The multiplexer in the figure is a 4-way switch, but it is not limited to the present invention. It may be a multi-way switch larger than 4 channels, or a 2-way or 3-way switch (for multi-processing of two CPUs or three CPUs). The system is 12 200923671 υ/wuiu. iw ^J851twf.d〇c/p system) It is mainly used for CPU selection. Referring to FIG. 5, it is a detailed structural diagram of another multiprocessor system according to an embodiment of the present invention. Still taking four CPUs as an example, it includes: a CPU 101, a CPU 103, a CPU 105, a CPU 107, a south bridge 109, and a super transfer standard bus center 201. Each CPU is connected to each other, and each CPU contains a north bridge and at least three super transfer standard bus bars. Each CPU can boot the multiprocessor system 200 as a boot CPU. Southbridge 109 includes a super-transport standard bus. The super-transfer standard bus center 2〇1 f is connected to each CPU to connect the super-transmission standard bus of the south bridge 109 to the super-transmission standard bus of the CPU 101, and the south bridge 1〇9 together with the CPU 101 and the north bridge thereof Operation to start the multiprocessor system 200, when the CPU 101 fails to work normally or the line is partially damaged, the super transfer standard bus center 201 connects the super transfer standard bus of one CPU of the remaining CPUs to the super transfer standard of the south bridge 109. Bus bar. The connection relationship and working principle of each Qpu and the super-transfer standard bus center 201 are the same as those of the CPU and the super-transfer standard bus center 2 in FIG. 3, and will not be described here. The multiprocessor system 200 of the present invention further includes a baseboard management controller 501' coupled to the super transfer standard bus center 201 via a universal input/output port (Gpi〇), which includes: a software automatic control unit 5〇3 and a detection unit 505. The software automatic control unit 5〇3 is used to automatically control the super-transfer standard bus center 2〇1, and switch to select any cpU2-super-transfer standard bus bar to connect with the super-transfer standard bus bar of the south bridge 1G9. The software automatic control unit 503 controls the super transfer standard bus center 201 by software programming. The detecting unit 5〇5 is used to detect the multiprocessor system. 13 200923671 J851twf.d〇c/p The system is to start and restart the multiprocessor system. When the above-mentioned processor system is working, the first CPU is started by the default one, and the multi-embedded system 2GG is started. At the same time, the k-measurement of the baseboard management controller 501 starts to count and check whether the level is Change, when the substrate tube is controlled to reach the value of the reservation, such as 2 minutes, if the level has not changed, then it can be judged that the multiprocessor system 2〇0 is not activated. At this time, the manual can be used to manually control the peripheral circuit 3 〇3, the super transfer standard bus bar 201 center 201 is switched to another CPU, and then the multiprocessor system 200 is restarted. Or 'the parameter that can be set by the software automatic controller 503 according to the pre-software programming, if it is not determined to be non-conducting, "丨,, to be conductive, the one in the super-transfer standard bus center can be confirmed according to the "〇1" digit. Turning on, these parameters are controlled by the GPIO to super-transfer the standard bus center 2〇1, so that the super-transport standard bus center 2〇1 is switched to another cpu, and then the multi-processor system 200 is restarted. The parameters set here For example, the manner in which one of the paths is turned on, such as setting the opening angle of the solenoid valve switch, is not limited to the manner represented by the embodiment. U 照照图6, which is shown as A flowchart of a method for switching a cpu according to an embodiment of the present invention. A method for switching a cPU can be obtained by the foregoing system, including: first providing a first CPU, a second CPU, and a south bridge, the first CPU and the second CPU each including a north bridge And at least one super transfer standard bus, and the south bridge also includes a super transfer standard bus. Then 'connect the south bridge's super transfer standard bus to the first CPU's super transfer standard bus, and make the south The bridge works with the first CPU and its Northbridge 14 200923671 V / W 1 V-i ** ^851twf, doc/p to start the multiprocessor system. The bridge's super-transmitter is finally, when the first CPU is not working properly. Or green to make the second CPU's super-transmission standard bus stop connected with 4 knives to be compliant with the bus. The specifics are:
S610 :檢測第一 CPU 疋否工作u苜多處理哭系统上 電運行後，基板管理控制器開始計時 ^是否S610: Detecting whether the first CPU is working or not, and after processing the powering system, the baseboard management controller starts timing.
化’當基板管理控制器達到一預訂的值，如看5;:疋= 電平未發生變化時’則可判斷多處理器系統沒有啟動。 、，S620:切換選擇多處理器系統的另—CPU之一超傳 送標準匯賴與祕之超傳送鮮匯流排連接。 S630 :重啟多處理器系統。 、綜上所述，在本發明之多處理器系統及切換cpu方 ^ ’可通過超傳送鮮匯流排巾心自崎擇城哪來作 ，啟動系統的cpu使用。或者如果作為啟動系統的cpu 出現問題，不用打開機箱就可以按照手冊切換另一顆c P U 〇 t啟動系統繼續工作。啟動系統的CPU不能正常工作或者 、、路部分壞了’整塊主板也不用報廢，可以切換另二顆 咖繼續使用，減少了更換整塊主板的費用，降低了成本。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限J本發明，任何熟習此技藝者，在不脫離本發明之精神 圍内，當可作些許之更動與潤飾，因此本發明之保護 乾圍當視後附之申請專利範圍所界定者為準。 β 【圖式簡單說明】 圖1繪不為習知AMD多處理器系統的結構示意圖。 15 200923671 --------- ^j851twf.doc/p 圖2繪示為本發明實施例的一種多處理器系統的結構 示意圖。 圖3繪示為本發明實施例的一種多處理器系統的具體 的結構示意圖。 圖4繪示為本發明實施例的超傳送標準匯流排中心的 結構不意圖。 圖5繪示為本發明實施例的另一種多處理器系統的具 體的結構示意圖。 (1 圖6繪示為本發明實施例的一種切換CPU方法的流 程圖。 【主要元件符號說明】 101 ： CPU 103 ： CPU 105 ： CPU 107 ： CPU 109 :南橋 111 :動態隨機存取記憶體 〇 200 :多處理器系統 201 :超傳送標準匯流排中心 303 :週邊電路 401 :輸入端匯流排 403 :輸出端匯流排 501 :基板管理控制器 503 ··軟體自動控制單元 505 :檢測單元 16When the substrate management controller reaches a predetermined value, see 5;: 疋 = the level has not changed, then it can be judged that the multiprocessor system is not started. , S620: One of the other CPUs that switch to select the multi-processor system is super-passed to send the standard remittance and the super-transmission fresh bus connection. S630: Restart the multiprocessor system. In summary, in the multi-processor system and the switching cpu side of the present invention, it is possible to start the cpu use of the system by super-transferring the fresh bus. Or if there is a problem with the cpu as the booting system, you can switch another c P U 按照 t to start the system and continue working without opening the chassis. The CPU of the booting system can't work normally, or the road part is broken. The whole motherboard does not need to be scrapped. You can switch the other two coffee beans to continue to use, which reduces the cost of replacing the whole motherboard and reduces the cost. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the present invention may be modified and retouched without departing from the spirit of the invention. The protection scope is subject to the definition of the patent application scope attached. β [Simple description of the drawing] Figure 1 is a schematic diagram showing the structure of a conventional AMD multiprocessor system. 15 200923671 --------- ^j851twf.doc/p FIG. 2 is a schematic diagram showing the structure of a multiprocessor system according to an embodiment of the present invention. FIG. 3 is a schematic structural diagram of a multiprocessor system according to an embodiment of the present invention. FIG. 4 is a schematic diagram showing the structure of a super transfer standard bus center according to an embodiment of the present invention. FIG. 5 is a schematic diagram showing the structure of another multiprocessor system according to an embodiment of the present invention. (1) FIG. 6 is a flowchart of a method for switching CPUs according to an embodiment of the present invention. [Description of Main Components] 101: CPU 103: CPU 105: CPU 107: CPU 109: South Bridge 111: Dynamic Random Access Memory 〇 200: multiprocessor system 201: supertransmission standard bus center 303: peripheral circuit 401: input terminal bus 403: output terminal bus 501: substrate management controller 503 · software automatic control unit 505: detection unit 16