200425670 五、發明說明（1) 相關申請案 本申請案係依據申請曰為2003年4月4曰之美國先行申 請案（Provisional Applicati〇n)案號 6〇/46〇，523主張 優先權’其内谷在此作為參考並包含於本申請案。 一、 【發明所屬之技術領域】 本發明係與數位通訊相關的領域，明確地來說，本發 明係關於數位通訊的錯誤隱匿。 二、 【先前技術】 _ 用於無線傳輸聲音信號的系統在這個領域是眾所周知· 的。圖一表示這樣的系統1 〇 〇之典型架構的方塊圖。音頻 設備1 02為一音源，舉例來說可能是一麥克風、一 FM調諧 器/接收器（Fm tuner/receiver)或是一類比錄音媒體。從 音頻设備1 0 2來的聲音信號被提供到一聲音類比至數位轉 換器（analog to digital converter，ADC)104以轉換成 數位樣本。接著，這些數位樣本被提供到一數位數據機發 射器（digital Modem transmitter，TX)106〇 數位數據機 發射器1 0 6可包括一格式化單元（圖上未示），以將數位樣 本格式化成一特殊的格式。數位數據機發射器6可包括 一前向錯誤校正（forward error correction，FEC)編碼 器（圖上未示），以將錯誤校正碼加入到被格式化的資料 中，以及包括一調變器（圖上未示），以將已格式化的資 料調變到載波信號中。調變器的輸出可被提供到一渡波=200425670 V. Description of the invention (1) Related applications This application claims priority based on the US Advance Application (Provisional Applicati) No. 60 / 46〇, 523, which was filed on April 4, 2003. Uchiya is hereby incorporated by reference and is incorporated herein. I. [Technical Field to which the Invention belongs] The present invention relates to the field of digital communication. Specifically, the present invention relates to the concealment of errors in digital communication. 2. [Prior art] _ The system for wirelessly transmitting sound signals is well known in this field. Figure 1 shows a block diagram of a typical architecture of such a system 100. Audio device 102 is a sound source. For example, it may be a microphone, an FM tuner / receiver, or an analog recording medium. The sound signal from the audio device 102 is provided to a sound analog to digital converter (ADC) 104 to be converted into digital samples. These digital samples are then provided to a digital modem transmitter (TX). 106 The digital modem transmitter 106 may include a formatting unit (not shown) to format the digital samples into A special format. The digital modem transmitter 6 may include a forward error correction (FEC) encoder (not shown) to add an error correction code to the formatted data, and include a modulator ( (Not shown) to modulate the formatted data into the carrier signal. The output of the modulator can be provided to a crossing =
200425670 五、發明說明（2) (圖上未示），並且在被送到射頻（radi〇 frequency， RF)發射器1 08經由天線11 〇傳送之前，由一數位至類比轉 換器（digital to analog converter，DAC)(圖上未示）轉 換成一類比信號。 在接收端’所傳送的信號將由射頻接收器（RX)114經 由天線11 2所接收。所接收的信號將被提供到數位數據機 接收器（digital modem receiver)116。數位數據機接收 器1 1 6可包括多個ADC (圖上未示），用以將所接收信號數 位化’並且包括一解調器（demodulator，圖上未示），以鲁 將聲音資料從數位格式中還原。數位數據機接收器丨丨6更 可包括一 FEC解碼器（圖上未示），以還原原先被傳送的 資料，以及包括一解格式化器（de-f0rmatter)(圖上未 示^，以解格式化已解調的資料。數位數據機接收器丨i 6 接著提供已解調及已解格式化的資料到聲音Dac 118，以 轉換成由揚聲器1 20再現（reproduce)的一類比信號。 在聲音信號傳輸中所產生的問題是，圖一中由射頻發 射器108所傳送的已調變载波信號在傳輸期間容易遭受數 位化資料的惡化（corruption),例如由於太接近其它的發§ 射源。舉例來說，雜訊可惡化由射頻發射器1 〇 _傳送的 2號，並且可能因為資料中的錯誤而造成在RF接收器ιΐ4 二法回復資料。這種情形的結果會使揚聲器12〇出現破 曰、爆音或其他不舒服的聲音。200425670 V. Description of the invention (2) (not shown in the figure), and before being transmitted to a radio frequency (RF) transmitter 1 08 via an antenna 11 0, a digital to analog converter (digital to analog converter (DAC) (not shown) into an analog signal. The signal transmitted at the receiver 'will be received by the radio frequency receiver (RX) 114 via the antenna 11 2. The received signal is provided to a digital modem receiver 116. The digital modem receiver 1 1 6 may include multiple ADCs (not shown in the figure) to digitize the received signal 'and include a demodulator (not shown in the figure), so that the sound data can be converted from Restore in digital format. The digital modem receiver 6 can further include an FEC decoder (not shown in the figure) to restore the original transmitted data, and a de-formatter (de-f0rmatter) (not shown in the figure ^, to Deformat the demodulated data. The digital modem receiver 丨 i 6 then provides the demodulated and deformatted data to the sound Dac 118 for conversion to an analog signal reproduced by the speakers 120. The problem that arises in the transmission of sound signals is that the modulated carrier signal transmitted by the RF transmitter 108 in FIG. 1 is susceptible to the corruption of digitized data during transmission, for example because it is too close to other transmitters. For example, noise can worsen the number 2 transmitted by the RF transmitter 10 __ and may cause the receiver to recover data at the RF receiver due to errors in the data. The result of this situation will make the speaker 12 〇 Broken, crackling or other uncomfortable sounds appear.
200425670 五、發明說明（3) 一種最小化被調變載波信號這種惡化負面效應的方法 ^ 數位化樣本供一定程度的冗餘（adun(JanCy)。這些 几餘可以由資料編碼提供。資料編碼係由將冗餘的資訊加 到原始貝料中所組成，這樣的話被接收已編碼的資料串的 1誤可^被識別出來並更正。在資料干擾無法更正的情況 】生^刖二被加入的冗餘程度決定所接收信號中可以更正 、，誤數量。典型的編碼技術識別並更正在資料串中單獨 位7C的錯誤。在一個資料編碼例子中，上述fec編碼器可 使用眾所周知的碼來實行前向錯誤校正編碼，諸如 B〇se^Chaudhuri^Hocquengheffl(BCH)^ Reed-So1〇m〇n^ ·、、、’或疋其他類似碼，藉以消除相對短時間的錯誤。 丨鞋床項，術·交錯（lnterleavinS)也可使用。交錯 L媒1被用來分離正常會被一起傳送之傳輸序列的已數位 L. ^ i知技藝中，交錯程序在傳送之前重新安排資 =料=例來說，任何兩個連續的資料符元會被特定數目的 較大ms iaving)成原始格式。因此，交錯程序允許 於傳逆：,ΐ ί送序列中有大量的錯誤可以藉由展開錯誤 |於傳送序列被更正。 丨數位號的結果’力。諸在此交錯資料信號類型的 化樣本惡化並不影響原來傳送序列的連續位元。並且200425670 V. Description of the invention (3) A method for minimizing the negative effects of the modulated carrier signal deterioration ^ Digital samples are provided for a certain degree of redundancy (adun (JanCy). These few can be provided by data encoding. Data encoding It is composed of adding redundant information to the original shell material. In this case, 1 error of the received encoded data string can be identified and corrected. In the case where the data interference cannot be corrected, students are added. The degree of redundancy determines the number of errors that can be corrected in the received signal. Typical coding techniques identify and correct individual bit 7C errors in the data string. In an example of data encoding, the above-mentioned fec encoder can use well-known codes to Implement forward error correction coding, such as B〇se ^ Chaudhuri ^ Hocquengheffl (BCH) ^ Reed-So1〇m〇n ^, ,,, ', or other similar codes, to eliminate relatively short-term errors. Interleaving can also be used. Interleaving L medium 1 is used to separate the digital L of the transmission sequence that would normally be transmitted together. ^ In the known art, the interleaving procedure is performed before transmission. The new funding arrangements = = frit embodiment, any two consecutive data symbols will be a certain number of larger ms iaving) into the original format. Therefore, the interleaving procedure allows the transmission sequence to be reversed: there are a large number of errors in the transmission sequence that can be corrected by expanding the error in the transmission sequence.丨 The result of the digital number 'force. The deterioration of the samples of these interleaved data signal types does not affect the continuous bits of the original transmission sequence. and
第9頁 200425670 五、發明說明（4) -- 在解交錯之後，所接收的編碼資料會有隨時間展開之位元 錯誤，其可利用在編碼階段所加入冗餘資料更正。如此在 接收器中會檢驗有錯誤更正碼的交錯數位樣本群 (group)，並且更正有錯誤的交錯數位樣本群。 然而，像這樣精密的錯誤更正碼無法更正所有數位樣 本的位元錯誤。在數位化樣本無法更正的例子中，另一種 技術·内插法（interpolation)可被用來試著隱匿不可更 正的數位化樣本。習知的内插程序經由内插鄰近數位化樣 本來評估那些無法更正的數位化樣本的取樣值，以隱匿任 何無法更正數位化樣本的效應。 然而’内插法會因為傳送序列中太多的錯誤造成無法 义内插中提供足夠多的好樣本而無法執行。換句話說，内 插法技術需要足约多的好樣本來估計或是預測因錯誤而失 去的樣本。例如當有鄰近的位元連續發生錯誤（也就是連 =兩個鄰接的壞樣本）時，利用兩個鄰接的好樣本内插至 壞樣本的線性内插法之第一階内插器（first-〇rdeie interpolator)將不夠有效。高階的内插器被用來改善鄰 居樣本連續發生錯誤時内插程序的效率。然而即使是高階 的内插器也會因為發生多個錯誤的情況下，而使隱匿錯誤 的能力受到限制。 任何無法更正或是可以藉由上述技術隱匿的數位化樣Page 9 200425670 V. Description of the invention (4)-After de-interlacing, the received encoded data will have bit errors that expand over time, which can be corrected using redundant data added during the encoding phase. In this way, the receiver will check the group of interleaved digital samples with error correction codes, and correct the group of interleaved digital samples with errors. However, precision error correction codes like this cannot correct bit errors in all digital samples. In cases where digitized samples cannot be corrected, another technique, interpolation, can be used to try to hide uncorrectable digitized samples. The conventional interpolation procedure evaluates the sampling values of those digitized samples that cannot be corrected by interpolating adjacent digitized samples to hide the effect of any digitized samples that cannot be corrected. However, the 'interpolation method' cannot be performed because there are too many errors in the transmission sequence to provide enough good samples in the sense interpolation. In other words, the interpolation technique requires a sufficient number of good samples to estimate or predict the samples lost due to errors. For example, when there are consecutive errors in adjacent bits (that is, even = two adjacent bad samples), the first-order interpolator of the linear interpolation method that uses two adjacent good samples to interpolate to the bad samples (first -〇rdeie interpolator) will not be effective enough. Higher-order interpolators are used to improve the efficiency of the interpolation procedure when consecutive errors occur with neighboring samples. However, even high-order interpolators can limit the ability to hide errors because multiple errors occur. Any digital transformation that cannot be corrected or that can be hidden by the above techniques
第10頁 200425670 五、發明說明（5) 本錯誤都可以被靜音（mute)。然而，突然間啟動靜音會對 使用者聆聽再生聲音上造成錯亂與困擾。 因此，需要一種低複雜的裝置、系統與方法來隱匿錯 誤，以建立高感知聲音品質。 二、【發明内容】 本發明的實施例提供一低複雜的裝置、系統與方法來 隱匿錯誤，以建立高感知聲音品質。Page 10 200425670 V. Description of the invention (5) This error can be muted. However, the sudden activation of mute can cause confusion and annoyance to the user when listening to the reproduced sound. Therefore, a need exists for a low-complexity device, system, and method to conceal errors in order to establish high perceived sound quality. 2. SUMMARY OF THE INVENTION Embodiments of the present invention provide a low-complexity device, system, and method for concealing errors to establish a high perceived sound quality.
根據本發明的第一實施例，係揭露一種用來隱匿數位 化資料錯誤的裝置與方法。其裝置具有用以接收數位資料 的一輸入，以及用以在錯誤隱匿之後輸出數位資料之一輸 出。其裝置包括至少一内插器，用以從其他已接收之數位 資料樣本估計已接收數位資料中一樣本的值。上述至少一 内插器有一用以輸入已接收數位資料之輸入，以及一用以 輸出已接收數位資料之樣本的估計值之輸出。 其裝置更包括至少一保留單元（holding unit)，具有 一輸入’用以只有當樣本是零錯誤（error free)時，選擇_ 性地接收已接收數位資料的樣本，以及一輸出，用以輸出 已接收數位資料中零錯誤樣本。零錯誤樣本可為之前所保 邊的零錯誤樣本，例如為最新沒有錯誤的樣本。根據本發 明的實施例，至少一保留單元亦可以接受至少已經被内插According to a first embodiment of the present invention, an apparatus and method for concealing digital data errors are disclosed. Its device has an input for receiving digital data and an output for outputting digital data after error concealment. The device includes at least one interpolator for estimating the value of the sample in the received digital data from other received digital data samples. The at least one interpolator has an input for inputting the received digital data and an output for outputting an estimated value of a sample of the received digital data. The device further includes at least one holding unit having an input 'for selectively receiving samples of the received digital data only when the samples are error free, and an output for outputting. Zero error samples in digital data have been received. The zero error sample can be the zero error sample of the previously guaranteed edge, for example, the latest error-free sample. According to an embodiment of the present invention, at least one reserved unit may also accept that at least it has been interpolated.
第11頁 200425670 五、發明說明（6) __ |部份處S的接收數位資料。纟—實施 I元的輸入跟至少—内插 至乂―保留單 爾态的輸入並聯（ln para〗lel)。 此外，其裝晉& k I資料之樣本的估計值盥，擇窃，用以在輸出已接收數位 丨間做選擇，零錯誤様^ 11出已接收數位資料之零錯誤樣本 、樣本可以是之前被保留的零錯誤樣本。 根據本發明更淮— |以接收一信號，其 ^實施例，係揭露一種接收器，用 式傳送的數位資料，*匕3由一發射器以封包（packet)格 其接收器包括有一内栖f用以隱匿在數位化資料的錯誤。 從已接收數位化資料沾=份，其包括至少一内插器，用以 I樣本的值。 、/ 、/、他樣本估計已接收數位化資料之 内插邛伤更包括至少一-只有當樣本是零錯誤時 ，具有一輸入，用以 本。根據本發明的實施、 接收已接收數位資料的樣 受已經被内插器至少部^声上述至少一保留單元亦可以接 施例中，至少一保留二:處理的已接收數位資料。在一實 聯。上述内插部分份的輸入跟至少一内插器的輸入並 數位資料之樣本的估 ^ $ 一選擇器，用以在輸出已接收 樣本間做選擇，其零錯樣已接收數位資料之零錯誤 樣本。 、m本可以是之前被保留的零錯誤Page 11 200425670 V. Description of the invention (6) __ | Part of the received digital data of S.纟 —implement the input of I element in parallel with at least—interpolate to 乂 —retain the singular state input (ln para 〖lel). In addition, the estimated value of the sample containing the & k I data is selected and used to choose between outputting the received digits. Zero errors. ^ 11 zero error samples and samples of received digital data can be Previously retained zero error samples. In order to receive a signal according to the present invention, the first embodiment of the present invention discloses a receiver for digital data transmission. * 3 is formed by a transmitter in a packet format, and the receiver includes an inhabitant. f Used to hide errors in digitized data. A copy of the received digitized data includes at least one interpolator for the value of the I sample. 、 / 、 / 、 Other samples are estimated to have received digitized data. The interpolated stigma also includes at least one-only when the sample is zero error, there is an input for the cost. According to the implementation of the present invention, a sample of received digital data is received by the interpolator at least partly. At least one of the above-mentioned reserved units may also be used in the embodiment, at least one of which is reserved: processed received digital data. In a real alliance. The input of the above-mentioned interpolation part and the input of at least one interpolator and the estimation of the digital data samples ^ $ A selector is used to choose between output received samples, and its zero error sample has zero error of the received digital data sample. , M could have been a zero error previously reserved
W 第12頁 200425670 五、發明說明（7) 根據本發 |統，包括有： I收器，用以接 器，用以從已 |化資料之樣本 |用以只有當樣 |的樣本。根據 1受已經被内插 |施例中，至少 聯。上述接收 位資料之樣本 本間做選擇 本。 明更進一 一發射器 收數位化 接收數位 的值，以 本是零錯 本發明的 器至少部 一保留單 器更包括 的估計值 零錯誤樣 步的實施例 ，用以傳送 資料。上述 化資料之其 及至少一保 誤時，選擇 實施例，至 分處理的已 元的輸入跟 係揭露一種通信系 數位化資料 接收器具有至少一内插 他樣本估計所接收數位 留卓元’具有一輸入， 性接收已接收數位資料 少一保留單元亦可以接 接收數位資料。在一實 以及一接 有一選擇器 與輸出已接 本可以是之 至少一内插器的輸入並 出已接收數 之零錯誤樣 零錯誤樣 ，用以在輸 收數位資料 前被保留的 根據本發明的實施例，數位資料是指標準格式的聲音 數位資料，諸如但不限定為I2s(inter—IC sound)。聲音 資料、/、有至〉、有一聲音資料區塊（b 1 o c k )的封包被傳送 2接=至）一錯誤指示為在聲音資料區塊上執行CRC檢 |二的、纟:至少一錯誤指示被用來選擇性地致能上述至少 保留單70 ’以接收數位資料中的零錯誤樣本，並且用來 =出已接收數位資料之樣本的估計值與輸出已接收數位 I k料之零錯誤樣本間做選擇。 根據本發明的實施例，上述内插器可以是第一到N階 第13頁 200425670 五、發明說明^ " " ' ' " =内插器。此外，上述内插器可以是多階内插器。當内插 器為多階内插器時，内插器的階數可以根據如訊嗓比 (signal-to-n〇ise rati〇，SNR)及 /或錯誤率來選擇。 這些以及其他有關本發明實施例的特徵及優點都可以 在热知此類技藝人士閱讀本發明實施例的詳細敘述配合圖 式與申請專利範圍後明瞭。 四、【實施方式】 以下所描述之較佳實施例中，係參閱所附圖，附圖以 圖示的方式說明本發明可以實施的實施例。需明白其他實 施例也可以實現，並且結構上的改變可以不脫離本發明之 較佳實施例之範圍。 本發明係與數位通訊的領域相關，明確地來說，本發 明關於數位通訊中聲音信號的錯誤隱匿。本發明實施例可 以被運用在多種通訊電子上，包括無線傳輸系統及有線系 統。因此，本發明在此描述的實施例可以應用在不同的通 訊系統，包括無線應用如但不限定為無線區域網路 (wireless local area network, wireless LAN)、無線 個人通訊裝置包括收音機、行動電話、行動無線電話、 個人數位助理（personal digital assistant，PDA)、個 人電腦記憶卡國際協會（Persona 1 Computer Memory Card International Association， PCMCIA)電腦介面應用、遙W Page 12 200425670 V. Description of the invention (7) According to the present system, it includes: I receiver, which is used to connect the sample of the data | for the sample of the sample only. Under 1 subject has been interpolated | Sample of the above-mentioned receiving data. The transmitter further digitizes the value of the received digits, so that the received digits are zero error. The device of the present invention has at least one reserved unit, and the estimated value includes zero error sample embodiments for transmitting data. When the above-mentioned data and at least one guarantee are made, an embodiment is selected, and the input of the sub-processed data is disclosed as a communication coefficient. The data receiver has at least one interpolated other sample to estimate the received digits. With one input, the received digital data is received, and one reserved unit can also receive digital data. In a real and one after another, a selector and an output connected can be the input of at least one interpolator and output the zero error sample of the received number. The zero error sample is used to retain the data before the digital data is received. In the embodiment of the invention, the digital data refers to audio digital data in a standard format, such as but not limited to I2s (inter-IC sound). Audio data, //, there is>, a packet with a sound data block (b 1 ock) is transmitted 2 connected = to)-an error indication is to perform a CRC check on the sound data block | The instruction is used to selectively enable at least 70 'of the above-mentioned reserve order to receive zero error samples in the digital data, and is used to = estimate the samples of the received digital data and output zero errors of the received digital data Choose between samples. According to the embodiment of the present invention, the above-mentioned interpolator may be the first to N stages. Page 13 200425670 V. Description of the invention ^ " " '' " = Interpolator. In addition, the above-mentioned interpolator may be a multi-order interpolator. When the interpolator is a multi-order interpolator, the order of the interpolator can be selected according to, for example, signal-to-noise rati0 (SNR) and / or error rate. These and other features and advantages of the embodiments of the present invention will become clear after a person skilled in the art reads the detailed description of the embodiments of the present invention, the accompanying drawings, and the scope of patent application. 4. [Embodiments] In the preferred embodiments described below, reference is made to the accompanying drawings, which illustrate the embodiments in which the present invention can be implemented by way of illustration. It should be understood that other embodiments may also be implemented, and structural changes may be made without departing from the scope of the preferred embodiments of the present invention. The present invention relates to the field of digital communication. Specifically, the present invention relates to error concealment of sound signals in digital communication. The embodiments of the present invention can be applied to a variety of communication electronics, including wireless transmission systems and wired systems. Therefore, the embodiments described herein can be applied to different communication systems, including wireless applications such as, but not limited to, wireless local area network (wireless local area network, wireless LAN), wireless personal communication devices including radios, mobile phones, Mobile radiotelephone, personal digital assistant (PDA), personal computer memory card international association (Persona 1 Computer Memory Card International Association (PCMCIA) computer interface application, remote
第14頁 200425670 五、發明說明（9) 測系統（t e 1 e m e t r y s y s t e m )、全球定位系統（g 1 〇 b a 1 positioning system，GPS)及其他射頻裝置。在這些應用 中，實現低廉且低複雜度錯誤隱匿系統為一般的需求。 如前所討論，傳統錯誤更正及隱匿技術是複雜的，並 且未提供令人滿意的錯誤更正及/或隱匿。本發明的實施 例提供一種用以隱匿錯誤以建立高感知的聲音品質的低複 雜裝置及方法。其裝置及方法的實施例不要求複雜的錯誤 更正碼，而是利用低複雜度的内插器來隱匿。更進一步來 說’其裝置及方法的實施例並不排除錯誤更正與交錯技術 的使用，並且可以強化利用現存錯誤更正與交錯之系統的 強健性。 參閱圖二及圖三，其為根據本發明實施例之示範性無 線聲音晶片組。圖二中之數位無線發射器2 〇 2接受來自聲 音發射器2 1 0的聲音A D C方塊2 1 2及功率控制發光二極體2 1 4 來的輸入。根據本發明實施例，聲音設備2 1 6提供聲音來 源至#音A D C方塊212’其接著以如但不限定在gpj)iF(s〇ny Philips Digital Interface)及I2S的標準格式給數位數 據機發射裔204。為了說明起見’此示範性無線聲音晶片 組將以由LRCK、BCK及資料信號所組成的I 2S聲音格式來描 述。 數位數據機發射器2 0 4將I 2 S資料袼式化並調變。調變Page 14 200425670 V. Description of the invention (9) Measuring system (t e 1 e m t r y s s s t em), global positioning system (g 1 0 b a 1 positioning system, GPS) and other radio frequency devices. In these applications, it is a common requirement to implement an inexpensive and low complexity error concealment system. As previously discussed, traditional error correction and concealment techniques are complex and do not provide satisfactory error correction and / or concealment. Embodiments of the present invention provide a low-complexity device and method for concealing errors to establish a high perceived sound quality. Embodiments of the device and method do not require complex error correction codes, but use a low-complexity interpolator to hide them. Furthermore, the embodiment of the apparatus and method does not preclude the use of error correction and interleaving techniques, and can strengthen the robustness of a system utilizing existing error correction and interleaving. Referring to FIG. 2 and FIG. 3, an exemplary wireless sound chipset according to an embodiment of the present invention is shown. The digital wireless transmitter 2 in FIG. 2 receives input from the sound A D C block 2 1 2 and the power control light emitting diode 2 1 4 from the sound transmitter 2 10. According to the embodiment of the present invention, the sound device 2 1 6 provides a sound source to the #aud ADC block 212 ', which is then transmitted to the digital modem in a standard format such as but not limited to gpj) iF (sony Philips Digital Interface) and I2S. Descent 204. For illustrative purposes', this exemplary wireless sound chipset will be described in an I 2S sound format consisting of LRCK, BCK, and data signals. The digital modem transmitter 204 formats and modulates the I 2 S data. Modulation
第15頁 200425670 五、發明說明（ίο) 後的資料由射頻發射器2 0 6升頻（up convert)成射頻信 號，並經由天線2 0 8傳輸出去。功率控制發光二極體區塊 2 1 4可產生控制信號，如重置（r e s e t )、電源開啟控制給數 位數據機發射器204及射粮發射器20 6。數位數據機發射器 2 0 4可產生如用於靜音的監測信號到功率控制發光二極體 區塊2 1 4。 在圖三中之數位無線接收器2 1 8中，射頻接收器2 2 4從 天線2 2 0、2 2 2接收被傳送信號，並將被傳送信號降頻 (down convert )成一基頻（baseband)信號。此基頻信號接· 著被數位數據機接收器22 6所解調，並被格式化成I2S格 ^ 式。I 2S資料被送到聲音揍收器2 28。聲音DAC 2 3 0將數位 聲音信號轉換成適合由揚聲器23 2所放大的信號。功率控 制發光二極體2 3 4可以產生如重置、電源開啟控制的控制 4吕號給數據機接收器226及射頻接收器224。數位數據機接 收器2 2 6可產生例如用於靜音和錯誤率指示器之監測信號 給功率控制發光二極體234。 圖四係為一可用於本發明實施例之示範性數位數據機 發射器2 0 4的方塊圖。根據本發b月之較佳實施例，數位聲 音輸入是建立在I2S數位聲音標準格式，其如圖四所示由 L R C K、B C K及資料信號所組成。根據本發明實施例，聲音 介面區塊2 3 6接收L R C K、B C K及資料信號。當一預備信號啟 動’聲音介面區塊2 3 6的輸出資料由封包格式器區塊238所Page 15 200425670 V. The information after the description of the invention (ίο) is up-converted by the RF transmitter 206 into a radio frequency signal and transmitted through the antenna 208. The power control light-emitting diode block 2 1 4 can generate control signals such as reset (r e s e t), power-on control to the digital modem transmitter 204 and the grain transmitter 20 6. The digital modem transmitter 2 0 4 can generate a monitoring signal such as that used for mute to the power control light emitting diode block 2 1 4. In the digital wireless receiver 2 1 8 in FIG. 3, the radio frequency receiver 2 2 4 receives the transmitted signal from the antennas 2 2 0 and 2 2 2 and down-converts the transmitted signal to a baseband. )signal. This baseband signal is demodulated by the digital modem receiver 22 6 and formatted in I2S format. The I 2S data is sent to the sound receiver 2 28. The sound DAC 2 3 0 converts the digital sound signal into a signal suitable for being amplified by the speaker 23 2. The power control light-emitting diodes 2 3 4 can generate controls such as reset and power-on control to the modem receiver 226 and the radio frequency receiver 224. The digital modem receiver 2 2 6 may generate, for example, a monitoring signal for a mute and error rate indicator to the power control light emitting diode 234. Figure 4 is a block diagram of an exemplary digital modem transmitter 204 that can be used in embodiments of the present invention. According to a preferred embodiment of the present invention, the digital audio input is based on the I2S digital audio standard format, which is composed of L R C K, B C K and data signals as shown in FIG. 4. According to the embodiment of the present invention, the sound interface block 2 3 6 receives L R C K, B C K and data signals. When a preparation signal is activated, the output data of the sound interface block 2 3 6 is provided by the packet formatter block 238.
第16頁 200425670 五、發明說明（11) ' -- 接受。到封包格式器區塊238的輸入資料可能需要緩衝以 確保聲音發射器210(圖二）傳送聲音資料不被中斷。如上 所討論’數位聲音輸入可以是任何格式。由於 數位，所以習知適合的緩衝與程序可以應用在聲音介面區 塊236,以產生封包格式器所需要的格式。符元時脈256用 以在聲音介面區塊23 6及封包格式器區塊238間提供一同步 介面。封包格式器區塊23陇受聲音介面區塊236所輸出的 貝料，並產生特定格式的封包，如圖五所示的格式。當資 料被封包格式器區塊238格式化後，將接著被傳送至調變 器 242 〇 在以I 2S為聲音格式的較佳實施例中，聲音資料以 H224MHZ或3. 〇72MHz的速率連續地到達聲音介面區塊236 入端。因為I2S串聯地產生聲音資料，並且也因為聲 ^資枓需要被緩衝’因此實現一個串聯至並聯轉換器 、/二1^$1丨:0»:_1161(：011^1^)是必須的，以使資料可 二·、、:丨二=疋或十六位元寬度的暫存器檔案（register \ 科可以同時緩衝N個區塊。在N個區塊被緩 :二_ 7二二故聲音資料被封包格式器238格式化成如圖 .^ 式。為了減低潛伏期（latency)，封包格 2 Ξ彳if义速率被計時，使聲音資料的次_區塊已 被緩衝刖，封包可以姑坆斗 Μ。# it ϋ Μ #序的基準產生符合前述速率的時 脈根據本發明實施例，其他先進先出（nfst h fifstPage 16 200425670 V. Description of Invention (11) '-Accept. The input data to the packet formatter block 238 may need to be buffered to ensure that the transmission of the audio data by the sound transmitter 210 (Figure 2) is not interrupted. As discussed above, 'digital sound input can be in any format. Due to the number, conventionally suitable buffers and programs can be applied to the sound interface block 236 to produce the format required by the packet formatter. The symbol clock 256 is used to provide a synchronous interface between the audio interface block 236 and the packet formatter block 238. The packet formatter block 23 receives the shell material output by the sound interface block 236, and generates a packet in a specific format, as shown in Figure 5. When the data is formatted by the packet formatter block 238, it will then be transmitted to the modulator 242. In the preferred embodiment using I 2S as the sound format, the sound data is continuously at a rate of H224MHZ or 3.02 MHz. Reached the end of the sound interface block 236. Because I2S generates sound data in series, and because sound resources need to be buffered, it is necessary to implement a series-to-parallel converter. / 2 1 ^ $ 1 丨: 0 »: _ 1161 (: 011 ^ 1 ^), In order to make the data can be two, one, two = 疋 or sixteen-bit width register file (register \ Branch can buffer N blocks at the same time. In N blocks is buffered: two _ 7 two two reason The sound data is formatted by the packet formatter 238 as shown in Figure ^. In order to reduce latency, the packet frame 2 Ξ 彳 if rate is timed, so that the secondary block of the sound data has been buffered. The packet can be saved.斗 Ｍ。 # it ϋ Μ # sequence basis to generate a clock that meets the aforementioned rate. According to the embodiment of the present invention, other first-in-first-out (nfst h fifst
200425670 五、發明說明（12) 〇 u t，F I F 0 )排程也可被應用。 圖五是應用於本發明實施例之一示範性封包格式。封 包50 0包括一前言（preamble)502，緊接的是一框起始 (start-of-frame，S0F)欄504、一具有循環冗餘檢查 (cyclic redundancy check，CRC) 5 0 8之標頭 5 0 6、聲音資 料5 1 0的N個區塊及計算每一個區塊的CRC 5 1 2、一命令欄 5 1 4以及其所屬之CRC 5 1 6。根據本發明實施例，封包格式200425670 V. Description of the invention (12) 0 u t, F I F 0) schedule can also be applied. FIG. 5 is an exemplary packet format applied to one embodiment of the present invention. Packet 50 0 includes a preamble 502, followed immediately by a start-of-frame (S0F) column 504, and a header with a cyclic redundancy check (CRC) 5 0 8 5 0 6, N blocks of audio data 5 1 0 and calculate the CRC of each block 5 1 2, a command line 5 1 4 and the CRC 5 1 6 to which it belongs. According to an embodiment of the present invention, the packet format
器區塊238也可在傳送封包5 0 0到前向錯誤校正（f orward error correction，FEC)編碼器240之前，交錯封包50 0以 得到更強健的錯誤隱匿。The decoder block 238 can also interleave the packets 50 to obtain more robust error concealment before transmitting the packets 500 to the forward error correction (FEC) encoder 240.
在一較佳實施例中，一典塑的封包可以由一別立元框 起始欄、一具有8位元CRC的8位元的標頭、N個分別具有8 位元CRC的聲音資料區塊所組成。此封包亦可選擇性地包 含一具有8位元CRC之8位元命令攔。每一聲音資料區塊可 有4 0位元長，並且N個區塊的總數由標頭欄所明定，標頭 可由5位元的"長度，，欄、一命令指示位元、以及二保留位 元所組成。根據本發明之實施例，一示範性標頭攔格式如 表一所示。 如表一所示，8個標頭位元被表示成記法Header[7:0] (也就是標頭位元0-7)，其中位元7為最高有效位元（MSB) 而且最先被傳送。Header[7: 3](也就是標頭的第3 —7位In a preferred embodiment, a packet can be composed of a start box of a separate box, an 8-bit header with an 8-bit CRC, and N sound data areas each with an 8-bit CRC. Composed of blocks. The packet may optionally include an 8-bit command block with an 8-bit CRC. Each audio data block can be 40 bits long, and the total number of N blocks is specified by the header column. The header can be a 5-bit " length column, a command instruction bit, and two Composed of reserved bits. According to an embodiment of the present invention, an exemplary header block format is shown in Table 1. As shown in Table 1, the eight header bits are represented as Header [7: 0] (that is, header bits 0-7), where bit 7 is the most significant bit (MSB) and is first Send. Header [7: 3] (that is, bits 3-7 of the header
200425670 五、發明說明（13) --- 凡）指定封包5 0 0内聲音資料區塊5丨〇的數目n。 「〇 〇 〇 〇 〇 值指出沒有聲音資料區塊，而「〇〇〇〇1」表示至「丨丨丨1 / 的值指出聲音資料區塊的數目從1到3卜因此，「〇 〇 〇 〇 ^ 至「1 1 1 1 1」中只有一個會被每一個封包中的標頭指定， 用以指出在封包中所包括聲音資料區塊的數目。每一聲音 資料區塊5 1 0被定義成4 0位元加上8位元CRC。 曰200425670 V. Description of the invention (13) --- Where) The number n of the sound data block 5 丨 0 in the specified packet 500. The value of "〇〇〇〇〇〇〇 indicates that there is no audio data block, and the value of" 〇〇〇〇〇1 "indicates that the number of audio data blocks from 1 to 3, so" 00 〇 ^ to "1 1 1 1 1" will be specified by the header in each packet to indicate the number of audio data blocks included in the packet. Each audio data block 5 1 0 is defined as 40 bits plus an 8-bit CRC. Say
Header [2](也就是標頭的第2位元）指出是否封包在 8位元C R C之刖包含8位元命令棚。值「〇」表示沒有命令 欄’值「1」表示有命令攔。Header[l:0](也就是標頭的 第0 - 1位元）可以保留給以後使用。 表一（標頭格式）Header [2] (that is, the second bit of the header) indicates whether the packet contains an 8-bit command box in the 8-bit C R C frame. The value "0" indicates that there is no command. The value "1" indicates that there is a command block. Header [l: 0] (that is, bits 0-1 of the header) can be reserved for future use. Table 1 (Header Format)
位元位址 功能 有效値 參數 Hcadcr[7:3] 長度僩 00000 無聲音資料E塊 00001-111 11 1-31個聲#資料區塊 Headcr[2] 命令指示 0 無命令位元組 1 包含命令位元組 Hcadcr[l :0] 保留 NA NA 根據本發明實施例，封包5 0 0的前言5 0 2可以由_週期的 同步碼（s y n c h r ο n i z a t i ο n c 〇 d e )所構成。在較佳實施例 中，同步碼可以包括11位元習知B a r k e r序列或週期（—上 1，-1，+1，+1，+1，-1，+1，+1，_1’ +1}。換句話說， 11位元Barker序列可以重複Μ次以形成前言502。在其他實 施例中，其他適合的同步碼也可以利用，諸如但不只限定 200425670 五、發明說明（14) 是偽雜訊（pseudo noise，PN碼）（例如最大長度序列（μ 序列））、kasami序列及黃金序列（g0 ld sequence)。 此外，根據本發明實施例，當封包5 〇 〇的聲音資料區 塊5 1 0和標頭5 0 6可用不同調變程序調變時，前言50 2的最 後部分和全部框起始欄5 0 4可以使用微分編碼相位位移鍵 控（phase shift keying, PSK)來調變。假如聲音資料區 塊5 1 0和標頭5 0 6的調變程序不一樣時，在框起始欄5 〇 4已 被送出之後，調變器2 4 2 (圖四）可以改變調變程序。在 較佳實施例中，前言長度典型為.15個週期的Barker序列， 其中11個週期非微分編碼。換句話說，當Barker序列的最 後四個週期被微分編碼時，前面丨丨個週期為同樣編碼。 請再參閱四，封包5 〇 0 (圖五）被送到將資料編碼傳 送（Tx資料）的FEC編碼器240，以提供強健性對抗雜訊和 干擾。被編碼的資料接著從FEC編碼器240被送到調變器 242。調變器242根據習知的調變方法，將其輸入對應至一 離散的類比波形。根據本發明較佳實施例，調變方法可以 疋一進位制相位移位鍵控（binary phase shift keying， BPSK)或是四元相位移位鍵控（qUaternary phase shift keying, QPSK). 〇 已調變信號接著被送到濾波器244，濾波器244拒絕由 取樣程序產生的影像，並且減低由主信號頻寬外所產生的Bit address function is valid. Parameter Hcadcr [7: 3] Length: 00000 No sound data E block 00001-111 11 1-31 sound #Data block Headcr [2] Command indication 0 No command Byte 1 Contains command Byte Hcadcr [l: 0] Reserved NA NA According to the embodiment of the present invention, the preamble 50 of the packet 50 may be composed of a _period synchronization code (synchr ο nizati ο nc ode). In a preferred embodiment, the synchronization code may include an 11-bit learned Barker sequence or period (—on 1, -1, + 1, + 1, + 1, -1, + 1, + 1, _1 ′ + 1}. In other words, the 11-bit Barker sequence can be repeated M times to form the preface 502. In other embodiments, other suitable synchronization codes can also be used, such as but not limited to 200425670 V. Description of the invention (14) is false Noise (PN code) (such as a maximum length sequence (μ sequence)), a kasami sequence, and a golden sequence (g0 ld sequence). In addition, according to the embodiment of the present invention, when the packet 5 of the sound data block 5 1 0 and header 5 0 6 can be modulated with different modulation programs, the last part of the preface 50 2 and the beginning of all boxes 5 0 4 can be modulated using differential coding phase shift keying (PSK) If the modulation procedure of the sound data block 5 10 and the header 5 06 is different, the modulator 2 4 2 (Figure 4) can change the modulation after the frame start column 5 04 has been sent out. In the preferred embodiment, the preamble is typically a Barker sequence of .15 cycles, of which 11 Cycles are non-differentially encoded. In other words, when the last four cycles of the Barker sequence are differentially coded, the previous 丨 cycles are the same code. Please refer to four again, the packet 5000 (Figure 5) is sent to the data Coded transmission (Tx data) of FEC encoder 240 to provide robustness against noise and interference. The encoded data is then sent from FEC encoder 240 to modulator 242. Modulator 242 is based on conventional modulation Method, and its input corresponds to a discrete analog waveform. According to a preferred embodiment of the present invention, the modulation method can be a binary phase shift keying (BPSK) or a quaternary phase shift key. Control (qUaternary phase shift keying, QPSK). 〇The modulated signal is then sent to the filter 244, which rejects the image generated by the sampling process and reduces the
200425670 五、發明說明（15) 旁帶（sideband)。濾波器244由系統時脈254所計時，系統 時脈254典型是符元時脈256頻率的四到八倍。濾波器244 應該内插進入較慢樣本（inc〇ming si〇wei· sample)至以一 等於過取樣（over-samp led)時脈的速率的樣本中。濾波器 244可根據習知的方法所建構。在經由DAC 246轉換成一類 比信號後，濾波器244的输出接著被送到rf發射器20 6。RF 發射器2 0 6可由不同構造實現，諸如但不限定是直接轉 換、低中頻（l〇w-IF)、或是超外差（SUper一 heterodyne)。RF發射器20 6包括天線208以傳輸射頻信 號0 鎖相時脈產生器2 4 8產生系統時脈2 5 4以及合成時脈 2 58。合成時脈258被RF發射器2 0 6用來合成射頻載波。系 統時脈2 5 4為過取樣時脈，如前所述，系統時脈2 5 4為符元 時脈2 5 6頻率的四到八倍。符元時脈2 5 6係藉由一種習知方200425670 V. Description of the invention (15) Sideband. The filter 244 is clocked by the system clock 254, which is typically four to eight times the frequency of the symbol clock 256. Filter 244 should be interpolated into slower samples (incoming sample) to samples at a rate equal to the over-sampled clock. The filter 244 may be constructed according to a conventional method. After being converted into an analog signal by the DAC 246, the output of the filter 244 is then sent to the rf transmitter 206. The RF transmitter 206 can be implemented by different structures, such as but not limited to direct conversion, low intermediate frequency (10w-IF), or super heterodyne. The RF transmitter 20 6 includes an antenna 208 to transmit a radio frequency signal. 0 The phase-locked clock generator 2 4 8 generates a system clock 2 5 4 and a composite clock 2 58. The synthesized clock 258 is used by the RF transmitter 206 to synthesize a radio frequency carrier. The system clock 2 5 4 is the oversampling clock. As mentioned earlier, the system clock 2 5 4 is four to eight times the frequency of the symbol clock 2 5 6. Rune Clock 2 5 6 is based on a known method
法的除法器電路（dividercircuit)由時脈產生器250所產 生。時脈產生器250也提供一外部MCLK0信號2 60幫助介面 它的聲音資料輸入，如I2S。MCLK〇信號26〇經由除法器電 路從系統時脈2 5 4取得。根據其他實施例，分離晶體參考 (separate crystal reference)可被 RF發射器 20 6及數位 數據機發射器所204使用，以取代鎖相時脈產生器248。此 外’非揮發性記憶體2 8 1經由記憶體介面2 9 9可用來提供一 初始配置到數位數據機接收器2 0 4。A divider circuit is generated by the clock generator 250. The clock generator 250 also provides an external MCLK0 signal 2 60 to help interface its audio data input, such as I2S. The MCLK0 signal 26O is obtained from the system clock 2 54 via a divider circuit. According to other embodiments, a separate crystal reference may be used by the RF transmitter 20 6 and the digital modem transmitter 204 instead of the phase-locked clock generator 248. In addition, the non-volatile memory 2 8 1 can be used to provide an initial configuration to the digital modem receiver 2 0 4 via the memory interface 2 9 9.
第21頁 200425670 五、發明說明（16) 圖六係為根據本發明之實施例之時脈產生器2 5 〇的方 塊圖。MCLK0信號260從系統時脈254取出，並經由 MCLK一SEL 602選擇。假如MCLK0一SEL 6 0 2 =卜則除以二方 塊60 4的輸出會被當作1101^0信號260。假如^1(^1[(^8£1602 =0，則系統時脈254會被當作MCLK0信號2 6 0。符元時脈256 由系統時脈254取出，並被08-8£1^ 6 0 6選擇。假如〇3_8£1^ 6 0 6 = ：1，則除以八方塊6 0 8的輸出被當作符元時脈2 5 6。假 如OS_SEL 6 0 6 = 0，則除以四方塊6 1 0的輸出被當作符元時 脈256。所有除法電路都是正緣觸發（posi tive-edge triggered)° 請再參閱圖四，數位數據機發射器2 0 4的控制介面部 份25 2實現RF介面262、外在介面264、及邏輯運算（内部 控制/設定）2 6 6。RF介面262用以控制RF發射器2 0 6，如藉 由設定通道頻率及RF發射器206的傳輸功率。為了在如但 不限定是I S Μ頻帶的共用頻帶干擾中強健接收，R F發射器 20 6會使用RF介面262以在下列特定的中心頻率的範圍傳 輸：5.165 Giga Hertz(GHz)、 5.19GHz、 5.21GHz、 5.23GHz、 5.25GHz、 5.27GHz、 5.29GHz、 5.31GHz、 5. 335GHz、5. 735GHz、5· 755GHz、5. 775GHz、5· 795GHz、 5.815GHz' 2.427GHz、 2.4245GHz或 2.425GHz、 2.457GHz、 2.4495GHz或 2.450GHz、及 2.47275GHz或 2.473GHz〇Page 21 200425670 V. Description of the invention (16) Fig. 6 is a block diagram of a clock generator 2 50 according to an embodiment of the present invention. The MCLK0 signal 260 is taken from the system clock 254 and selected via the MCLK_SEL 602. If MCLK0-SEL 6 0 2 = Bu then divide by two The output of block 60 4 will be treated as a 1101 ^ 0 signal 260. If ^ 1 (^ 1 [(^ 8 £ 1602 = 0), the system clock 254 will be treated as the MCLK0 signal 2 6 0. The symbol clock 256 is taken from the system clock 254 and will be 08-8 £ 1 ^ 6 0 6. Choice. If 〇3_8 £ 1 ^ 6 0 6 =: 1, the output divided by eight squares 6 0 8 is treated as symbol clock 2 5 6. If OS_SEL 6 0 6 = 0, divide by The output of the four square 6 1 0 is regarded as the symbol clock 256. All division circuits are positive-edge triggered ° Please refer to Figure 4 again, the control interface of the digital modem transmitter 2 0 4 25 2 Realize RF interface 262, external interface 264, and logic operation (internal control / setting) 2 6 6. RF interface 262 is used to control RF transmitter 2 0 6, such as by setting the channel frequency and RF transmitter 206. Transmission power. For robust reception in common band interference such as, but not limited to, the IS M band, the RF transmitter 206 will use the RF interface 262 to transmit in the following specific center frequency ranges: 5.165 Giga Hertz (GHz), 5.19 GHz, 5.21GHz, 5.23GHz, 5.25GHz, 5.27GHz, 5.29GHz, 5.31GHz, 5.335GHz, 5.735GHz, 5.755GHz, 5.775GHz, 5.795GHz, 5.815 GHz '2.427GHz, 2.4245GHz or 2.425GHz, 2.457GHz, 2.4495GHz or 2.450GHz, and 2.47275GHz or 2.473GHz.
第22頁 200425670 五、發明說明（17) 根據本發明之實施例，數位數據機發射器2 0 4的典型 參數如表二所示。信號速率會根據聲音取樣率而有不同， 根據本發明之實施例，不是4 4. 1 k i 1 ο H e r t z ( k Η z )就是 4 8kHz 〇 表二（發射器參數的整理） 參數 聲罾取樣率 値 系統時脈率 (f*y〇 44.1kHz 22.5792MHz 48kHz 24.5760MHz 聲_音資料率 44.1kHz 1.764Mbps 48kHz 1.92 Mbps 符元時脈率 ΝΑ fty，/4 或 fsy*/8 I2S BCK 率 44.1kHz 2.8224 MHz 48kHz 3.072 MHz I2S LRCK m 44.1kHz 44.1iHz 48kHz 48kHz I2S MCLK0 率 44.1kHz 11.2896MHz(MCLKO^SEL=0) 22.5792MHz(MCLKO_SEL=l) 48kHz 12.2880MHz(MCLKO SEL=0) 24.5760MHz(MCLKO SEL=1) 根據較佳實施例，聲音資料率等於2 0位元*聲音取樣 率。對於44.1kHz及48kHz的聲音取樣率而言，聲音資料率 分別為 1.764Mbps(mega bitsper second)及 1.92Page 22 200425670 V. Description of the invention (17) According to the embodiment of the present invention, typical parameters of the digital modem transmitter 204 are shown in Table 2. The signal rate will vary according to the sound sampling rate. According to the embodiment of the present invention, it is either 4 4.1 ki 1 ο Hertz (k Η z) is 4 8kHz 〇 Table 2 (Arrangement of transmitter parameters) Parameter acoustic sampling Rate 値 System clock rate (f * y〇44.1kHz 22.5792MHz 48kHz 24.5760MHz Acoustic data rate 44.1kHz 1.764Mbps 48kHz 1.92 Mbps Symbol clock rate NA fty, / 4 or fsy * / 8 I2S BCK rate 44.1kHz 2.8224 MHz 48kHz 3.072 MHz I2S LRCK m 44.1kHz 44.1iHz 48kHz 48kHz I2S MCLK0 rate 44.1kHz 11.2896MHz (MCLKO ^ SEL = 0) 22.5792MHz (MCLKO_SEL = l) 48kHz 12.2880MHz (MCLKO SEL = 0) 24.5760MHz (MCLKO SEL = 1) According to a preferred embodiment, the sound data rate is equal to 20 bits * sound sampling rate. For the sound sampling rates of 44.1kHz and 48kHz, the sound data rate is 1.764Mbps (mega bitsper second) and 1.92, respectively.
Mbps。I2S BCK率包括在12S封包格式中的額外附加 (〇 v e r h e a d)。在I 2 S封包中每通道有3 2位元。因此I 2 S BCK率等於64位元*聲音取樣率，對於44. 1 kHz及48kHz的聲 音取樣率而言，聲音資料率分別為2. 8224MHz及3. 072 MHz。BCK也為系統時脈率（f sys)的八分之一。Mbps. The I2S BCK rate includes an additional addition in the 12S packet format (0 v e r h e a d). There are 32 bits per channel in the I 2 S packet. Therefore, the I 2 S BCK rate is equal to 64 bits * sound sampling rate. For the sound sampling rates of 44.1 kHz and 48 kHz, the sound data rates are 2. 8224 MHz and 3. 072 MHz, respectively. BCK is also one-eighth of the system clock rate (f sys).
第23頁 200425670 五、發明說明（18) 如圖七所示，為保護磬咅σ ^ 2a 曼卓日口口質在干擾、雜訊、且/或 哀弱（fadmg)中達到強健性接收，本發明實施例在封包格 式盗方塊238中實現聲音資料區塊交錯器7〇卜有_聲音 資料區塊被送到緩衝器702。資料從緩衝器被擷取的順序 由交錯定序器（lnterleaving sequencer)7〇4所決定。交 錯定序器704重新排定N個聲音資料區塊在從緩衝器7〇2裸 取的順序。接著已交錯的區塊被格式化成具有如圖五所示 的格式的封包500»封包50 0接著被送到調變器24 2傳送出 去。 父錯序列可根據習知的方法完成，諸如但不限定那些 用以區隔與迴旋的交錯器。本發明實施例交錯資料區塊大 於1位元。這樣提供一個好處：鑑於傳統交錯器在傳送之 前編碼並交錯位元，對資料區塊編碼是不必要的。然而除 了交錯資料區塊之外，個別位元編碼可以在本發明某些實 施例中應用。 圖八所示為可以用於本發明實施例之示範性數位數據 機接收器2 2 6。RF接收器2 24的輸入可以包括一天線切換器 270，其根據一接收信號強度指示（received signal strength indicator, RSSI)值來選擇天線 220及 222其中 之一。決定哪一個天線被選擇的決定邏輯在自動增益控制 (automatic gain control, AGC)/天線選擇區塊 276中實 現。天線切換器2 70的輸出接著由RF接收器224處理。Page 23 200425670 V. Description of the invention (18) As shown in Figure 7, in order to protect 磬 咅 σ ^ 2a, the quality of the mandroglia mouth has reached robust reception in interference, noise, and / or fadmg, In the embodiment of the present invention, the audio data block interleaver 70 is implemented in the packet format stealing block 238. The audio data block is sent to the buffer 702. The order in which data is retrieved from the buffer is determined by the interleaving sequencer 704. The cross-sequencer 704 rearranges the order of N audio data blocks from the buffer 702. The interleaved block is then formatted into a packet 500 »packet 50 0 having the format shown in Figure 5 and then sent to the modulator 24 2 for transmission. The paternity sequence can be accomplished according to conventional methods, such as, but not limited to, interleavers used to separate and convolute. In the embodiment of the present invention, the interleaved data block is larger than 1 bit. This provides an advantage: since the traditional interleaver encodes and interleaves bits before transmission, encoding the data block is unnecessary. However, in addition to interleaved data blocks, individual bit encodings can be applied in some embodiments of the invention. FIG. 8 shows an exemplary digital modem receiver 2 2 6 that can be used in embodiments of the present invention. The input of the RF receiver 2 24 may include an antenna switcher 270, which selects one of the antennas 220 and 222 according to a received signal strength indicator (RSSI) value. The decision logic to determine which antenna is selected is implemented in automatic gain control (AGC) / antenna selection block 276. The output of the antenna switch 2 70 is then processed by the RF receiver 224.
第24頁 200425670 五、發明說明（19) RF接收器224的設定經RF介面280被控制介面部份278 所決定，RF介面2 80可由習知方法所實現。RF接收器224的 增益由AGC/天線選擇區塊276所設定，AGC/天線選擇區塊 2 7 6根據RSSI值來決定增益設定。RF接收器22 4的輸出為基 頻接收信號的同相（I )成分（i nphase)及正交（Q)成分 (quadrature)。Page 24 200425670 V. Description of the invention (19) The setting of the RF receiver 224 is determined by the control interface part 278 of the RF interface 280, and the RF interface 2 80 can be realized by a conventional method. The gain of the RF receiver 224 is set by the AGC / antenna selection block 276, and the AGC / antenna selection block 2 7 6 determines the gain setting according to the RSSI value. The output of the RF receiver 224 is the in-phase (I nphase) and quadrature (Q) components (quadrature) of the received signal at the fundamental frequency.
在數位數據機接收器226中，兩個ADC 282、28 4可分 別用以數位化所接收基頻信號I及Q。ADC的取樣由時脈恢 復區塊2 8 6所控制。已數位化的I與Q信號被送到解調器 2 8 8，以還原在數位格式中的資料。解調器2 8 8利用習知的 方法將數位的I與Q資料還原成被傳輸的符元。如上述討 論，根據本發明的實施例，因為圖五中封包5 0 0的前言5 〇 2 及聲音資料區塊5 1 0可以利用不同的調變程序調變，解調 器288能夠支援多種調變程序，以對在封包5 0 0中的框起始 攔50 4之前及之後不同的調變解調。 在一較佳實施例中，如圖九所示之非連貫（n 〇 n 一 coherent)解調器可用來當作解調器288。然而，任何適用 之解調器都可應用於本發明之實施例十。圖九所示之非連 貫解調β包括兩個微分摘測^§ 9 0 2、9 0 4。兩個貞測器 9 0 2、9 0 4的暫存器由符元時脈294計時，每一偵測器將接 收基頻信號的通道乘上已被時脈294之週期所延遲的信號In the digital modem receiver 226, the two ADCs 282, 284 can be used to digitize the received baseband signals I and Q, respectively. The ADC sampling is controlled by the clock recovery block 268. The digitized I and Q signals are sent to a demodulator 2 8 8 to restore the data in the digital format. The demodulator 2 8 8 restores the digital I and Q data to the transmitted symbols using a conventional method. As discussed above, according to the embodiment of the present invention, because the preamble 5 0 2 of the packet 5 0 and the sound data block 5 1 0 in FIG. 5 can be modulated using different modulation programs, the demodulator 288 can support a variety of modulations. Change the program to demodulate the different modulations before and after the start of the box in the packet 500. In a preferred embodiment, a non-coherent demodulator as shown in FIG. 9 can be used as the demodulator 288. However, any applicable demodulator can be applied to the tenth embodiment of the present invention. The non-coherent demodulation β shown in Fig. 9 includes two differential extraction tests ^ § 9 0 2 and 9 0 4. The registers of the two testers 9 0 2 and 9 0 4 are clocked by the symbol clock 294. Each detector multiplies the channel receiving the fundamental frequency signal by a signal that has been delayed by the period of the clock 294.
200425670 五、發明說明（20) 版本（ve r s i on )，這兩個偵測器的輸出被一加法器9 0 6加總 以形成一軟決定值（soft decision value)。軟決定值被 送到截剪器（si icer ) 908，進而可以確定一符元決定。截 剪器90 8接收軟決定值，並在其輸出端產生一解調符元。 根據本發明之實施例，圖九所示之非連貫解調器可以 解調微分編碼的BPSK信號。對BPSK而言，被解調符元不是 + 1(以「0」表示）就是-1(以「1」表示）。截剪器908 可以簡單地運用軟決定值的符元來做上述的對應。 % 凊再參閱圖八，已解調的符元從解調器2 8 8被送到F E C 解碼器290，以還原原始傳送資料。FEC解碼器29〇使用符 元時脈294來產生解碼已解調資料所需的時脈。FEC解碼器 2 9 0可用習知方法來實現。 已解碼資料接著被送到封包解格式化器2 9 8。封包解 格式化器2 9 8接收已解碼符元，並且將圖五的封包5 〇 〇解格 式化成其標頭、資料、命令（如果有）。在標頭50 6中的 長度攔資訊被用在封包5 0 0的解格式化。封包解格式化器 298使用框開始（frame start)信號283及符元時脈294，以· 將封包50 0的標頭5 0 6及CRC 5 08剝出（strip out)。框開始 4吕號2 8 3由框同步區塊4 3 8根據圖五所示之框時序開始（t卜e start of frame timing)所發佈。框同步區塊438利用從 時脈恢復區塊2 8 6的控制信號，並用框起始欄5 〇 4來判定框200425670 V. Invention description (20) version (ve r s i on), the outputs of the two detectors are summed by an adder 906 to form a soft decision value. The soft decision value is sent to the si icer 908, which can determine a symbol decision. The clipper 90 8 receives the soft decision value and generates a demodulation symbol at its output. According to an embodiment of the present invention, the non-coherent demodulator shown in Fig. 9 can demodulate a differentially coded BPSK signal. For BPSK, the demodulated symbol is either +1 (represented by "0") or -1 (represented by "1"). The clipper 908 can simply use soft-determined symbols to make the above correspondence. % 凊 Referring again to Figure 8, the demodulated symbols are sent from the demodulator 2 88 to the F E C decoder 290 to restore the original transmission data. The FEC decoder 29 uses the symbol clock 294 to generate the clock required to decode the demodulated data. The FEC decoder 290 can be implemented in a conventional manner. The decoded data is then sent to the packet formatter 2 98. The packet de-formatter 2 98 receives the decoded symbols and formats the packet 500-decoding of Figure 5 into its header, data, and command (if any). The length block information in the header 506 is used to deformat the packet 500. The packet deformatter 298 uses the frame start signal 283 and the symbol clock 294 to strip the header 50 0 6 and CRC 5 08 of the packet 50 0 (strip out). Frame start 4 Lu No. 2 8 3 is released by frame synchronization block 4 3 8 according to the frame start (frame start) shown in FIG. 5. The frame synchronization block 438 uses the control signal of the block 2 8 6 to recover from the clock, and uses the frame start column 504 to determine the frame.
第26頁 200425670 五、發明說明（21) 的開始。在一些實施例中，被接收的資料可在一 FIF〇e憶 體（圖上未示）來緩衝。根據本發明之實施例，長度欄可 以被刪除，使得當標頭發生錯誤時，封包解格式化器298 仍然可以將封包解格式化。 17 C R C 5 1 2及聲音資料區塊51 0被送到内插部份2 9 5。已 接收的聲音資料區塊5 1 0可在一 F I F0記憶體（圖上未示） 來緩衝。假如C R C 5 1 2未通過，内插部份2 9 5執行運算以隱 匿在對應聲音資料的錯誤，以致於品質不會明顯降低。 内插部分2 9 5接者將聲音資料傳送到聲音介面區塊2g6 來處理。聲音介面區塊2 9 6的輸出可以是例如由LRCK、 BCK、及資料信號所組成的I2S數位聲音標準格式。 控制介面部份2 78實現了 RF介面2 8 0、外部介面2 8 5、 及内部控制/設定3 0 1。R F介面2 8 0用來控制R F接收器2 2 4， 諸如藉由設定RF接收器224的通道頻率及發射功率。此 外，控制介面2 7 8經由記憶體介面3 0 5介面連結非揮發架構 的記憶體303，以架構數位數據機接收器226。Page 26 200425670 V. The beginning of the description of the invention (21). In some embodiments, the received data may be buffered in a FIFoe memory (not shown). According to an embodiment of the present invention, the length field can be deleted, so that when an error occurs in the header, the packet deformatter 298 can still deformat the packet. 17 C R C 5 1 2 and audio data block 5 10 are sent to the interpolation part 2 9 5. The received audio data block 5 1 0 can be buffered in a F I F0 memory (not shown). If C R C 5 1 2 fails, the interpolation part 2 9 5 performs an operation to hide the errors in the corresponding sound data, so that the quality will not be significantly reduced. The interpolation part 2 9 5 sends the sound data to the sound interface block 2g6 for processing. The output of the audio interface block 296 can be, for example, an I2S digital audio standard format composed of LRCK, BCK, and data signals. The control interface part 2 78 implements the RF interface 280, the external interface 285, and the internal control / setting 301. The R F interface 2 8 0 is used to control the R F receiver 2 2 4, such as by setting the channel frequency and transmit power of the RF receiver 224. In addition, the control interface 278 is connected to a non-volatile memory 303 through a memory interface 305 to construct a digital modem receiver 226.
鎖相時脈產生器2 8 7產生系統時脈2 9 2及合成時脈 289，合成時脈28 9由RF接收器2 24所使用，以合成RF載 波。系統時脈2 9 2為一過取樣時脈，並且頻率可以為符元 時脈2 9 4的四到八倍。藉由習知方法的除法器電路，符元 時脈2 9 4由時脈產生器2 9 1所產生。時脈產生器2 9 1也由外The phase-locked clock generator 2 8 7 generates a system clock 2 9 2 and a composite clock 289, and a composite clock 28 9 is used by the RF receiver 2 24 to synthesize an RF carrier wave. The system clock 2 9 2 is an oversampled clock, and the frequency can be four to eight times the symbol clock 2 9 4. With the divider circuit of the conventional method, the symbol clock 2 9 4 is generated by the clock generator 2 9 1. Clock generator 2 9 1
第27頁 200425670 五、發明說明（22) 部提供一 MCLKOj言號293，使得與其聲音資料輸出的溝通更 為容易。MCLKCH言號2 93是經由習知方法的除法器電路從恢 復時脈2 9 7所取出。 根據本發明之實施例，數位數據機接收器2 2 6的典型 參數如表三所示。信號速率會根據聲音取樣率而有不同， 根據本發明之實施例，不是4 4. 1 k i 1 ο H e r t z (k Η z )就是 48kHz。 表三（接收器參雖ii) 參數 聲音取樣率 値 系統時脈率 44.1kHz 225792MHz 48kHz 245760MHz 聲音g料率 44.1kHz 1.764Mtps 48kHz 1.92 Mbps 符元時脈率 ΝΑ U4 或 U8 I2S BCK 率 44.1kHz 2.8224 MHz 48kHz 3.072 MHz I2S LRCK 率 4+.lkHz AUlUz 48kHz 48kHz I2S MCLK0 率 44-.lkHz 112896MHz(MCLKO_SEL=i)) 225792MHz(MCLKO_SEL=l) 48kHz 12 挪 0MHz(MCLKQ_SEL=O) 245760M Hz(MCLK0_ SEL =1)Page 27 200425670 V. The description of the invention (22) provides a MCLKOj signal 293, which makes it easier to communicate with its audio data output. The MCLKCH signal 2 93 is taken from the recovery clock 2 9 7 via a divider circuit of a conventional method. Table 3 shows typical parameters of the digital modem receiver 2 2 6 according to the embodiment of the present invention. The signal rate will vary according to the sound sampling rate. According to an embodiment of the present invention, either 44.1 k i 1 ο H r t z (k Η z) is 48 kHz. Table 3 (Receiver parameters ii) Parameter Sound sampling rate 値 System clock rate 44.1kHz 225792MHz 48kHz 245760MHz Sound rate 44.1kHz 1.764Mtps 48kHz 1.92 Mbps Symbol clock rate ΝΑ U4 or U8 I2S BCK rate 44.1kHz 2.8224 MHz 48kHz 3.072 MHz I2S LRCK rate 4 + .lkHz AUlUz 48kHz 48kHz I2S MCLK0 rate 44-.lkHz 112896MHz (MCLKO_SEL = i)) 225792MHz (MCLKO_SEL = l) 48kHz 12 Move 0MHz (MCLKQ_SEL = O) 245760M Hz (MCLK0_ SEL = 1)
如上所討論，封包解格式化器2 9 8接收已解調符元， 並且將封包5 0 0解格式化成其標頭、資料、及命令（如果 有的話）。封包解格式化器2 98接收已解調符元，並且擷 取聲音資料區塊5 1 0及所對應的CRC 5 1 2。當所對應聲音資As discussed above, the packet deformatter 298 receives the demodulated symbols and deformats the packet 50 into its header, data, and command (if any). The packet deformatter 2 98 receives the demodulated symbols and extracts the audio data block 5 10 and the corresponding CRC 5 1 2.当 corresponding sound information
illill
第28頁 200425670 五、發明說明（23) 料區塊為錯誤時，C R C 5 1 2為「1」；當所對應聲音資料區 塊5 1 0無錯誤時，CRC 5 1 2為「〇」。 根據本發明之實施例，内插部分295根據CRC 5 1 2執行 運以隱匿在相對應聲音資料中的錯誤，使得品質並不 會明顯降低。交錯聲音資料區塊5 1 〇及其相關之crc 5 1 2被 傳送到内插部分295,藉此聲音資料區塊510及CRC 5 12以 44· 1kHz或是48kHz的聲音率傳輸。 一 根據本發明之實施例’ CRC 5 1 2及聲音資料區塊5 1 〇應· 該要如圖十所示的示範性波形一樣校準。為了最小化處理 中的潛伏’封包解格式化器2 9 8可被計時的快些，並且c r c 5 1 2可以短些。然而，相位的關係應該在聲音資料區塊交 界被保持。 、 在封包解格式化器298可處理包含在那些封包5〇〇的聲 音資料區塊5 1 0之前，在一個或多個封包5 〇 〇遣失 (dr0pped)的情況下，所對應的cRC 5丨2不能被計算。·因 此’内插部份29 5不请楚在遺失封包5 0 0中發生的聲音資料 區塊錯誤。為了處理這樣的例子，根據本發明之實^例，· 封包解袼式化器298偵測一封包遺失，並且傳送對應於遺 失聲音資料區塊5 1 0之CRC 5 1 2脈衝到内插部份2 9 5。内插 部^ 2 9 5將隱匿由遺失聲音資料區塊5丨〇所引起的錯誤。需 庄忍封包50(3會因標頭50 6的錯誤而遺失。、Page 28 200425670 V. Description of the invention (23) When the data block is wrong, C R C 5 1 2 is "1"; when the corresponding audio data block 5 1 0 is no error, CRC 5 12 is "0". According to the embodiment of the present invention, the interpolation section 295 performs the operation according to the CRC 5 12 to hide errors in the corresponding audio data, so that the quality is not significantly reduced. The interleaved audio data block 5 10 and its associated crc 5 12 are transmitted to the interpolation section 295, whereby the audio data block 510 and CRC 51 2 are transmitted at a sound rate of 44.1 kHz or 48 kHz. A CRC 5 1 2 and audio data block 5 1 0 according to an embodiment of the present invention should be calibrated like the exemplary waveform shown in FIG. In order to minimize the latency in the processing, the packet formatter 2 98 can be timed faster, and c r c 5 1 2 can be shorter. However, the phase relationship should be maintained at the boundary of the audio data block. Before the packet deformatter 298 can process the audio data block 5 1 0 included in those packets 5 0, in the case that one or more packets 5 0 are lost (dr0pped), the corresponding cRC 5丨 2 cannot be calculated. · Therefore, the interpolated part 29 5 does not invite the audio data block error that occurred in the lost packet 5 0 0. In order to deal with such an example, according to an example of the present invention, the packet deinterleaver 298 detects a packet loss and transmits a CRC 5 1 2 pulse corresponding to the lost audio data block 5 1 0 to the interpolation unit. Serving 2 9 5. The interpolation unit ^ 2 9 5 will hide errors caused by the missing audio data block 5 丨 〇. Need Zhuang Ren packet 50 (3 will be lost due to the error of the header 50 6.,
200425670200425670
五、發明說明（24) 處理之後’内插部份2 9 5將聲音資料經由左通道 (DataL)及右通道（DataR)送到聲音介面區塊2 96。聲音介 面區塊2 96將聲音資料轉換成適當的數位格式。如上所討 論，根據一較佳實施例，數位格式係為！ 2S。聲音介面區 塊2 96所用的時脈是％1{及1^(：1{，並由時脈產生5|2()1利田 恢復時脈m經由習知方法之除法器電路所產產生生'當= 信號（Rdy)被啟動，内插部份29 5送資料到聲音介面區塊 2 96供處理。符元時脈294被用來在聲音介面區塊29 6與内 插部份2 95間提供同步介面。聲音介面區塊29 6應該重新計 時輸入資料，以致於被傳送的聲音資料會跟BCK同步，並 且左/右通道資料被校準到LRCK。速率轉換所需要的BCK與 LRCK兩者都由在時脈產生器291的符元時脈294所產出。/因 為信號BCK、Data、LRCK及MCLK0被使用I2S格式的典型聲 音解碼器中利用，所以在圖四與圖八中顯示信號BCK、V. Description of the invention (24) After processing, the interpolation section 2 9 5 sends the sound data to the sound interface block 2 96 through the left channel (DataL) and the right channel (DataR). The sound interface block 2 96 converts the sound data into an appropriate digital format. As discussed above, according to a preferred embodiment, the digital format is! 2S. The clock used in the sound interface block 2 96 is% 1 {and 1 ^ (: 1 {, and is generated by the clock 5 | 2 () 1 Litian restores the clock m, which is generated by the divider circuit of the conventional method. 'When = signal (Rdy) is activated, the interpolation section 29 5 sends data to the sound interface block 2 96 for processing. The symbol clock 294 is used in the sound interface block 29 6 and the interpolation section 2 95 Provide a synchronous interface. The audio interface block 29 6 should re-time the input data so that the transmitted audio data will be synchronized with the BCK, and the left / right channel data will be calibrated to LRCK. Both BCK and LRCK required for rate conversion All are produced by the symbol clock 294 in the clock generator 291. / Because the signals BCK, Data, LRCK, and MCLK0 are used in a typical sound decoder using the I2S format, the signals are shown in Figures 4 and 8 BCK,
Data、LRCK及MCLK0。其他格式的信號可要求其他的輸入/ 輸出信號。 ^ 如上所述，根據本發明之實施例，聲音資料區塊交錯 器700(圖七）在封包格式化器238(圖四）中被實現，用讎 以將聲音資料區塊510的錯誤在整個封包5〇〇展開。因此根 據本發明之實施例，在傳送已還原信號聲音資料區塊51〇 到内插部份29 5之前，已還原聲音資料區塊51〇應該被還原 成原始順序。聲音資料區塊解交錯器丨丨〇 〇在封包格式化器Data, LRCK and MCLK0. Signals of other formats may require other input / output signals. ^ As mentioned above, according to an embodiment of the present invention, the audio data block interleaver 700 (FIG. 7) is implemented in the packet formatter 238 (FIG. 4), and the error of the audio data block 510 is used throughout. The packet was opened at 500. Therefore, according to the embodiment of the present invention, the restored sound data block 51 should be restored to the original order before transmitting the restored signal sound data block 51 to the interpolation section 29 5. Audio data block deinterleaver 丨 丨 〇 〇 In the packet formatter
第30頁 200425670 五、發明說明（25) 一 2 9 8中被實現，如圖十一所示。N個已交錯的聲音資料區塊 5 If皮送到緩衝器11〇2。資料從緩衝器擷取的順序由解交 錯定序器11 0 4所決定。解交錯定序器丨丨〇 4回復在數位無線 發射器202之交錯定序器7〇4執行的順序。Page 30 200425670 V. Description of the invention (25)-2 98 is realized, as shown in Figure 11. The N interleaved audio data blocks 5 If are sent to the buffer 1102. The order in which data is retrieved from the buffer is determined by the descrambling error sequencer 1104. The de-interlacing sequencer 丨 丨 4 reverts to the sequence performed by the interleaving sequencer 704 of the digital wireless transmitter 202.
根據本發明之實施例，聲音資料區塊5丨〇可包括多個 聲音資料通道。在這樣的情況下，聲音資料區塊解交錯器 1 1 0 0的實施例可以包括有如圖十一所示之一解析器1 1 〇 4。 解析器11 0 4將聲音資料區塊5 1 0解析到對應至N個聲音通道 的資料。接著，多通道的輸出被送到内插部份2 9 5 (圖 八）以進一步處理。根據其他的實施例，一聲音資料區塊 5 1 0可對應到從多個通道其中之一來的資料。換句話說， 從每一聲音通道來的資料會有其專屬的CRC 512。在較佳 實施例中，每一聲音資料區塊由兩個通道所組成：Audi 〇According to an embodiment of the present invention, the audio data block 5 may include multiple audio data channels. In such a case, the embodiment of the audio data block deinterleaver 110 may include a parser 1 104 as shown in FIG. The parser 11 0 4 parses the sound data block 5 1 0 into data corresponding to N sound channels. The multi-channel output is then sent to the interpolation section 295 (Figure 8) for further processing. According to other embodiments, a sound data block 510 may correspond to data from one of a plurality of channels. In other words, the data from each sound channel will have its own CRC 512. In the preferred embodiment, each audio data block is composed of two channels: Audi 〇
Data (Right)及 Audio Data (Left)，每一個都是 2 〇位 元。Data (Right) and Audio Data (Left), each of which is 20 bits.
如圖十二所示，根據本發明之實施例，内插部份2 9 5 (圖八）包括一普通内插區塊1202，其可實現任何可用的 插值方法’諸如線性内插法（linear interpolation^)、二 P皆内插法(second-order interpolation)、三 p皆内杨法 (third - order i nt er po 1 at i on)或其他°跟普通内插區塊 1 202平行的是保留區塊1 204，其保留最新的「乾淨」沒有 錯誤的聲音資料區塊5 1 0 (或是至少部分從普通内插區塊As shown in FIG. 12, according to an embodiment of the present invention, the interpolation section 295 (FIG. 8) includes a general interpolation block 1202, which can implement any available interpolation method such as linear interpolation (linear interpolation ^), second-order interpolation, third-order i nt er po 1 at i on, or other ° Parallel to ordinary interpolation block 1 202 is Reserved block 1 204, which retains the latest "clean" error-free audio data block 5 1 0 (or at least partially from ordinary interpolation blocks
200425670 五、發明說明（26) 1 20 2所接收之已處理的聲音資料區塊510)。根據本發明 之其他實施例，保留區塊1 2 0 4的輸入可以不跟普通内插器 1 2 0 2的輸入平行。舉例來說，根據一實施例，保留區塊 1 2 0 4可以位在普通内插器1 2 〇 2之内。因此在聲音資料進入 保留區塊1 2 0 4之前，聲音資料可以進入普通内插器丨2 〇 2。 從普通内插區塊1 202及保留區塊1 204來的輸出被送到 選擇器方塊1 2 0 6，其根據CRC 5 12輸入的狀態，選擇從普 通内插區塊1 202的輸出或是保留區塊1 204的輸出。根據本 發明之實施例，一般而言，對於會明顯降低普通内插區塊| 1 2 0 2結果的錯誤組態（p a 11 e r η )，保留區塊1 2 〇 4的輸出會 被選出。在更適合的錯誤條件下，普通内插區塊丨2 〇 2的輸 出會被選出。此外，選擇器方塊12〇 6可以致動保留區塊 1 2 04 ’以及可用在普通内插區塊12〇 2的額外保留區塊 1 2 04。致能控制如圖十二虛線所示，從選擇器區塊12〇6到 普通内插區塊1 2 〇 2及保留方塊1 2 0 4。 圖十三係為一階内插區塊1 3 0 0的實施例，其可以應用 來取代圖十二的普通内插區塊1202。為了清楚說明，對應蠢 到圖十二的部分之一階内插方塊1 3 〇 〇中不同部份由虛線所響 圍住。因此一階内插區塊丨3 〇 〇包括左聲音資料與右聲音資 料線性内插器部份1 3 0 2、1 3 0 4，以及左聲音資料與右聲音 資料保留暫存器i 3 〇 6、i 3 〇 8。一階内插區塊丨3 〇 〇更包括一 選擇器部伤1310，其包括一組合邏輯（combinational200425670 V. Description of Invention (26) 1 20 2 The processed sound data block 510 received). According to other embodiments of the present invention, the input of the reserved block 1 2 0 4 may not be parallel to the input of the ordinary interpolator 1 2 0 2. For example, according to an embodiment, the reserved block 1240 can be located within the ordinary interpolator 1220. Therefore, before the sound data enters the reserved block 1 2 0 4, the sound data can enter the ordinary interpolator 丨 2 02. The output from the normal interpolation block 1 202 and the reserved block 1 204 is sent to the selector block 1 2 0 6. According to the state of the CRC 5 12 input, the output from the normal interpolation block 1 202 or The output of block 1 204 is reserved. According to the embodiment of the present invention, in general, for the wrong configuration (p a 11 e r η) that will significantly reduce the result of the ordinary interpolation block | 1 2 0 2, the output of the reserved block 1 2 04 will be selected. Under more suitable error conditions, the output of the ordinary interpolation block 丨 2 02 will be selected. In addition, the selector block 1206 can actuate the reserved block 1 2 04 ′ and an additional reserved block 1 2 04 that can be used in the normal interpolation block 12 02. The enabling control is shown by the dotted line in FIG. 12, from the selector block 1206 to the ordinary interpolation block 1220 and the reserved block 1204. Fig. 13 is an embodiment of a first-order interpolation block 1300, which can be applied to replace the ordinary interpolation block 1202 of Fig. 12. For the sake of clarity, the different parts of the first-order interpolation block 1300 corresponding to the part from Fig. 12 are surrounded by dotted lines. Therefore, the first-order interpolation block 丨 3 〇 includes the left and right sound data linear interpolator parts 1 3 0 2, 1 3 0 4 and the left and right sound data retention registers i 3 〇 6. i 3 〇8. The first-order interpolation block includes a selector 1310, which includes a combination of logic (combinational
第32頁 200425670 五、發明說明（27) logic，C/L)方塊1312、左聲音資料及右聲音資料多工器 1314、 1316。 根據本發明之實施例，一階内插區塊1 3 0 0的選擇器部 份1310從封包解格式化器298接收CRC 51 2當成輸入，用以 決定要選擇兩個聲音樣本的線性插值，還是選擇保留最新 好的聲音樣本。如上所討論，當所對應聲音資料區塊5 i 〇 為錯誤時，CRC 512為「1」。當所對應聲音資料區塊510 為零錯誤時，CRC 512為「〇」。 根據本發明之實施例，一階内插方塊丨3 〇 〇的所有暫存 器是正緣觸發。這些暫存器是利用44· 1 kHz或是48kHz的倍 數的時脈所計時。特定速度應該被設定，以致於先前的聲 音資料區塊在已被聲音介面區塊296(圖八）處理之前， 一階内插區塊1 3 0 〇可以處理資料。 左聲音資料及右聲音資料線性内插器部份1 3 0 2、1304 分別接收 Audio Data (Left)及 Audio Data (right)信號 當作輸入’其係為在解格式化及解交錯之後從接收封包的 左右聲音資料。Audio Data (Left)信號被輸入到第一暫 存器1 322。第一暫存器1 322的輸出被提供作為加法器1326 及第二暫存器132 4的輸入。第二暫存器132 4的輸出被提供 作為加法器1 3 2 6的輸入。加法器1 3 2 6的輸出被用來當作除 法器132 8的輸入，其輸出被提供至多工器131 4的第一輸Page 32 200425670 V. Description of the invention (27) logic (C / L) block 1312, left sound data and right sound data multiplexers 1314, 1316. According to an embodiment of the present invention, the selector section 1310 of the first-order interpolation block 13 300 receives the CRC 51 2 from the packet deformatter 298 as an input, and is used to determine a linear interpolation for selecting two sound samples. Still choose to keep the latest sound samples. As discussed above, when the corresponding audio data block 5 i 0 is an error, the CRC 512 is "1". When the corresponding audio data block 510 is zero error, the CRC 512 is "0". According to an embodiment of the present invention, all registers of the first-order interpolation block 3300 are positive edge triggered. These registers are clocked using a clock that is a multiple of 44.1 kHz or a multiple of 48 kHz. The specific speed should be set so that before the previous audio data block has been processed by the audio interface block 296 (Fig. 8), the first-order interpolation block 1300 can process the data. Left sound data and right sound data linear interpolator part 1 3 0 2, 1304 Receive Audio Data (Left) and Audio Data (right) signals as input respectively. Left and right audio data of the packet. The Audio Data (Left) signal is input to the first register 1 322. The output of the first register 1 322 is provided as the input of the adder 1326 and the second register 1324. The output of the second register 1324 is provided as the input of the adder 1 3 2 6. The output of the adder 1 3 2 6 is used as the input of the divider 132 8 and its output is provided to the first input of the multiplexer 13 14
第33頁 200425670 五、發明說明（28) 入。相似的電路也被應用在Audio Data (right)信號，包 括有··暫存器1330、1332、加法器1334、及除法器1336。 除法器1336的輸出被提·供至多工器131 6的第一輸入。暫存 器 1306、1308、1318、1320、1322、1324、133 0及 133 2舉 例來說可以是D型正反器或是RS正反器。Page 33 200425670 V. Description of Invention (28). Similar circuits are also applied to the Audio Data (right) signal, including a register 1330, 1332, an adder 1334, and a divider 1336. The output of the divider 1336 is provided to the first input of the multiplexer 1316. The registers 1306, 1308, 1318, 1320, 1322, 1324, 1330, and 133 2 can be, for example, D-type flip-flops or RS flip-flops.
組合邏輯（C/L)區塊131 2接收X、Y及Z向量當作輸入 其為相對應暫時鄰接聲音資料區塊5 1 0的CRC。如上所討 論，當聲音資料區塊510為錯誤時，CRC為「1」。當聲音 資料區塊510為零錯誤時（，1，），CRC為「0」。 向量X由暫存器1318、132 0所延遲。向量Y由暫存器 1 3 1 8所延遲。向量z未被延遲。當它的輸入向量χγζ組態為 「010」時，組合邏輯（C/L)區塊131 2產生邏輯「1」，也 就是第一聲音資料區塊510為錯誤（，1，），而暫時鄰近其第 一聲音資料區塊5丨〇的兩聲音資料區塊5丨〇為零錯誤（，〇，） 的情況。當「〇 1 〇」的情況發生時，線性内插器部份The combinational logic (C / L) block 131 2 receives X, Y and Z vectors as inputs. It is a CRC corresponding to the temporarily adjacent audio data block 5 1 0. As discussed above, when the audio data block 510 is an error, the CRC is "1". When the audio data block 510 is zero error (, 1,), the CRC is "0". The vector X is delayed by the registers 1318, 1320. The vector Y is delayed by the registers 1 3 1 8. The vector z is not delayed. When its input vector χγζ is configured as "010", the combinatorial logic (C / L) block 131 2 generates logic "1", that is, the first sound data block 510 is wrong (, 1,), and temporarily A case where two sound data blocks 5 and 0 adjacent to the first sound data block 5 and 0 are zero errors (, 0,). When "〇 1 〇" occurs, the linear interpolator part
1302、1304的輸出經由多工器1314、131 6被選出。這是因 為當「0 1 0」的情況發生時，線性内插器部份1 3 〇 2、1 3 可以經由内插來令人滿意地隱匿錯誤。在其他的情況下， 保留暫存器130 6及130 8的輸出被選出以通過多工器1314、 1316〇 保留暫存器1 3 0 6及1 3 0 8保留最新好聲音資料區塊The outputs of 1302 and 1304 are selected via the multiplexers 1314 and 1316. This is because when the situation of "0 1 0" occurs, the linear interpolator sections 1 3 2 and 1 3 can satisfactorily hide errors through interpolation. In other cases, the outputs of the retention registers 130 6 and 130 8 are selected to pass the multiplexers 1314 and 1316. The retention registers 1 3 0 6 and 1 3 0 8 retain the latest good sound data blocks.
200425670 五、發明說明（29) 510。保留暫存益130 6及1 3 0 8有一致能線（E)。僅當致能線 被設定成「1」時（也就是致能線被啟動），允許在保留 暫存器1 3 0 6及1 3 0 8輸入端的信號被保留暫存器6及；[3 0 8 所接收。反之，當致能線沒被啟動（，〇,），保留暫存器 1 3 0 6及1 3 0 8的輸出為先前保留的好樣本值。每當γ使用反 相器1 338、1 340為「〇」時，保留暫存器13〇6及13〇8的致 能線將會被設定成「1」。 接著在本發明之實施例中，根據對三個聲音資料區塊 5 1 0的C R C組態（X Υ Ζ )，不是線性内插器部份1 3 〇 2、1 3 0 4的. 輸出就是保留暫存器1 3 〇 6及1 3 0 8的輸出會被選出當作 Da taL及Da taR到聲音介面區塊296 (圖八）。内插器輸出可 以根據也可不根據XYZ組態（也就是聲音資料的錯誤組 態）來選擇。當内插器輸出並不根據聲音資料的錯誤組態 來選擇時’之前所接收未被錯誤破壞且被保留在保留暫存 器1 3 0 6及1 308的聲音資料會被用來當作1)31^[及1)31^1{傳到 聲音；I面區塊2 9 6。依這樣的方法，本發明之實施例改善 了錯誤隱匿功能。 ° 根據圖十三所示之線性内插器之實施例，在線性内插· 部份1 30 2、1 3 04的資料路徑應被保持完全精準（full precision)，但縮短成2〇位元，因為兩通道的聲音資料長 度是20位元。根據其他實施例，縮短可以根據實施於特定 系統的聲音資料長度而有不同。200425670 V. Description of Invention (29) 510. Retained temporary benefits 130 6 and 1 3 0 8 have consistent energy lines (E). Only when the enable line is set to "1" (that is, the enable line is activated), the signals at the input terminals of the holding registers 1 3 0 6 and 1 3 0 8 are allowed to be held at the register 6 and; [3 0 8 received. Conversely, when the enable line is not activated (, 0,), the outputs of the register 1306 and 1308 are retained as the good sample values previously reserved. Whenever γ uses the inverters 1 338 and 1 340 as “0”, the enable lines of the reserve registers 1306 and 1308 will be set to “1”. Then, in the embodiment of the present invention, according to the CRC configuration (X Υ Z) of the three audio data blocks 5 1 0, it is not the linear interpolator part 1 3 〇2, 1 3 0 4. The output is The outputs of the holding registers 1306 and 1308 are selected as Da taL and Da taR to the sound interface block 296 (Figure 8). The interpolator output can be selected with or without the XYZ configuration (that is, the wrong configuration of the sound data). When the output of the interpolator is not selected based on the wrong configuration of the sound data, the sound data previously received is not corrupted by mistake and is retained in the retention register 1 3 0 6 and 1 308 will be used as 1 ) 31 ^ [and 1) 31 ^ 1 {to the sound; I side block 2 9 6. In this way, the embodiment of the present invention improves the error concealment function. ° According to the embodiment of the linear interpolator shown in Figure 13, in the linear interpolation, the data path of part 1 30 2, 1 3 04 should be kept full precision, but shortened to 20 bits , Because the audio data length of the two channels is 20 bits. According to other embodiments, the shortening may vary depending on the length of the sound material implemented in a particular system.
200425670 五、發明說明（30) 圖十四係為二階内插區塊1 4 〇 〇之實施例，其可以取代 圖十二所示之普通線性内插區塊i 2 〇 2。為了清楚說明，對 應至圖十二部分之二階内插區塊丨4〇〇中的不同部份由虛線 所圍住。二階内插區塊1 4 0 0包括二階内插器部分1 4 0 2，該 内插部分1 402更包括保留暫存器1 404、暫存器1416及 1418、增量器（incrementer， INC)1408、純量器（scaiar) 143卜方波器（squarer)1428、乘法器（multiplier) 1 42 0、1 42 2、除法器1 424及加法器1 426。二階内插區塊 1 400更包括一選擇器部份1 40 6，該選擇器部份14〇6包括 有：反或閘1412、1414、及閘1 434、或閘1 43 6、及多工器 1410。1404、1416、141 8舉例來說可以是d型正反器或是 RS正反器。 根據本發明之實施例，二階内插區塊1 4 0 0的選擇器部 份1 4 0 6接收從封包解格式化器2 9 8來的CRC 51 2當成輸入， 以決定選擇聲音取樣的二階内插或是選擇保留暫存器丨4 〇 4 的輸出。如上所述，當所對應聲音資料區塊5丨〇為錯誤 時’ C R C 5 1 2為「1」。當聲音資料區塊51 〇為零錯誤時， CRC 512為「 0」。 根據本發明之實施例，二階内插區塊丨4 〇 〇的所有暫存 器、閂（latch)及增量器140 8為正緣觸發。當在增量器 1 4 0 8的致能（E )提供「1」時，增量器1 4 〇 8從1開始計數。200425670 V. Description of the invention (30) FIG. 14 is an embodiment of the second-order interpolation block 14 00, which can replace the ordinary linear interpolation block i 2 02 shown in FIG. 12. For the sake of clarity, the different parts of the second-order interpolation block 丨 400 corresponding to the part in Figure 12 are enclosed by dashed lines. The second-order interpolation block 1 4 0 0 includes a second-order interpolator section 1 2 0 2. The interpolation section 1 402 further includes a reserve register 1 404, a register 1416 and 1418, and an incrementer (INC). 1408, scalar (scaiar) 143 square waver (squarer) 1428, multiplier (multiplier) 1 42 0, 1 42 2, divider 1 424 and adder 1 426. The second-order interpolation block 1 400 further includes a selector section 1 40 6. The selector section 1406 includes: OR gate 1412, 1414, and gate 1 434, OR gate 1 43 6, and multiplexing. 1410. 1404, 1416, 1418 can be d-type flip-flops or RS flip-flops, for example. According to the embodiment of the present invention, the selector section 1 4 0 of the second-order interpolation block 14 0 0 receives the CRC 51 2 from the packet deformatter 2 98 as an input to decide to select the second order of the sound samples. Interpolate or choose to retain the output of the register 4 0 4. As described above, when the corresponding audio data block 5o0 is an error, 'C R C 5 1 2 is "1". When the audio data block 51 0 is zero error, the CRC 512 is “0”. According to an embodiment of the present invention, all registers, latches, and incrementers 1408 of the second-order interpolation block 丨 400 are triggered by a positive edge. When "1" is provided in the enable (E) of the incrementer 1408, the incrementer 1408 counts from 1.
第36頁 200425670 五、發明說明（31) 假如在增量器1 408的重置（R)變成「1」，增量器1408狀態 就會被重設成「0」。增量器1 4 0 8的一個輸出被提供到乘 法器1420。增量器1408的輸出也由方波器所方波化，並且 提供給乘法器1 422。乘法器1 42 0的輸出被提供給加法器 1 426，乘法器1 422的輸出被提供給除法器1 424，接著除法 器1 424的輸出提供給加法器1 42 6。加法器1 426的輸出提供 給多工器1410的第一輸入。根據本發明之實施例，在CRC 5 1 2的輸入變成高電位之後，增量器1 4 0 8需要立刻開始從1 開始計數。就接收到不正確的聲音資料取樣的數目來說， 增量器1 4 0 8產生一時間索引（t i m e i n d e X )。此時間索引和胃^ 時間索引的方波被用來量測内插器的一階與二階的項 (term)。一階與二階項分別為暫存器141 6與暫存器1418的 輸入。方波器1 4 2 8被用以產生時間索引的方波。 只有當保留暫存器1 404與暫存器1416、141 8各自的致 動線（E)被設定成「1」時，保留暫存器14〇4與暫存器 1 4 1 6、1 4 1 8才會允許在各自輸入的一信號被接收，否則保 留暫存器140 4與暫存器1416、141 8的輸出被保留在各自之 前的好值。因此，根據本發明之實施例，當χ=「〇」時， 保留暫存器1 404被致能，其輸入被接收且通過到其輸出，攀 並且k供給加法器142 6的輸入，也提供給多工器141〇的第 二輸入。兩個反或閘1412、141 4根據在三個聲音資料區塊 的CRC組態（XYZ)，產生致能信號到暫存器1416、Ul8。Page 36 200425670 V. Description of the invention (31) If the reset (R) of the incrementer 1 408 becomes "1", the state of the incrementer 1408 will be reset to "0". An output of the incrementer 1 4 0 8 is supplied to the multiplier 1420. The output of the incrementer 1408 is also squared by the square waver and supplied to the multiplier 1 422. The output of multiplier 1 42 0 is supplied to adder 1 426, the output of multiplier 1 422 is supplied to divider 1 424, and the output of divider 1 424 is supplied to adder 1 42 6. The output of adder 1 426 is provided to the first input of multiplexer 1410. According to the embodiment of the present invention, after the input of the CRC 5 1 2 becomes high, the incrementer 1 0 0 8 needs to start counting from 1 immediately. In terms of the number of samples of incorrect sound data received, the incrementer 14 0 8 generates a time index (t i m e i n d e X). This time index and stomach ^ time indexed square wave are used to measure the first and second order terms of the interpolator. The first-order and second-order terms are the inputs of register 1416 and register 1418, respectively. A square waver 1 4 2 8 is used to generate a time indexed square wave. Only when the respective actuation lines (E) of the holding register 1 404 and the holding registers 1416, 1418 are set to "1", the holding register 1404 and the holding registers 1 4 1 6, 1 4 Only one 8 will allow a signal to be received at each input, otherwise the outputs of the holding registers 140 4 and the registers 1416, 1418 are kept at their previous good values. Therefore, according to the embodiment of the present invention, when χ = "0", the reserve register 1 404 is enabled, its input is received and passed to its output, and the input of k is supplied to the adder 1426, also provided A second input to the multiplexer 1410. The two OR gates 1412 and 1414 generate enable signals to the registers 1416 and Ul8 according to the CRC configuration (XYZ) in the three audio data blocks.
200425670 五、發明說明（32) 更特別的是，當XY=「00」時，兩個輸入的反 1412致能暫存器1416。當暫存器1416被致能時，在 141 6輸入端的χγ組合被傳到暫存器1416的輸出。減 1=0接收X與γ當作輸入，並且在其輸出端提供乂與也能 到暫存器1 4 1 6的輸入。 的，心 地，當ΧΥΖ=「00 0」時，三個輸入的反或問1418 致此暫存器1418。當暫存器1418被致能，在暫存器 =的χυζ組合被傳到暫存器1418的輸出。減法器“32: Υ(經由純量器1431)與2當作輸入，並且在其 k供X、Υ與ζ的組合到暫存器i 4 J 8的輸入。 •八 加 算。換 的輸入 皆為「 能，並 出。然 「1」〕 聲音樣 而代之 現在各 輸入0 法器1 426的輸出為一零錯誤聲音資料取樣的總計 句話說，只有零錯誤聲音取樣可以到達加法器丨426 。因此，當所有聲音取樣乂^為零錯誤（ 〇」）時，所有保留暫存器1 404、U16、14^;^ΥΖ 且將在其輸入的目前零錯誤樣本傳送到各自的輸 而，當任何XYZ聲音取樣包括錯誤時（也就是為 ，各自的暫存器將不會被致能以傳送包括錯誤的 本，因此它將不被加法器丨426在總計算中考慮。取 的是，先前保留在各自暫存器的好聲音樣本將會出 自暫存器的輸出，並且被傳送到加法器1 426各自的200425670 V. Description of the invention (32) More specifically, when XY = "00", the two input inverse 1412 enables the register 1416. When the register 1416 is enabled, the χγ combination at the input of 1416 is passed to the output of the register 1416. Minus 1 = 0 receives X and γ as inputs, and provides 乂 and 能 to the registers 1 4 1 6 at its output. Yes, heartily, when XYZ = "00 0", the inverse OR of three inputs 1418 is sent to this register 1418. When register 1418 is enabled, the χυζ combination in register = is passed to the output of register 1418. Subtractor "32: Υ (via scalar 1431) and 2 as inputs, and at its k, the combination of X, Υ, and ζ is input to the register i 4 J 8. • Eight additions. The input for the change It is "can, parallel. Then" 1 "] sound samples instead. Now each input is 0. The output of 1 426 is a total of zero error sound data samples. In total, only zero error sound samples can reach the adder. 426 . Therefore, when all sound samples 乂 ^ are zero errors (0), all registers 1 404, U16, 14 ^; ^ ΥZ are retained and the current zero-error samples input at their input are transmitted to their respective inputs. When any XYZ sound samples include errors (that is, the respective registers will not be enabled to transmit the error-included copies, so it will not be considered by the adder 426 in the overall calculation. Taken previously, Good sound samples retained in their respective registers will come from the output of the register and will be passed to the respective 1 426 adder's
第38頁 200425670 五、發明說明（33) 當多工器1410的第一輸入（也就是加法器142 6的輸 出）被選擇器部份1 4 0 6利用多工器1 4 1 0的選擇線（S )選出 時’多工器1410的第一輸入被傳送到多工器的輸出， 並且送到二階内插區塊1 4 0 0的聲音輸出（Audio ουτ)。也 就是ΧΥΖ等於「10 0」、「101」、「110」其中之一或多 者’多工器1410的第一輸入被選擇器部份140 6選出，以傳 送到多工器1 4 1 0的輸出，並且利用多工器丨4丨〇的選擇線傳 送到二階内插區塊1 4 0 0的聲音輸出。 當多工器1 4 1 0的第二输入（也就是保留暫存器丨4 〇 4的 輸出）被選擇器部份140 6利用多工器1410的選擇線選出 時，多工器1 4 1 0的第二輸入被傳送到多工器1 4 1 〇的輸出， 並且送到二階内插區塊1 40 0的聲音輸出（Audi〇 〇υτ)。也 就是說’當X Υ Ζ不等於「1〇〇」、「1〇1」、「11〇」其中之 一或多者時，多工器1410的第二輪入被選擇器部份14〇6選 出，以傳送到多工器1 41 0的輸出並且利用多工器丨4丨〇的選 擇線傳送到二階内插區塊1 400的聲音輸出。及閘Η34及或 閘1 4 3 6實現上述之選擇程序。 因此，根據本發明之實施例，二階内插區塊14〇〇的不馨 同部分將根據ΧΥΖ的組態被致能，以致於内插器估計沒被 錯誤所干擾的聲音資料。資料路徑應該内部地被保持在完 全精準，但在多工器1410的輸入縮短成2〇位元。根據其他 的實施例，縮短可以根據實施於特殊系統的聲音資料長度Page 38 200425670 V. Description of the invention (33) When the first input of the multiplexer 1410 (ie, the output of the adder 1426) is selected by the selector 1 4 0 6 using the selection line of the multiplexer 1 4 1 0 (S) When selected, the first input of the 'multiplexer 1410 is transmitted to the output of the multiplexer and sent to the audio output (Audio ουτ) of the second-order interpolation block 1 400. That is, XYZ is equal to one or more of "10 0", "101", and "110". The first input of the multiplexer 1410 is selected by the selector portion 140 6 to be transmitted to the multiplexer 1 4 1 0 And use the selection line of the multiplexer 丨 4 丨 〇 to transmit to the sound output of the second-order interpolation block 1400. When the second input of the multiplexer 1 4 1 0 (that is, the output of the holding register 丨 4 〇 4) is selected by the selector section 140 6 using the selection line of the multiplexer 1410, the multiplexer 1 4 1 The second input of 0 is transmitted to the output of the multiplexer 1410, and is also sent to the sound output (Audi0υτ) of the second-order interpolation block 1400. In other words, when X Υ Z is not equal to one or more of "100," "10," and "11," the second round of the multiplexer 1410 enters the selected part 14. 6 is selected to be transmitted to the output of the multiplexer 141 0 and to the sound output of the second-order interpolation block 1 400 using the selection line of the multiplexer 丨 4 丨. And gate 34 and or gate 1 4 3 6 implement the selection process described above. Therefore, according to the embodiment of the present invention, different parts of the second-order interpolation block 1400 will be enabled according to the configuration of the XYZ, so that the interpolator estimates the sound data that is not disturbed by the error. The data path should be kept completely accurate internally, but the input at the multiplexer 1410 is shortened to 20 bits. According to other embodiments, the length of the sound data which can be implemented in a particular system is shortened
第39頁 200425670 五、發明說明（34) 而有不同。 圖十五係為多階内插區塊1 5 0 0的實施例，其可取代圖 十二所示之普通内插區塊1 2 0 2。多階内插區塊1 5 0 0可包括 多個具有一多工器150 4在内插器輸出間選擇的内插器1502 (範圍從線性内插器（一階）到η階内插器）。選擇的決 定係由邏輯方塊1 5 0 6所決定，邏輯方塊1 5 0 6係根據比較器 (：0肘？1 1 5 08及（：0肘？21510的結果來決定。（；01^1 1 5 08比較 訊噪比估計器區塊1 5 1 2的輸出與一臨界值vSNR, c〇MP2 1 5 1 0 比較錯誤率估計器區塊1514的輸出與一臨界值Verr〇r。 計器區，1512根據已接收基頻信號估計接收信號的SNR， 一般而言在資料解調之前，會要求其軟決定值。錯誤率估 計方塊151 4估計已接收信號的錯誤率。 於高SNR及低錯誤率的條件 當低SNR及高錯誤率的條件 内插方法的選擇可以根據啟 以根據即時運算的SNR及/或 之執行中做進一步選擇。 根據本發明之實施例，對 下’高階内插器可以被使用· 下，低階内插器可以被使用: 動的初始條件來決定 片弋，或是可 錯誤率的估計在更本Page 39 200425670 V. Description of Invention (34). FIG. 15 is an embodiment of a multi-order interpolation block 1 500, which can replace the ordinary interpolation block 1 2 2 shown in FIG. Multi-order interpolation block 1 500 can include multiple interpolators 1502 with a multiplexer 150 4 interpolator output (ranging from linear interpolator (first order) to n-order interpolator ). The decision of choice is determined by logic block 1 506, which is determined by the results of the comparators (: 0 cubits? 1 1 5 08 and (: 0 cubits? 21510). (; 01 ^ 1 1 5 08 Compare the output of the signal-to-noise ratio estimator block 1 5 1 2 with a threshold value vSNR, c〇MP2 1 5 1 0 Compare the output of the error rate estimator block 1514 with a threshold value Verr〇r. Counter area 1512 estimates the SNR of the received signal based on the received baseband signal. Generally speaking, the soft decision value is required before data demodulation. Error rate estimation block 1514 estimates the error rate of the received signal. For high SNR and low error The selection of the conditional interpolation method when the low SNR and high error rate conditions can be further selected according to the real-time calculation of the SNR and / or the execution. According to the embodiment of the present invention, the lower-order interpolator Can be used · The low-order interpolator can be used: the initial conditions of the motion to determine the slice, or the estimation of the error rate
甘炅先進的實施 根據本發明之實乂 音資料區塊錯誤率、=錯誤率可以是位元錯誤率、聲 校正，位元錯誤率就’疋封包錯誤率。假如使用前向錯誤 根據發生在N個封包?可^以/皮估計。封包與區塊錯誤率可以 3疋聲音資料區塊的CRC錯誤數目來計According to the actual implementation of the present invention, the audio data block error rate and error rate can be bit error rate and sound correction, and the bit error rate is the packet error rate. If forward error is used, it can be estimated based on N packets. The packet and block error rate can be calculated from the number of CRC errors in the 3 疋 audio data block.
第40頁 200425670 五、發明說明（35) 算0 當大量錯誤發生時，聲音品質明顯下降。在這種情況 下’本發明之實施例提供一靜音信號.啟動部份16〇〇，如圖 十六所示。靜音信號啟動部份1 6 0 0啟動〜靜音作號，使得 聲音接收器22 8可使揚聲器232(圖二）靜音。 根據本發明之實施例’控制内部靜音信號（Mute)的狀 態圖如圖十七所示。Mute NC是可規劃參數，可以在初 始設定中被設定。Mu t e th代表發生錯誤的連續聲音資料區 · 塊的一臨界值。NC代表沒有錯誤之連續聲音資料區塊的一 臨界值。 如圖十七所示，連績聲音資料區塊錯誤的數目被判定 是否大於M u t e th( S1 7 0 2 )。假如連續聲音資料區塊錯誤數目 不大於Mute th(否）的話，則S1 702會被重複。另一方面，假 如連續聲音資料區塊錯誤數目大於Mute th(是）的話，靜音 信號由靜音信號啟動部份1 6 0 0 (S1 704 )所啟動。Page 40 200425670 V. Description of the invention (35) Count 0 When a large number of errors occur, the sound quality decreases significantly. In this case, an embodiment of the present invention provides a mute signal. The activation section 160 is shown in FIG. The mute signal activation part 1660 is activated to mute the signal, so that the sound receiver 228 can mute the speaker 232 (Figure 2). A state diagram of controlling the internal mute signal (Mute) according to the embodiment of the present invention is shown in FIG. Mute NC is a programmable parameter and can be set in the initial settings. Mu t e th represents a critical value of the continuous sound data area where the error occurred. NC represents a threshold value for continuous audio data blocks without errors. As shown in Fig. 17, the number of consecutive errors in the audio data block is judged whether it is greater than M u t e th (S 1 7 0 2). If the number of consecutive audio data block errors is not greater than Mute th (No), S1 702 will be repeated. On the other hand, if the number of consecutive audio data block errors is greater than Mute th (Yes), the mute signal is activated by the mute signal activation section 16 0 (S1 704).
接著判斷連續正確聲音資料區塊的數目是否大於NC (S1 7 0 6 )。假如連續正確聲音資料區塊的數目不大於NC (否）的話，則S1 7 0 6會被重複。另一方面，假如連續正確 聲音資料區塊的數目大於NC(是）的話，靜音信號就變成不 作用（inactive)(S1708)。It is then determined whether the number of consecutive correct sound data blocks is greater than NC (S1 7 0 6). If the number of consecutive correct sound data blocks is not greater than NC (No), S1 7 0 6 will be repeated. On the other hand, if the number of consecutive correct audio data blocks is greater than NC (Yes), the mute signal becomes inactive (S1708).
第41頁 200425670 五、發明說明（36) 根據本發明之實施例， 一 斷的理由，一語音資料方 圖十八所不，為了測試與診 64個聲音資料區塊被監測。‘=誤率由錯誤監測部份1 80 0在 1)時，語音資料區塊錯誤就田敗（也就是CRC = 料區塊CRC失敗的數目以產’扭疋。監測在64個聲音資 « μ產生一錯誤計數。此 用來決定一錯誤監測信號的頻率。 、 1 表4總結在64個64個聲音資料區塊中CRC 512失敗數 所對應的錯誤計數之輸出頻率，在超過32個CRC失敗的情 況下’其應該在低邏輯（也就是邏輯「〇」）。在其他情 況下，錯誤監測信號為頻率等於表4所示的方波。錯誤監 測部份1 8 0 0實現如表4的對應。一錯誤計數L E D丨8 0 2可以 驅動一發光二極體（LED)’以在連線狀態下提供一視覺診 斷。注意表4表示錯誤對輸出頻率的一特定對應關係，其 他適合的對應關係也可以被實現。Page 41 200425670 V. Explanation of the invention (36) According to the embodiment of the present invention, one voice data is shown in Fig. 18. For testing and diagnosis, 64 sound data blocks are monitored. '= Error rate from the error monitoring part 1 80 0 in 1), the voice data block error is defeated (that is, CRC = the number of data block CRC failures to produce' twisting. Monitoring in 64 sound data « μ generates an error count. This is used to determine the frequency of an error monitoring signal. Table 1 summarizes the output frequency of the error count corresponding to the CRC 512 failures in 64 64 sound data blocks. In case of failure, it should be at low logic (ie logic "0"). In other cases, the error monitoring signal is a square wave with a frequency equal to that shown in Table 4. The error monitoring part 1 8 0 0 is implemented as shown in Table 4 Correspondence. An error counting LED 丨 8 0 2 can drive a light-emitting diode (LED) 'to provide a visual diagnosis in the connected state. Note that Table 4 shows a specific correspondence between errors and output frequencies. Other suitable Correspondence can also be implemented.
第42頁 200425670Page 42 200425670
五、發明說明（37) 表4 (輸出頻率與CRC失敗數目的對應關係） CRC失敗數目 輸出 _ 0 ohz (led 1*6 BCK/8192 ^ 6-16 BCK/16384 —- 16-32 —iCK/32768 - >32 @2 (LED總是齒FT ~ 總之，以 斤述者’僅為本發明之較佳實施例而已’ :::以之限疋本發明所實施之範圍。大凡依本 作之均等變化與修，，皆應仍屬於本發2 §月專 =…内，謹請責審查委員明鑑，並祈惠准發，月曰專利涵 禱0 疋戶斤荃 200425670 圖式簡單說明 五、【圓示簡單說明】 本發明以舉例的方式來說明，但並不以此為限。圖示 簡單說明如下： 圖一係為用於無線傳輸聲音信號之系統的典型架構方 塊圖； 圖二與圖三係為根據本發明實施例之示範性無線聲音 晶片組的方塊圖， 圖四係為根據本發明實施例之示範性數位數據機發射 器的方塊圖； 圖五係根據本發明實施例之示範性封包格式； 圖六係根據本發明實施例之可使用於圖四所示之發射 器的一時脈產生器； 圖七係為根據本發明實施例之可使用於圖四所示之發 射器之示範性聲音資料區塊交錯器的方塊圖； 圖八係為可使用於本發明實施例之示範性數位數據機 接收器的方塊圖； 圖九係為根據本發明實施例之可使用於如圖八所示之 數位數據機接收器的非連貫解調器； 圖十係為根據本發明實施例之表示一示範性校正CRC 及聲音資料區塊之時序圖。 圖十一係為根據本發明實施例之可利用於如圖八所示 之數位數據機接收器之聲音資料區塊解交錯器之方塊圖； 圖十二係為根據本發明實施例之可使用於如圖八所示 之數位數據機接收器之示範性内插部分份的方塊圖；V. Explanation of the invention (37) Table 4 (The correspondence between the output frequency and the number of CRC failures) CRC failure number output _ 0 ohz (led 1 * 6 BCK / 8192 ^ 6-16 BCK / 16384 —- 16-32 —iCK / 32768-> 32 @ 2 (LED is always tooth FT ~ In short, those who describe it are 'only the preferred embodiment of the present invention' ::: The limit is to limit the scope of the present invention. The equal changes and repairs should still belong to this issue. 2 § Monthly Special = ..., I would like to blame the reviewing committee for your reference, and pray for the issuance of the patent. [Circumscription Simple Explanation] The present invention is described by way of example, but is not limited thereto. The diagram is briefly explained as follows: Figure 1 is a block diagram of a typical architecture of a system for wirelessly transmitting sound signals; Figure 2 Figure 3 is a block diagram of an exemplary wireless sound chipset according to an embodiment of the present invention, Figure 4 is a block diagram of an exemplary digital data transmitter according to an embodiment of the present invention; Figure 5 is a block diagram of an exemplary digital modem transmitter according to an embodiment of the present invention; An exemplary packet format; FIG. 6 shows an exemplary packet format according to an embodiment of the present invention. A clock generator used in the transmitter shown in FIG. 4; FIG. 7 is a block diagram of an exemplary sound data block interleaver that can be used for the transmitter shown in FIG. 4 according to an embodiment of the present invention; FIG. FIG. 9 is a block diagram of an exemplary digital modem receiver that can be used in an embodiment of the present invention; FIG. Fig. 10 is a timing chart showing an exemplary correction of the CRC and sound data blocks according to an embodiment of the present invention. Fig. 11 is a digital modem according to an embodiment of the present invention that can be used in Fig. 8 The block diagram of the receiver's sound data block deinterleaver; Figure 12 is a block diagram of an exemplary interpolation portion that can be used in the digital modem receiver shown in Figure 8 according to an embodiment of the present invention;
第44頁 200425670 圖式簡單說明 圖十三係為根據本發明實施例之可使用於如圖十二所 示之一般内插區塊之位置之示範性第一階内插區塊； 圖十四係為根據本發明實施例之可使用於如圖十二所 示之一般内插區塊之位置之示範性第二階内插區塊； 圖十五係為根據本發明實施例之可使用於如圖十二所 示之一般内插區塊之位置之示範性多階内插區塊； 圖十六係為根據本發明實施例之可使用於如圖八所示 之數位數據機接收器之示範性靜音信號啟動部分的方塊 圖； 圖十七根據本發明實施例之用以控制内部靜音信號狀I 態的狀態圖；以及 圖十八根據本發明實施例之用以監測聲音資料區塊錯 誤率的錯誤監測部份方塊圖。 圖示元件符號說明Page 44 200425670 Brief description of the drawings FIG. 13 is an exemplary first-order interpolation block that can be used for the position of the general interpolation block shown in FIG. 12 according to an embodiment of the present invention; FIG. 14 Fig. 15 is an exemplary second-order interpolation block that can be used for the position of the general interpolation block shown in Fig. 12 according to an embodiment of the present invention; An exemplary multi-level interpolation block at the location of a general interpolation block as shown in FIG. 12; FIG. 16 is an example of a digital modem receiver that can be used in the digital modem receiver shown in FIG. 8 according to an embodiment of the present invention. A block diagram of an exemplary mute signal activation section; FIG. 17 is a state diagram for controlling an internal mute signal state according to an embodiment of the present invention; and FIG. 18 is used to monitor a sound data block error according to an embodiment of the present invention Block diagram of the error detection part of the rate. Graphic component symbol description
100 系 統 102 音頻設備 104 聲 音 類 比 至 數 位 轉 換器 106 數 位 數 據 機 發 射 器 108 射 頻 發 射 器 110、 112 天旅 114 :射頻接收器 116 數 位 數 據 機 接 收 器 118 聲 音 DAC 120 揚聲器 202 數 位 無 線 發 射 器 204 數位數據機發射器 206 射 頻 發 射 器 208 天線 第45頁 200425670 圖式簡單說明 210 聲音發射器 212 聲音ADC方塊 214 功率控制發光二極體 216 聲音設備 218 數位無線接收 22〇\ 2 2 2 天線 224 射頻接收器 226 數位數據機接收器 228 聲音接收器 230 聲音DAC 232 揚聲器 234 功率控制發光二極體 236 聲音介面區塊 238 封包格式器區： 240 前向錯誤校正編碼 器 242 調變器 244 渡波Is 246 DAC 248 鎖相時脈產生器 250 時脈產生器 252 控制介面部份 254 系統時脈 256 符元時脈 258 合成時脈 260 MCLKO信號 262 RF介面 264 外在介面 266 邏輯運算 270 天線切換器 276 AGC/天線選擇區塊 278 控制介面部份 280 RF介面 281 非揮發性記憶體 282 ' 284 ADC 283 框開始信號 285 外部介面 286 時脈恢復區塊 287 鎖相時脈產生器 288 解調器 289 合成時脈 290 FEC解碼器100 System 102 Audio Device 104 Sound Analog to Digital Converter 106 Digital Modem Transmitter 108 RF Transmitter 110, 112 Sky Travel 114: RF Receiver 116 Digital Modem Receiver 118 Sound DAC 120 Speaker 202 Digital Wireless Transmitter 204 Digital Modem transmitter 206 Radio frequency transmitter 208 Antenna Page 45 200425670 Brief description of the diagram 210 Sound transmitter 212 Sound ADC block 214 Power control light emitting diode 216 Sound device 218 Digital wireless reception 22 0 2 2 2 Antenna 224 RF reception 226 Digital modem receiver 228 Sound receiver 230 Sound DAC 232 Speaker 234 Power control light-emitting diode 236 Sound interface block 238 Packet formatter area: 240 Forward error correction encoder 242 Modulator 244 Crossover Is 246 DAC 248 Phase-locked clock generator 250 Clock generator 252 Control interface part 254 System clock 256 Symbol clock 258 Synthetic clock 260 MCLKO signal 262 RF interface 264 External interface 266 Logic operation 270 Antenna Switch 276 AGC / Antenna selection block 278 Control interface part 280 RF interface 281 Non-volatile memory 282 '284 ADC 283 Frame start signal 285 External interface 286 Clock recovery block 287 Phase-locked clock generator 288 Demodulation 289 Synthetic Clock 290 FEC Decoder
第46頁 200425670 圖式簡單說明 291 時脈產生器 292 系統時脈 293 MCLKO信號 294 符元時脈 295 内插部份 296 聲音介面區塊 297 恢復時脈 298 封包解格式化器 299 記憶體介面 303 記憶體 305 記憶體介面 438 框同步區塊 500 封包 502 前言 504 框起始棚 506 標頭 508 循環冗餘檢查 510 聲音資料 512 CRC 514 命令欄 516 CRC 602 MCLKO一SEL 604 除以二方塊 606 OS一SEL 608 除以八方塊 610 除以四方塊 700 聲音資料區塊交錯器 702 緩衝器 704 交錯定序器 90 2、 9 0 4 微分偵測器 906 加法器 908 截剪器 1100 聲音資料區塊解交錯器 1102 緩衝器 1 104 解交錯定序器 1202 普通内插區塊 1 2 0 4 保留區塊 1206 選擇器方塊 1 3 0 0 一階内插區塊 1302 左聲音資料線性内插器部份 1304 右聲音資料線性内插器部份 1306 左聲音資料保 留暫存器Page 46 200425670 Brief description of the diagram 291 Clock generator 292 System clock 293 MCLKO signal 294 Symbol clock 295 Interpolation section 296 Sound interface block 297 Restore clock 298 Packet deformatter 299 Memory interface 303 Memory 305 Memory interface 438 Frame synchronization block 500 Packet 502 Preface 504 Frame starting shed 506 Header 508 Cyclic redundancy check 510 Audio data 512 CRC 514 Command bar 516 CRC 602 MCLKO-SEL 604 Divide by two blocks 606 OS one SEL 608 divided by eight squares 610 divided by four squares 700 Sound data block interleaver 702 Buffer 704 Interleaving sequencer 90 2, 9 0 4 Differential detector 906 Adder 908 Clipper 1100 Sound data block deinterlacing 1102 Buffer 1 104 Deinterlacing Sequencer 1202 Normal Interpolation Block 1 2 0 4 Reserved Block 1206 Selector Block 1 3 0 0 First Order Interpolation Block 1302 Left Sound Data Linear Interpolator Part 1304 Right Audio data linear interpolator part 1306 Left audio data retention register
第47頁 200425670 1308 右聲音資料保留暫存器 1310 選擇器部份 1312 組合邏輯方塊 1314 左聲音資料多 工器 1316 左聲音資料多 工器 1318^ 1320、 1322、 1 324、1 330、1332 暫存 1326 加法器 1328 除法器 1334 加法器 1336 除法器 1 338 ^ 1 340 反相器 1400 二階内插區塊 1402 二階内插器部 分 1404 保留暫存器 1406 選擇器部份 1408 增量器 1410 多工器 1412、 1 4 1 4反或闡 、1 41 8 暫存器 1420、1422乘法器 除法器 方波器 純量器 及閘 多階内 多工器 比較器 訊噪比 錯誤率 靜音信 錯誤監 1428 1431 1434 1500 1504 1508 1512 1514 1600 1800 插區塊 COMP1 估計器 估計器 號啟動 測部份 區塊 區塊 部份 1 4 2 6加法器 1 4 3 0減法器 1 432減法器 1 4 3 6 或閘 1 5 0 2内杨器 1 5 0 6邏輯方塊 1510比較器COMP2 1 802錯誤計數ledPage 47 200425670 1308 Right sound data retention register 1310 Selector section 1312 Combination logic block 1314 Left sound data multiplexer 1316 Left sound data multiplexer 1318 ^ 1320, 1322, 1 324, 1 330, 1332 temporary storage 1326 adder 1328 divider 1334 adder 1336 divider 1 338 ^ 1 340 inverter 1400 second-order interpolation block 1402 second-order interpolator section 1404 reserved register 1406 selector section 1408 incrementer 1410 multiplexer 1412, 1 4 1 4 inverse or interpretation, 1 41 8 registers 1420, 1422 multiplier divider square wave scalar and gate multi-stage internal multiplexer comparator signal-to-noise ratio error rate mute signal error monitor 1428 1431 1434 1500 1504 1508 1512 1514 1600 1800 Insert block COMP1 Estimator Estimator number Start measuring part block block part 1 4 2 6 Adder 1 4 3 0 Subtractor 1 432 Subtractor 1 4 3 6 OR Gate 1 5 0 2 inner device 1 5 0 6 logic block 1510 comparator COMP2 1 802 error count led
| Application Number | Priority Date | Filing Date | Title |
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| US10/435,176US7155654B2 (en) | 2003-04-04 | 2003-05-10 | Low complexity error concealment for wireless transmission |
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| TW200425670Atrue TW200425670A (en) | 2004-11-16 |
| TWI242949B TWI242949B (en) | 2005-11-01 |
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| TW93105453ATWI242949B (en) | 2003-05-10 | 2004-03-02 | Apparatus and method for low complexity error concealment for wireless transmission |
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| TW (1) | TWI242949B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI814734B (en)* | 2017-09-28 | 2023-09-11 | 南韓商三星電子股份有限公司 | Calculation device for and calculation method of performing convolution |
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI814734B (en)* | 2017-09-28 | 2023-09-11 | 南韓商三星電子股份有限公司 | Calculation device for and calculation method of performing convolution |
| Publication number | Publication date |
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| TWI242949B (en) | 2005-11-01 |
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