200423348 五、發明說明（1) [發明所屬之技術領域】 本發明係關於一種具散熱片之半導體封裝件，尤指一 種可釋放該散熱片之應力的半導體封裝件。 i【先前技術】200423348 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package with a heat sink, especially a semiconductor package that can release the stress of the heat sink. i [prior art]
I | 覆晶式球栅陣列（FI ip-Chip Bai 1 Grid Array, F C B G A)半導體封裝件係為一種同時具有覆晶與球栅陣列之 封裝結構’以使至少一晶片的作用表面（A c t丨v e $ u r f a c e ) 可藉由多數銲塊（S 〇 1 d e r B u m p s )而電性連接至基板 (Substrate)之一表面上，並於該基板之另一表面上植設 多數作為輸入/輸出（I /〇）端之銲球（S〇1 d e r B a 1 1 );此一 封l結構由於可大幅縮減體積，以使該封裝件中晶片與基 板之比例更趨接近，同時亦減去習知金線（W i r e )之設計， 而可降低阻抗提昇電性，以避免訊號於傳輸過程中產生扭 曲’因：此確已成為下一世代晶片與電子元件的主流封裝技 術。 由於該覆晶式球柵陣列封裝的優越特性，使其多係運 用於高積集度（I n t e g r a t i〇η )之多晶片封裝件中，以符該 型電子元件之犖積與運算需求，惟此類電子元件亦由於其： 高運算特性，使其於運作過程所產生之熱能亦將較一般封 裝件為高，因此，其散熱效果是否良好即成為該類封裝技 術影響品質良率的重要關鍵；對習知之覆晶式球柵陣列封 裝件而言，由於其晶片上並無金線與銲線墊（Finger)之設 計，故可直接將用以進行散熱之散熱片（Heat Sink)黏覆 於該晶片的非作用表面（N〇n-active Surface)上，而不需I | FI ip-Chip Bai 1 Grid Array (FCBGA) semiconductor package is a packaging structure with both flip-chip and ball-grid array 'to make the active surface of at least one wafer (A ct 丨ve $ urface) can be electrically connected to one surface of the substrate (substrate) through a plurality of solder bumps (S 〇 1 der B umps), and the majority of the other surface of the substrate is implanted as input / output (I / 〇) end of the solder ball (S〇1 der B a 1 1); this structure can greatly reduce the volume, so that the ratio of the chip to the substrate in the package closer to the same time, while also reducing the conventional The design of the wire (Wire) can reduce the impedance and improve the electrical properties, so as to avoid distortion of the signal during transmission. This is why it has become the mainstream packaging technology for the next generation of chips and electronic components. Due to the superior characteristics of the flip-chip ball grid array package, it is mostly used in multi-chip packages with high integration (Integrati0η) to meet the accumulation and computing requirements of this type of electronic components. Such electronic components are also due to their high computing characteristics, so that the thermal energy generated during operation will be higher than that of ordinary packages. Therefore, whether the heat dissipation effect is good or not becomes an important key for this type of packaging technology to affect quality and yield. ; For the conventional flip-chip ball grid array package, since there is no gold wire and finger pad design on the wafer, the heat sink (Heat Sink) for heat dissipation can be directly pasted. On the non-active surface of the wafer without the need for
17154矽品.ptd 第7頁 ΛΊ ή 200423348 五、發明說明（2) ，透過導熱性較差的封裝膠體（Enc uUn 從而形成-晶片-膠黏劑-散熱片_外界的直 •達至一遠較其他封裝件為佳的散熱功效。 例如美國專利第5，9 0 9，0 5 6號專利，即提出一具有散 -熱片的覆晶式球柵陣列封裝件5，其係如第6 A圖所示，於 一基板50上設置支撐件51 (stlffener)，並將散熱片52點 置於該支撐件5 1上，而以一樹脂53 (Ep〇xy )、膠帶 ' (T a b )、或也、封材料（s e a 1 )接合該散熱片5 2與晶片5 4，以 ^揮散熱功效；或如第6B圖所示的另一實施例，以一相變 暑（ph we Change)材料5 5接合該散熱片52與晶片54，並= 如圖所不之屏障環56 (Dam Ring)避免該相變化材料55於 相變化時滲漏出該散熱片與晶片之接合層；此外，該專利 亦提出如第6C圖所示的另—實施例，係於該散熱片W上形 成一體、成型之環狀固定部52，，以藉其將散熱片52接置於 該基板5〇上，同樣可以該散熱片52與晶片54之直接黏接而 發揮快速散熱的功效。 # &接而 准此頮白：：曰曰式球柵封裝件5之散熱設言十，雖可利 用其蛛金線之覆晶式設計，.而 二:- 而採將散熱片5 2直接接觸晶片17154 硅 品 .ptd Page 7 ΛΊή 200423348 V. Description of the invention (2), through the formation of encapsulation gel (Enc uUn with poor thermal conductivity) to form -chip-adhesive-heat sink_external direct Other packages are better for heat dissipation. For example, US Patent No. 5,9,09,506, which proposes a flip-chip ball grid array package 5 with a heat-dissipation sheet, which is shown in Section 6 A. As shown in the figure, a support 51 (stlffener) is provided on a substrate 50, and a heat sink 52 is placed on the support 51, and a resin 53 (EpOxy), tape (Tab), Or, a sealing material (sea 1) joins the heat sink 5 2 and the chip 5 4 to radiate heat dissipation effect; or as another embodiment shown in FIG. 6B, a phase change (ph we Change) material is used. 5 5 The heat sink 52 and the wafer 54 are joined, and a barrier ring 56 (Dam Ring) as shown in the figure prevents the phase change material 55 from leaking out of the joint layer between the heat sink and the wafer when the phase changes; in addition, the The patent also proposes another embodiment as shown in FIG. 6C, which is formed on the heat sink W to form an integral and formed ring-shaped fixing portion 52 so as to borrow it. The heat sink 52 is connected to the substrate 50, and the heat sink 52 and the chip 54 can be directly adhered to exert the effect of rapid heat dissipation. # &Amp; The following is true: :: Yue type ball grid package The heat dissipation design of 5 is ten, although the flip-chip design of its spider wire can be used, and the second one is:-The heat sink 5 2 is directly contacted with the chip
5 4之方式提昇其散熱效率，彳θ丄 ^ ^ ^ K 麄 干 但此一接置方法卻將產生其他 ’質問題，此係由於散熱片材料、晶片材料、膠黏劑、甚 至基板材料等之熱膨脹係數（coefiicient 〇f ThermalThe method of 5 4 improves its heat dissipation efficiency. 彳 θ 丄 ^ ^ ^ K 麄 is dry, but this connection method will cause other quality problems, which are due to heat sink material, wafer material, adhesive, and even substrate material. Coefiicient 〇f Thermal
ExpanS1〇n， CTE)均不同，因此當該封裝件5於後續可靠度 測試中經歷極大之溫度變化時，不同材料的接合表面即可 能因材料熱應變量之差異’而產生熱應力並衍生各種品質ExpanS10n, CTE) are all different, so when the package 5 undergoes extreme temperature changes in subsequent reliability tests, the bonding surfaces of different materials may generate thermal stress due to differences in the thermal strain of the material and generate various quality
17154矽品.ptd r 11I,17154 Silicon product.ptd r 11I,
200423348 五、發明說明（3) 問題’以前述散熱片5 2與晶片5 4之接合表面為例，一般散 熱片所使用之銅材料其熱膨脹係數平均約在1 6. 3 ppm/t 左右，而作為晶片之矽材料其熱膨脹係數則僅約為2. 8至 3 · 3 ppm/°C，因此，當此類封裝件5於封裝完成而欲進行 後續諸如溫度循環試驗（T h e r m a 1 C y c 1 i n g T e s t，T S Ό、 熱震試驗（Thermal Shock Test，TST)、或高溫儲存試驗 (High Temperature Storage Life Test， HTST)等可靠度 測§式時’即可能因咼溫環境或溫度急遽變化之影響而形成 各種熱應力之破壞。 因此’對前述之覆晶式球拇陣列封裝件5而言，當其 處於一增溫環境時，此時熱膨脹係數較大之散熱片5 2所產 生的膨脹熱變形量將較晶片5 4為大，並受該散熱片5 2之中 央部位與晶片5 4相互黏接的拘束影響而產生一彎曲 (Bend丨ng)’如弟7 Α圖之剖視圖所示，將導致該散熱片5 2 與晶片54向上翹曲（Warpage)，同時，由於該散熱片52内 所產生之熱膨脹應力係較晶片5 4為大，故其彎曲變形量亦 將大於晶片54而使兩者有脫層61 (Delami/natl〇n)之虞， 進而可能導致黏接於該，熱片54外圍的支撐件5丨受壓變 形，或降低晶片5 4下方之銲塊5 7的連接品質等；此外，若 自三維受力圖的角度觀之’可如第7B圖所示，將該處於^ 溫環境的散熱片52視為一受到兩正交力矩Μι、心作用之板 塊（P 1 a t e )，亦即以Μ丨、Μ 2模擬該散熱片5 2受熱所承受之 彎曲力矩（Bending Moment)，此時，其上表面528之\、 方向（如圖所示）將分別產生一最大杈伸熱應力σ !、σ200423348 V. Description of the invention (3) Problem 'Taking the joint surface of the heat sink 5 2 and the wafer 5 4 as an example, the copper material used for general heat sinks has an average thermal expansion coefficient of about 16.3 ppm / t, and The silicon material used as the chip has a thermal expansion coefficient of only about 2.8 to 3.3 ppm / ° C. Therefore, when such a package 5 is completed in the package, it is necessary to perform subsequent tests such as temperature cycling (T herma 1 C yc 1 ing T est, TS Ό, Thermal Shock Test (TST), or High Temperature Storage Life Test (HTST) reliability measurement § formula 'may be due to high temperature environment or rapid changes in temperature The influence of the thermal stress will cause the destruction of various thermal stresses. Therefore, for the flip-chip ball-thumb array package 5 described above, when it is in a temperature-increasing environment, at this time the expansion caused by the heat sink 5 2 with a larger thermal expansion coefficient The amount of thermal deformation will be greater than that of the wafer 54, and will be affected by the constraint of the central portion of the heat sink 5 2 and the wafer 54 being bonded to each other. As shown in the cross-sectional view of FIG. 7A Will cause the heat sink 5 2 and The sheet 54 warps upward. At the same time, since the thermal expansion stress generated in the heat sink 52 is larger than that of the wafer 54, the amount of bending deformation will also be greater than that of the wafer 54 and the two will delaminate 61 (Delami / natl〇n), which may cause adhesion to the support member 5 丨 around the heat plate 54 under pressure or deform, or reduce the connection quality of the solder bumps 57 under the wafer 54, etc .; As shown in FIG. 7B, the angle view of the force diagram can be regarded as a plate (P 1 ate) that is subjected to two orthogonal moments Mm and the heart, that is, M丨, M 2 simulates the bending moment (Bending Moment) that the heat sink 5 2 is subjected to under heat. At this time, the direction of the upper surface 528 (as shown in the figure) will generate a maximum branch thermal stress σ !, σ
17154石夕品.ptd 第9頁 475 200423348 i、發明說明（4) (下表面52b為最大收縮熱應力），而產生如第7C圖所示之 翹曲變形（圖式中係略為放大該散熱片5 2之高度以加強說 朗），導致其中央部位向上突起，而與晶片5 4表面分離脫 層，同時，由於該散熱片5 2之四周均係與該環狀支撐件5 1 黏接，將令其產生一周圍拘束的邊界條件，導致該散熱片 5 2發生板殼挫曲（Buckle)之現象，且亦將使其上、下表面 5 2 a、5 2 b之四周與角緣位置受拘束而承受一最大應力。 反之，當該覆晶式球柵陣列封裝件5處於一降溫環境 時，此時熱膨脹係數較大之散熱片5 2所產生的收縮熱變形 m 較晶片5 4為大，並受該散熱片5 2之中央部位與晶片5 4 相互黏接拘束的影響而產生一彎曲，如第8 A圖之剖視圖所 示，將導致該散熱片5 2與晶片5 4向下翹曲，同時，由於該 散熱片5 2内所產生之熱收縮應力係較晶片5 4為大，故其彎 曲變形量亦將大於晶片54而對晶片54產生一下壓力，進而 可能導致晶片54受壓而破損62 (Crack)，形成電子元件之 破壞；此外，若自三維受力圖的角度觀之，可如第8 B圖所 示，將該處於增溫環境的散熱片5 2視為一受到兩正交力矩 Μ丨、Μ 2作用之板塊，亦即以Μ丨、Μ 2模擬該散熱片5 2降溫所 承受之彎曲力矩，此時，其上表面5 2 a之X、y方向（如圖所 將分別產生一最大收縮熱應力σ i、σ 2 (下表面5 2 b為 最大拉伸熱應力），而產生如第8C圖所示之麵曲變形（圖式 中係略為放大該散熱片5 2之高度以加強說明），導致該散 熱片5 2之中央向下壓陷，同時，由於該散熱片5 2之四周均 4與該環狀支撐件5 1黏接，將令其產生一周圍拘束的邊界17154 石 夕 品 .ptd Page 9 475 200423348 i. Description of the invention (4) (The lower surface 52b is the maximum shrinkage thermal stress), and warpage deformation occurs as shown in Figure 7C (the heat dissipation is slightly enlarged in the figure) The height of the sheet 5 2 is strengthened, causing its central part to protrude upward and separate and delaminate from the surface of the chip 5 4. At the same time, the periphery of the heat sink 5 2 is adhered to the annular support 5 1. Will cause it to have a bounded boundary condition around it, causing the heat sink 5 2 to buckle (shell), and will also cause the upper and lower surfaces of 5 2 a, 5 2 b around the corner and edge positions Be restrained and subject to a maximum stress. Conversely, when the flip-chip ball grid array package 5 is in a cooling environment, the shrinkage thermal deformation m generated by the heat sink 5 2 with a large thermal expansion coefficient at this time is larger than that of the wafer 54 and is affected by the heat sink 5 The central part of 2 and the chip 5 4 are adhered to each other to restrict the effect of a bend, as shown in the cross-sectional view of FIG. 8A, which will cause the heat sink 5 2 and the chip 5 4 to warp downward. At the same time, due to the heat dissipation The thermal shrinkage stress generated in the wafer 52 is larger than that of the wafer 54. Therefore, the amount of bending deformation will be greater than the wafer 54 and generate a pressure on the wafer 54, which may cause the wafer 54 to be compressed and damaged 62 (Crack). The destruction of the electronic component is formed. In addition, if viewed from the perspective of the three-dimensional force diagram, the heat sink 5 2 in the temperature-increasing environment can be regarded as one subject to two orthogonal moments M, as shown in FIG. 8B. The plate acting by Μ 2 is to simulate the bending moment with which the heat sink 5 2 is cooled by Μ 丨 and Μ 2. At this time, the X and y directions of the upper surface 5 2 a (as shown in the figure will produce a maximum Shrinkage thermal stresses σ i, σ 2 (the lower surface 5 2 b is the maximum tensile thermal stress), and The surface curvature as shown in FIG. 8C is deformed (the height of the heat sink 5 2 is slightly enlarged in the figure to strengthen the description), which causes the center of the heat sink 5 2 to be depressed downward. At the same time, due to the heat sink 5 Both sides 4 of 2 are glued to the ring-shaped support 5 1, which will cause a bounded boundary around it.
17154矽品.ptd 第10頁 200423348 五、發明說明（5) 條件，導致其上、下表面5 2 a、5 2 b之四周與角緣位置承受 一最大應力，並可能進而形成該散熱片5 2與支撐件5 1間之 脫層分離。 此外，前述因溫度改變所致之熱應力如無法順利釋 放，即便其未於測試過程中產生諸如前述之各種結構破 壞，亦可能於該散熱片5 2上應力最大處，亦即與支撐件5 1 黏接之環狀外圍表面，產生一殘餘應力（R e s i d u a 1 Stress)，進而可能於後續溫度循環測試或電子元件運作 時，加速材料疲勞（F a t i g u e )之可能性，而於該散熱片 5 2、晶片5 4或支撐件5 1的接合處產生延伸裂缝，破壞該封 裝件5的結構組成。 再者，對習知球柵式陣列封裝技術而言，為顧及製程 上的特殊用途，亦有部分於該散熱片開孔之封裝結構設 計，例> 美國專利第5，9 0 9，0 5 7號專利，其係於該晶片上 之散熱片開設複數個孔洞，以作為後續填膠製程之入口， 惟其孔洞並非開設於該散熱片上應力最大之位置，且為使 填膠速度易於控制，所開設之孔洞口徑勢必不可過大，故 該孔洞設計非但無法解決前述的熱應力問題，反而可能因： 其孔洞口徑過小，而於孔洞周圍之應力不連續點產生應力 集中（Stress Concentration)現象，進而加速封裝結構之 破壞。 同時，美國專利第5，9 9 8，2 4 2號專利亦提出一封裝結 構，係於散熱片上開設一小孔以連接外加之真空泵浦 (Vacuum Pump)，並藉其作用而維持晶片周圍的真空環17154 硅 品 .ptd Page 10 200423348 V. Description of the invention (5) The conditions that cause the upper and lower surfaces 5 2 a, 5 2 b around the corner and the location of the corner edge to bear a maximum stress, and may form the heat sink 5 Delamination and separation between 2 and support 51. In addition, if the aforementioned thermal stress due to temperature change cannot be smoothly released, even if it does not cause various structural damage such as the aforementioned during the test, it may also be the place where the stress on the heat sink 5 2 is the largest, that is, with the support 5 1 The bonded peripheral surface produces a residual stress (Residua 1 Stress), which may further accelerate the possibility of material fatigue during subsequent temperature cycle tests or electronic component operations, and the heat sink 5 2. An extension crack is generated at the joint of the wafer 54 or the support 51, and the structural composition of the package 5 is destroyed. Furthermore, for the conventional ball grid array packaging technology, in order to take into account the special application in the manufacturing process, there are also some packaging structure designs in the openings of the heat sink. Examples > US Patent No. 5,9 0 9,0 5 7 Patent No., which consists of a plurality of holes in the heat sink on the chip as the entrance of the subsequent filling process, but the holes are not opened in the position where the stress on the heat sink is the greatest, and in order to make the filling speed easy to control, The hole diameter of the hole must not be too large, so the hole design not only cannot solve the aforementioned thermal stress problem, but may be caused by: The hole diameter is too small, and the stress discontinuity around the hole will cause stress concentration (Stress Concentration) phenomenon, which will accelerate the packaging. Structural destruction. At the same time, U.S. Patent No. 5,9,8,2,42 also proposed a packaging structure, which is to open a small hole in the heat sink to connect to the vacuum pump, and use it to maintain the surrounding area of the chip. Vacuum ring
17154石夕品.口七(1 第11頁 200423348 、五、發明說明（6) 境，惟此單一孔洞之設計亦同樣無法解決該散熱片上的熱 ^力問題，尤其當所配置之散熱片係與晶片相互黏接時， 4玄小孔周圍更可能產生應力集中所導致的破壞現象。 因此，综觀前述的習知封裝結構，可知不論其所採用 Λ散熱片接置方式為樹脂、膠帶、密封墊或相變化材料， 或者不論其係於該散熱片上開設用於填膠或抽真空之孔 Ί同，倘若無法將該散熱片於可靠度測試中所產生之熱應力 於測試過程即立即釋放，勢難以避免此一熱應力所致的材 料變形問題，進而亦難以阻絕諸如翹曲、挫曲、脫層、晶 壓及銲塊變形等品質問題，且也將加速長期使用後材 料疲勞破壞之可能性，而降低該類封裝件的可靠度、電性 與散熱效率。 是故，如何開發一種具有散熱片的半導體封裝件，以 令該散熱片接觸晶片而提昇散熱效率之時，復能同時兼顧 其熱應力之擴散問題，以避免該封裝件之材料翹曲、脫層 或晶片受4貝’確為此^一研究領域所需迫切解決之課題。 【内容】 因此，本發明之一目的即在於提供一種可於散熱片t 應力最大之位置釋放其應力的具有散熱片半導體封裝件。 鲁本發明之復一目的在於提供一種可減少晶片所受壓力 以避免晶片破損的具有散熱片之半導體封裝件。 本發明之另一目的在於提供一種可避免散熱片與晶片 間產生脫層的具有散熱片之半導體封裝件。 ' 本發明之再一目的在於提供一種可避免散熱片、晶片17154 Shi Xipin. Mouth Seven (1 Page 11 200423348, V. Invention Description (6) environment, but the design of a single hole also cannot solve the thermal problem on the heat sink, especially when the heat sink is configured. When it is adhered to the chip, the damage phenomenon caused by stress concentration is more likely to occur around the 4 holes. Therefore, looking at the foregoing conventional packaging structure, it can be seen that regardless of the Λ heat sink connection method used is resin, tape, The gasket or phase change material, or whether it is a hole for filling or vacuuming on the heat sink is different. If the heat stress generated in the reliability test of the heat sink cannot be released immediately during the test It is difficult to avoid material deformation problems caused by this thermal stress, and it is also difficult to prevent quality problems such as warping, buckling, delamination, crystal pressure, and solder bump deformation, and it will also accelerate the fatigue damage of materials after long-term use. Possibility, which reduces the reliability, electrical properties, and heat dissipation efficiency of this type of package. Therefore, how to develop a semiconductor package with a heat sink so that the heat sink contacts the crystal When improving the heat dissipation efficiency, the compound energy also takes into account the diffusion of thermal stress at the same time to avoid warping, delamination or wafer damage of the package material. This is an urgent problem in this research field. [Content] Therefore, one object of the present invention is to provide a semiconductor package with a heat sink capable of releasing the stress of the heat sink t at the position where the stress of the heat sink t is the greatest. Another object of the present invention is to provide a method of reducing the stress on the wafer. A semiconductor package with a heat sink to avoid chip breakage. Another object of the present invention is to provide a semiconductor package with a heat sink that can avoid delamination between the heat sink and the wafer. 'Another object of the present invention is to provide A kind of avoidable heat sink and chip
17154矽品.ptd 第12頁 200423348 五、發明說明（7) 與基板發生翹曲變形的具有散熱片之半導體封裝件。 本發明之又一目的在於提供一種可確保銲塊連接品質 的具有散熱片之半導體封裝件。 為達前述及其他目的，本發明所提供之具散熱片之半 導體封裝件，係包括：基板，係具有一第一表面與一相對 之第二表面；至少一晶片，係具有一第一表面與一相對之 第二表面，並以其第二表面設置於該基板之第一表面上且 電性連接至該基板；至少一支撐件，係設置於該基板之第 一表面上；散熱片，係設置於該支撐件上，以令該晶片位 於該散熱片與支撐件所定義而成之圍置空間中，並令該晶 片之第一表面與該散熱片接觸，其中，該散熱片各邊連接 之角緣處之中的至少一組相互對稱位置，係分別開設有可 貫穿該散熱片之鏤空部，以藉該鏤空部釋放該散熱片之應 力；以及多數銲球，係植接於該基板之第二表面上。 該散熱片亦可設計成具有一平坦部與自該平坦部而朝 該基板方向延伸的支撐部，以藉該散熱片之支撐部取代該 支撐件，而令該支撐部設置於該基板之第一表面上，使該 晶片位於該平坦部與支撐部所定義而成之圍置空間中，並 令該晶片之第一表面與該平坦部接觸，同時，該平坦部各 邊連接之角緣處之中的至少一組相互對稱位置，亦分別開 設有可貫穿該平坦部之鏤空部。 前述之鏤空部係為一具有足夠鏤空面積的鏤空孔槽， 其係開設於該散熱片上之表面或其平坦部之各邊連接的角 緣處。為達至較佳的應力釋放功效，其開設位置係相互對17154 silicon product.ptd page 12 200423348 V. Description of the invention (7) A semiconductor package with a heat sink that is warped and deformed with the substrate. Yet another object of the present invention is to provide a semiconductor package having a heat sink capable of ensuring the quality of solder bump connection. In order to achieve the foregoing and other objectives, a semiconductor package with a heat sink provided by the present invention includes: a substrate having a first surface and an opposite second surface; and at least one wafer having a first surface and An opposite second surface, and the second surface is disposed on the first surface of the substrate and is electrically connected to the substrate; at least one support member is disposed on the first surface of the substrate; the heat sink is It is arranged on the support so that the chip is located in the surrounding space defined by the heat sink and the support, and the first surface of the chip is in contact with the heat sink, wherein the sides of the heat sink are connected At least one group of mutually symmetrical positions in the corner edges is provided with a hollow portion that can penetrate the heat sink to release the stress of the heat sink by the hollow portion; and most solder balls are planted on the substrate. On the second surface. The heat sink may also be designed to have a flat portion and a support portion extending from the flat portion toward the substrate. The support portion of the heat sink is used to replace the support member, and the support portion is provided on the first portion of the substrate. On one surface, the chip is positioned in a surrounding space defined by the flat portion and the support portion, and the first surface of the wafer is brought into contact with the flat portion, and at the same time, the corner edges connecting the sides of the flat portion At least one of the groups is symmetrical to each other, and a hollow portion is formed respectively through the flat portion. The aforementioned hollow portion is a hollow hole slot with a sufficient hollow area, which is opened at the corner of the surface of the heat sink or the sides connected by the flat portions thereof. In order to achieve better stress relief effect, the opening positions are opposite to each other.
17154矽品.ptd 第13頁 i77 1五、發明說明（8) 拜，同時復具有一足夠大的開 應力可進行一均勻且有效。®積，以令該散熱片上之 ' 本發明即係利用該複數^衝釋放。 於溫度變化之環境而產生熱蹲二孔槽，以於該封裝件處 孔槽釋放其熱應力，並緩和' ς' f Z :藉由該貫穿散熱片之 散熱片與支撐件接觸之拙A " …、片之彎曲熱變形；對該 於其應力產生處係鄰近於兮 ^ 生的熱應力而言，由 於應力產生後即快速釋访 ^ ’故可藉此一孔槽設計而 卞从’並今兮座上 對該散熱片與晶片接觸之中 Μ應力無法繼續擴散，而 言(·則可於其擴散至該散熱，if ^區域所產生的熱應力而 避免該散熱片與晶片的變^。 邊角緣之孔槽時釋放，以 因此，本發明之具散埶 於例如覆晶式球柵陣列封裝 ^牛V體封裝件，即可運用 熱片直接接觸晶片以提昇^等封裝技術中，以當將該散 而釋放熱應力並阻止其擴^〔，效率時，藉由該孔槽設計 如麵曲、脫層、晶片受損、g從而可避免該封裝件產生諸 結構問題。 貝、輝塊破壞或材料疲勞等習知的 【實施方式】 第1 Α圖係為本發明之| ^ 嫌例剖視圖，其係為―；2熱片，導體封裝件的較佳 (FCBGA)，包括一作為曰f BB式球柵陣列封裝件1 1 Π ρ, Λθ ,Α 1 ο^ρ, 日承载件（c h i P c a r r i e r )之基板 10’以if塊12¾性連接至基板1Q且接置於基板1()之第一表 面l〇a上的晶片H，接置於該基板1〇之第一表面ι〇&的環狀 支撐件20 (Stlffener Ring)’接置於該環狀支撐件2〇與17154 silicon product. Ptd page 13 i77 1 5. Description of the invention (8) worship, while having a large enough opening stress to perform a uniform and effective. ® product, so that the present invention on the heat sink is released using the plurality of punches. A thermal squatting two-hole slot is generated in a temperature-changing environment, so that the hole slot at the package releases its thermal stress, and alleviates 'ς' f Z: the contact between the heat sink through the heat sink and the support A "…, the bending thermal deformation of the sheet; for the thermal stress that is adjacent to the place where the stress is generated, because the stress is released immediately after the stress is generated ^ 'this can be followed by a slot design 'And now the M stress on the heat sink in contact with the chip cannot continue to spread, in terms of (·, it can be diffused to the heat dissipation, the thermal stress generated in the if ^ area to avoid the heat sink and the chip ^. The holes and corners of the corners are released when they are scattered, so that the present invention can be dispersed in, for example, a flip-chip ball grid array package ^ cattle V-body package, which can use a hot sheet to directly contact the chip to enhance the package. In the technology, when the thermal stress is released and the expansion is prevented, the hole and groove design such as surface curvature, delamination, wafer damage, and g can be used to avoid structural problems of the package. 。 Shell, glow block failure or material fatigue 】 Figure 1 Α is the cross-sectional view of the example of the present invention, which is ―; 2 thermal sheet, conductor package is better (FCBGA), including a f BB ball grid array package 1 1 Π ρ, Λθ, Α 1 ο ^ ρ, the substrate 10 'of the chi P carrier is connected to the substrate 1Q with an if block 12¾ and is connected to the wafer H on the first surface 10a of the substrate 1 (). A ring support 20 (Stlffener Ring) connected to the first surface of the substrate 10 and a ring support 20 connected to the ring support 20 and
1|讎 1111 __ΙΚΡΓ. iiSiiii $ 14頁 17154石夕品.口士(1 200423348 五、發明說明（9) 晶片1 1表面的散熱片3 0，以及植接於該基板1 〇之第二表面 1 0 b且與該多數銲塊1 2電性連接的多數銲球1 3 ;其中，該 散熱片3 0之周圍各邊連接角緣處係分別開設有貫穿該散熱 片3 0的鏤空部31a。 該散熱片3 0係選用一錢有錄的銅材料 (Ni-Plated-Cu)，將其製成具有約2 0至4 0密爾（mil)之厚 度的板狀散熱片3 0，並於其表面開設預定之鏤空部3 1 a， 此型材料與尺寸之散熱片30約可達至2至4 W/cm. k的熱傳 效率；同時，該環狀支撐件2 0所選用之材料係與該散熱片 3 0相同，以避免其於接合表面發生熱膨脹係數不匹配（CTE Mismatch)之翹曲或脫層情形，且由於該鑛鎳銅材料之熱 膨脹係數亦與習用之基板1 0材料（例如環氧樹脂、聚亞酿 胺、BT樹脂或FR4樹脂等）相近，故亦可令該環狀支撐件20 與基板.1 0間產生翹曲或脫層之可能性降至最低，其中，該 環狀支撐件2 0之高度約可設計成1 0至4 0密爾（m i 1 )，其數 值可視晶片1 1之厚度或配置層數而定。 第1 B圖即為前述散熱片3 0之上視圖，本實施例之散熱 片係為一方形散熱片3 0，其虛線所示分別為該晶片接置於 該散熱片之外緣位置1 1 ’、以及該圍置成方框區域的環狀 支撐件2 0接置於該散熱片3 0之内緣位置2 0 ’，且該環狀支 撐件2 0之相對外緣係與該散熱片3 0的外緣相互對齊；其 中，圖示之鏤空部3 1 a即為本發明中用以釋放應力的應力 釋放孔槽，其係分別開設於該散熱片3 0上相互對稱的四邊 連接角緣處，且並未與該環狀支撐件2 0接觸，以發揮其應1 | 雠 1111 __ΙΚΡΓ. IiSiiii $ 14 p.17154 Shi Xipin. Mouth (1 200423348 V. Description of Invention (9) The heat sink 3 0 on the surface of the wafer 1 1 and the second surface 1 implanted on the substrate 1 0 0 b and a plurality of solder balls 13 which are electrically connected to the plurality of solder bumps 12; wherein, at the connection corner edges of the sides around the heat sink 30, hollow portions 31a penetrating the heat sink 30 are respectively provided. The heat sink 30 is made of a well-known copper material (Ni-Plated-Cu), and is made into a plate-shaped heat sink 30 having a thickness of about 20 to 40 mils. A predetermined hollow portion 3 1 a is formed on the surface, and the heat transfer efficiency of this type of material and the size of the heat sink 30 can reach about 2 to 4 W / cm. K; at the same time, the ring-shaped support member 20 is selected from materials It is the same as the heat sink 30, in order to avoid warping or delamination of the thermal expansion coefficient mismatch (CTE Mismatch) on the joint surface, and because the thermal expansion coefficient of the mineral nickel copper material is also the same as the conventional substrate 10 material (Such as epoxy resin, polyurethane, BT resin or FR4 resin, etc.) are similar, so the ring-shaped support member 20 and the substrate can also be made. The possibility of warping or delamination is minimized. The height of the ring-shaped support 20 can be designed to be about 10 to 40 mil (mi 1), and the value can be determined by the thickness or configuration of the wafer 1 1. The number of layers is determined. Figure 1B is the top view of the aforementioned heat sink 30. The heat sink of this embodiment is a square heat sink 30, and the dashed lines show the chip connected to the heat sink respectively. The outer edge position 1 1 ′ and the ring-shaped support member 20 surrounded by the frame area are connected to the inner edge position 2 0 ′ of the heat sink 30, and the relative outer edge of the ring-shaped support member 20 is It is aligned with the outer edge of the heat sink 30. Among them, the hollow part 3a shown in the figure is a stress relief hole groove for releasing stress in the present invention, which is respectively opened on the heat sink 30. The symmetrical four sides are connected at the corner edges and are not in contact with the ring-shaped support member 20 to exert its application.
17154石夕品· ptd 第15頁 20042334817154 Shi Xipin · ptd Page 15 200423348
200423348 五、發明說明（11) 低，即可如第2 B圖所示，減緩其翹曲變形程度，同時，亦 不致形成該散熱片3 0與晶片1 1之分離或銲塊1 2連接品質下 降等相關問題，也不致令該熱應力轉變成累積於該散熱片 3 0中的殘餘應力。 此外，當該封裝件1處於一降溫環境時，雖亦具有一 向下麵曲之趨勢，惟造成其勉曲之收縮熱應力亦同樣可於 延伸至四角緣時，藉由該應力釋放孔槽3 1 a而自然釋放， 使得分布於該散熱片3 0上之熱應力大幅降低，而不致導致 晶片1 1受壓或該散熱片3 0與環狀支撐件2 0脫層之問題，也 不致有因殘餘應力所形成的材料疲勞問題，其功效與前述 之增溫示例相同，故不再另以圖式說明之。 本發明中開設於該散熱片3 0周圍的應力釋放孔槽3 1 a 並非僅限於前述較佳實施例之形狀，一般而言，僅需於鄰 近該散.熱片3 0拘束區域的位置開設複數個相互對稱且具有 適當面積的孔槽即可，例如第3 A、3 B、3 C、3 D圖所示之其 他實施例，係於該散熱片3 0各邊連接之角緣位置，分別開 設具有直角三角形3 1 b、對齊於該支撐件内緣直角之方形 3 1 c、與該支撐件内緣直角成一傾斜之方形3 1 d、圓弧形a 3 1 e等各種形狀的應力釋放孔槽，則亦可收相同之功效。 因此，根據前述各實施例可知，該散熱片3 0上所開設 之鏤空孔槽的形狀、位置、甚至數量並無一定之設計限 制，僅需令其貫穿該散熱片3 0上未與晶片1 1接觸之對稱分 布位置、同時亦具有一足夠大的鏤空面積即可；此外，一 般而言，當開設於該散熱片3 0上之孔槽數目愈多或其鏤空200423348 V. Description of the invention (11) Low, that is, as shown in Fig. 2B, the degree of warpage and deformation can be slowed down, and at the same time, the separation of the heat sink 30 and the wafer 11 or the connection quality of the solder bump 12 cannot be formed. Relevant problems such as descent will not cause the thermal stress to be converted into residual stress accumulated in the heat sink 30. In addition, when the package 1 is in a temperature-lowering environment, although it also has a tendency to bend downward, the shrinkage thermal stress that causes it to flex can also be extended to the four corner edges, and the holes and grooves 3 1 are released by the stress. a and natural release, so that the thermal stress distributed on the heat sink 30 is greatly reduced, without causing the problem that the wafer 11 is pressed or the heat sink 30 is delaminated from the ring-shaped support member 20, and there is no cause. The material fatigue problem caused by the residual stress has the same effect as the aforementioned temperature increasing example, so it will not be described in other figures. In the present invention, the stress relief holes 3 1 a provided around the heat sink 30 are not limited to the shape of the foregoing preferred embodiment, and generally, only need to be opened at a position adjacent to the heat sink 30. A plurality of holes and grooves that are symmetrical to each other and have an appropriate area may be used. For example, other embodiments shown in Figures 3 A, 3 B, 3 C, and 3 D are located at the corner edges of the heat sink 30, Stresses of various shapes including a right-angled triangle 3 1 b, a square 3 1 c aligned with the right angle of the inner edge of the support, a square 3 1 d inclined at an angle to the right angle of the support, and a circular a 3 1 e The same effect can be obtained by releasing the slot. Therefore, according to the foregoing embodiments, it can be known that the shape, position, and even the number of the hollow holes formed on the heat sink 30 are not limited in design. It only needs to pass through the heat sink 30 and the chip 1 1 The symmetrically distributed position of the contact can also have a sufficiently large hollow area; in addition, generally speaking, when the number of holes and grooves opened on the heat sink 30 is larger, or the hollow
17154石夕品.ptd 第17頁 20042334817154 Shi Xipin.ptd Page 17 200423348
200423348 五、發明說明（13) ^Ϊ 5 ’、如第4 F圖所示，於該基板1 0之下表面1 〇嫩接 <夕 ^球13 ’以藉由貫穿該基板1 0之多數導電貫孔 义性連接該鲜球1 3與晶片1 1，而使晶片1 1可藉由該 夕數I干球1 3而電性读拉 ^包肛運接至外界之電路板。 大 而由於5亥散熱片3 0上係開設有該應力釋放孔槽3 1 a， ^ ^ ’違散熱片3 0與環狀支撐件2 〇所圍置之容置空間4 4係 叮藉由。亥複數個孔槽3 1 a而與外界連通，故前述第4 d圖之 底部填膠（Underf i 1 1)製程亦可於該散熱片30接置完成後 才進行’亦即以該應力釋放孔槽3 1 a作為填膠之入口 (Access) ’而於該熱固性樹脂材料進入該容置空間44後充 填於各輝塊1 2之間，可另收提昇該封裝件1量產效率之功 效0 此外’前揭實施例之設計均係為一平板型散熱片3 〇， 並將该散熱片3 0接置於基板1 〇上之環狀支撐件2 〇而使其與 該晶片1 1之非作用表面丨丨b接觸，惟本發明之半導體封裝 件1中’亦可減省該環狀支撐件2 〇之設計，而直接將該散 熱片32設計成具有一平坦部33與自該平坦部33而朝該基板 1。0方向延伸的環狀支撐部3 4，而使該平坦部3 3與該環狀支 樓部34—體成型，以如第5圖所示藉該支撐部34而將該散 熱片3 2。又置於基板1 〇之表面上，並令該晶片1 1位於該平坦 4 3 3與支撐部3 4所定義而成之容置空間3 5中，以使該晶片 1 1之非作用表面1 1 b與該平坦部3 3以一導熱膠4 3黏接；其 中’該平坦部33上係同樣開設有可貫穿該散熱片3〇之應力 釋放孔槽3 1 a，而同樣可於溫度環境變化，而使該散熱片200423348 V. Description of the invention (13) ^ Ϊ 5 ', as shown in Fig. 4F, the bottom surface 10 of the substrate 10 is tenderly connected with < the ball 13 ' to pass through a majority of 10 of the substrate The conductive vias connect the fresh ball 13 and the wafer 11 in a meaningful way, so that the wafer 11 can be electrically connected to the external circuit board by the electric number I dry ball 13. Because the stress relief hole groove 3 1 a is provided on the heat sink 30, the heat sink 30 is surrounded by the heat sink 30 and the ring-shaped support member 40. . There are multiple holes 3 1 a in communication with the outside world, so the underfill (Underf i 1 1) process in the bottom of Figure 4 d can also be performed after the heat sink 30 is placed, that is, the stress is released. The hole 3 1 a is used as the access (filling) of the glue filling. After the thermosetting resin material enters the accommodation space 44 and is filled between the glow blocks 12, it can additionally receive the effect of improving the mass production efficiency of the package 1. 0 In addition, the design of the previously disclosed embodiments is a flat plate heat sink 3 0, and the heat sink 30 is connected to a ring-shaped support member 2 0 on the substrate 1 0 to make it and the wafer 1 1 Non-active surface 丨 丨 b contact, but in the semiconductor package 1 of the present invention, the design of the ring-shaped support member 20 can also be omitted, and the heat sink 32 can be directly designed to have a flat portion 33 and the flat portion 33. The support portion 34 is an annular support portion 34 extending in the direction of the substrate 1.0, and the flat portion 33 and the annular branch portion 34 are integrally formed to borrow the support portion 34 as shown in FIG. 5. And the heat sink 3 2. It is also placed on the surface of the substrate 10, and the wafer 11 is located in an accommodation space 3 5 defined by the flat 4 3 3 and the support portion 3 4 so that the non-active surface 1 of the wafer 1 1 1 b is bonded to the flat portion 33 with a thermally conductive adhesive 43; wherein the flat portion 33 is also provided with a stress relief hole 3 1 a that can penetrate the heat sink 30, and can also be used in a temperature environment. Change while making the heat sink
200423348 ’五、發明說明（14) ^ ^ 30與晶片U黏接之部位產生熱應力時，藉該應力釋放孔槽 3 la釋放並阻絕該熱應力之擴散，亦可達至前述之本發明 功效。 本發明之具散熱片半導體封裝件Ρ其散熱片30之形 I並非僅如前述實施例所示為一方形，其形狀可視設計者 之封裝需求而定，而該散熱片30上所開設之應力釋放孔槽 的位置而形狀與數量亦4隨該散熱片30之形狀而隨之變 更；此外，前述實施例中所採之環狀支撐件20係為一圍置 成方形框的支撐件，惟其設計亦同樣有諸多選擇，且亦不 p#環狀設計，僅需達至接設於該基板1 〇上而可支撐該散 熱片3 0之功能即可。 綜上所述’本發明之具政熱片半導體封裝件，確具有 可於散熱片中應力最大之位置釋放其應力的功效，同時， 復可減f少晶片所受壓力’並避免散熱片、晶片盥基板間產 生脫層或翹曲變形，進而可阻絕銲塊連接品 疲勞破壞等習知結構問題。 貝旁低A材抖 惟以上所述者，僅為本發明之具體 用以限定本發明之範圍，舉凡熟習此項技=去=，並非 揭^之精神與原理下所完成的一切等效改：發明所 之 痛-散熱片上開設不同形狀之孔槽：:乡例如 專利範圍所涵蓋。 仍應白由後述200423348 'Fifth, the description of the invention (14) ^ ^ 30 When thermal stress is generated at the location where the wafer U is bonded, the stress relief hole 3a is used to release and prevent the diffusion of the thermal stress, which can also achieve the aforementioned effect of the present invention. . In the semiconductor package with heat sink P of the present invention, the shape I of the heat sink 30 is not only a square shape as shown in the foregoing embodiment, and its shape can be determined by the packaging requirements of the designer. The stress created on the heat sink 30 The position, shape and number of the release slots are also changed according to the shape of the heat sink 30. In addition, the ring-shaped support member 20 adopted in the foregoing embodiment is a support member surrounded by a square frame. The design also has many options, and it is not a p # ring design. It only needs to be connected to the substrate 10 to support the function of the heat sink 30. In summary, 'The thermally conductive semiconductor package of the present invention does have the effect of releasing its stress at the most stressed position in the heat sink. At the same time, it can reduce the stress on the wafer' and avoid heat sinks, Delamination or warpage deformation occurs between the wafer and the substrate, which can prevent conventional structural problems such as fatigue damage of the solder joint connection. Beside low A material, but the above is only the specific use of the present invention to limit the scope of the present invention. For those who are familiar with this technique = go =, not all equivalent changes completed under the spirit and principles of ^ : Pain of the Invention-Different Shaped Holes and Slots on the Radiator:: For example, covered by patent scope. Still should be mentioned later
200423348 圖式簡單說明 【圖式簡單說明】 第1 A圖係本發明之具散熱片半導體封裝件的較佳實施 例剖視圖； 第1 B圖係第1 A圖所示之半導體封裝件的散熱片上視 圖； 第2 A及2 B圖係第1 A圖所示之半導體封裝件於增溫時的 熱應力施力示意圖； 第3 A至3 D圖係本發明之具散熱片半導體封裝件的散熱 片各實施例上視圖； 第4A至4F圖係本發明之具散熱片半導體封裝件的製法 流程圖； 第5圖係本發明之具散熱片半導體封裝件的另一實施 例剖視圖； 第.6 A至6 C圖係美國專利第5，9 0 9，0 5 6號專利之習知具 散熱片半導體封裝件的各種實施例剖視圖； 第7A圖係習知具散熱片半導體封裝件於增溫時的熱應 力施力示意圖； 第7B及7C圖係第7A圖所示之半導體封裝件的散熱片於: 增溫時之熱應力施力示意圖； 第8A圖係習知具散熱片半導體封裝件於降溫時的熱應 力施力示意圖；以及 第8B及8C圖係第8A圖所示之半導體封裝件的散熱片於 降溫時之熱應力施力不意圖。200423348 Brief description of the drawings [Simplified description of the drawings] Figure 1A is a cross-sectional view of a preferred embodiment of the semiconductor package with a heat sink of the present invention; Figure 1B is a view of the heat sink of the semiconductor package shown in Figure 1A Views; Figures 2A and 2B are schematic diagrams of the thermal stress exertion of the semiconductor package shown in Figure 1A during temperature increase; Figures 3A to 3D are heat dissipation of the semiconductor package with a heat sink of the present invention 4A to 4F are flowcharts of a method for manufacturing a semiconductor package with a heat sink according to the present invention; FIG. 5 is a cross-sectional view of another embodiment of the semiconductor package with a heat sink according to the present invention; A to 6C are cross-sectional views of various embodiments of the conventional heat sink semiconductor package of the US Pat. Figures 7B and 7C are the heat sinks of the semiconductor package shown in Figure 7A at: Figure 8A is a schematic diagram of the heat stresses of the semiconductor package when warming; Figure 8A is a conventional semiconductor package with heat sink Schematic diagram of thermal stress applied during cooling; 8B and 8C of the system of FIG. 8A as shown in FIG fins in the semiconductor package of the thermal stress is not intended to force cooling.
第21頁 17154^S.ptd 200423348Page 21 17154 ^ S.ptd 200423348
圖式簡單說明 ,1 半導體封裝件 10 基板 10a 基板第一表面 10b 基板第二表面 Μ 1 晶片 1 Γ 晶片外緣接置位 12 銲塊 13 銲球 .20 環狀支撐件 2(Γ 支撐件接置位置 30 散熱片 30a 散熱片上表面 '31a 應力釋放孔槽 31b 應力釋放孔槽 31c 應力釋放孔槽 31d 應力釋放孔槽 31e 應力釋放孔槽 32 散熱片 m 散熱片平坦部 34 散熱片支撐部 35 容置空間 41 膠黏劑 42 底部填膠材料 43 導熱膠 44 容置空間 5 半導體封裝件 50 泰板 51 支撐件 52 散熱片 52’ 散熱片固定部 52a 散熱片上表面 52b 散熱片下表面 53 樹脂層 54 晶片 55 相變化材料 56 屏障環 57 銲塊 61 脫層 Λ 晶片破損 d 孔槽寬度 M 力矩 σ 應力 17154石夕品.口七(1 第22頁Brief description of the figure, 1 semiconductor package 10 substrate 10a substrate first surface 10b substrate second surface M 1 wafer 1 Γ outer edge of the wafer is placed 12 solder bumps 13 solder balls. 20 ring-shaped support 2 (Γ support connected Position 30 Heat sink 30a Heat sink upper surface '31a Stress relief hole groove 31b Stress relief hole groove 31c Stress relief hole groove 31d Stress relief hole groove 31e Stress relief hole groove 32 Heat sink m Heat sink flat portion 34 Heat sink support portion 35 Capacity Placement space 41 Adhesive agent 42 Underfill material 43 Thermally conductive glue 44 Receiving space 5 Semiconductor package 50 Thai board 51 Support member 52 Heat sink 52 'Heat sink fixing portion 52a Heat sink upper surface 52b Heat sink lower surface 53 Resin layer 54 Wafer 55 Phase change material 56 Barrier ring 57 Welding pad 61 Delamination Λ Wafer damage d Slot width M Moment σ Stress 17154 Shi Xipin. Mouth seven (1 page 22
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092110108ATWI294673B (en) | 2003-04-30 | 2003-04-30 | Semiconductor package with heatsink |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092110108ATWI294673B (en) | 2003-04-30 | 2003-04-30 | Semiconductor package with heatsink |
| Publication Number | Publication Date |
|---|---|
| TW200423348Atrue TW200423348A (en) | 2004-11-01 |
| TWI294673B TWI294673B (en) | 2008-03-11 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092110108ATWI294673B (en) | 2003-04-30 | 2003-04-30 | Semiconductor package with heatsink |
| Country | Link |
|---|---|
| TW (1) | TWI294673B (en) |
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| US8575746B2 (en) | 2006-07-20 | 2013-11-05 | Samsung Electronics Co., Ltd. | Chip on flexible printed circuit type semiconductor package |
| TWI550804B (en)* | 2015-05-19 | 2016-09-21 | 力成科技股份有限公司 | Chip package structuer |
| CN111755340A (en)* | 2020-06-30 | 2020-10-09 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN112447608A (en)* | 2019-09-02 | 2021-03-05 | 矽品精密工业股份有限公司 | Electronic package, bearing structure thereof and manufacturing method thereof |
| CN112530885A (en)* | 2019-09-18 | 2021-03-19 | 江苏长电科技股份有限公司 | Chip packaging structure and packaging method |
| CN114937645A (en)* | 2022-05-17 | 2022-08-23 | 江苏长电科技股份有限公司 | Chip package structure |
| CN116569327A (en)* | 2020-12-09 | 2023-08-08 | 华为技术有限公司 | Encapsulation structure and preparation method thereof, electronic device |
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| TWI433618B (en) | 2012-02-08 | 2014-04-01 | Universal Scient Ind Shanghai | Stacked substrate structure |
| CN103779289A (en)* | 2012-10-18 | 2014-05-07 | 富葵精密组件(深圳)有限公司 | Connection substrate and package-on-package structure |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8575746B2 (en) | 2006-07-20 | 2013-11-05 | Samsung Electronics Co., Ltd. | Chip on flexible printed circuit type semiconductor package |
| TWI550804B (en)* | 2015-05-19 | 2016-09-21 | 力成科技股份有限公司 | Chip package structuer |
| CN112447608A (en)* | 2019-09-02 | 2021-03-05 | 矽品精密工业股份有限公司 | Electronic package, bearing structure thereof and manufacturing method thereof |
| TWI771610B (en)* | 2019-09-02 | 2022-07-21 | 矽品精密工業股份有限公司 | Electronic package, carrier structure and manufacturing method thereof |
| CN112447608B (en)* | 2019-09-02 | 2024-12-24 | 矽品精密工业股份有限公司 | Electronic packaging and its bearing structure and manufacturing method |
| CN112530885A (en)* | 2019-09-18 | 2021-03-19 | 江苏长电科技股份有限公司 | Chip packaging structure and packaging method |
| CN111755340A (en)* | 2020-06-30 | 2020-10-09 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN116569327A (en)* | 2020-12-09 | 2023-08-08 | 华为技术有限公司 | Encapsulation structure and preparation method thereof, electronic device |
| CN114937645A (en)* | 2022-05-17 | 2022-08-23 | 江苏长电科技股份有限公司 | Chip package structure |
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| TWI294673B (en) | 2008-03-11 |
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| Date | Code | Title | Description |
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| MK4A | Expiration of patent term of an invention patent |