TW200411832A - Method for manufacturing MOSFET with recessed channel - Google Patents

Abstract

A method for manufacturing a MOSFET with a recessed channel is described. To manufacture the MOSFET, a first sacrificial layer is formed on a semiconductor substrate first. Then, a source/drain is formed in the semiconductor substrate uncovered by the sacrificial layer. After a second sacrificial layer is formed on the source/drain, the first sacrificial layer and a portion of the semiconductor substrate under the first sacrificial layer are removed to form an opening. Thereafter, a sacrificial spacer is formed alongside an interior surface of the opening, a gate oxide layer is formed at the bottom of the opening, and a gate conductive layer is formed to fill the opening. The second sacrificial layer and the sacrificial spacer are removed. Finally, a lightly doped source/drain is formed in the semiconductor substrate.

Description

Translated fromChinese

200411832200411832

發明所屬之技術領域： 本發明係有關於一種金氧半場效應電晶體 (metal-oxide-semiconductor field effect transistor，MOSFET )之製造方法，特別是有關於—種且 凹陷通道（recessed channel )之金氧半場效應電， 製造方法。 m之 先前技術： 所有半導體元件的技術發展趨勢是往較小線寬來進化 的’金氧半場效應電晶體亦是如此，當線寬縮小至Q 1 或9Onm以下時，為了降低源/汲極電阻值，且避免短通道 效應（short channel effect)，並可進行自行對準5夕化 物製程（sal icide process )，遂發展了具有浮升源/沒 極（raised source/drain)或凹陷通道（recessed channel )之金氧半場效應電晶體之製造方法及其結構。 如第1圖所示，為繪示習知技術製作之具凹陷通道之金 氧半場效應電晶體之剖面結構示意圖，習知技術分別以兩 道光罩（或兩道以上）形成閘極與凹陷通道，然而，在線 寬縮小至0· 13mm或90nm以下時，則容易發生閘極12與凹 陷通道1 4無法對準的問題，因此使得金氧半場效應電晶體 效能變差’甚至使得金氧半場效應電晶體無法運作，習知The technical field to which the invention belongs: The present invention relates to a method for manufacturing a metal-oxide-semiconductor field effect transistor (MOSFET), and more particularly to a kind of metal oxide with a recessed channel Half-field effect electricity, manufacturing method. The previous technology of m: The technology development trend of all semiconductor devices is to evolve to smaller line widths. The same is true for 'metal oxide half field effect transistors. When the line width is reduced to less than Q 1 or 9 nm, in order to reduce the source / drain Resistance value, and avoid short channel effect, and can carry out self-aligned salicide process, then developed with raised source / drain or recessed channel ( A method for manufacturing a metal-oxygen half-field effect transistor (recessed channel) and its structure. As shown in Figure 1, a schematic cross-sectional structure diagram of a metal-oxygen half-field effect transistor with a recessed channel made by the conventional technique is shown. The conventional technique uses two photomasks (or more than two) to form a gate and a recessed channel. However, when the line width is reduced to 0.13mm or below 90nm, the problem of misalignment between the gate 12 and the recessed channel 14 is prone to occur, so that the performance of the gold-oxygen half-field effect transistor is worsened, or even the gold-oxygen half-field effect. Transistor does not work.

第7頁 200411832 發明說明（2) 技術之缺失由此可見一般。 發明内容： f於習知技術之缺失，本發明的目的就是在提供一種具 凹陷通道之金氧半場效應電晶體之製造方法，避免發生閘 極與凹陷通道無法對準的問題。 本發明的另一目的就是在提供一種具凹陷通道之金氧半 場=電晶體之製造方法，可以提昇金氧半場效應電晶體 效應電晶體之Lii i製氧半場 於-半‘ϊΐίτ: 先形成一第一犧牲層 3牲^半導體基材，再形成一第二犧牲層於源4: 移除第-犧牲層與其下方之部分半導體基材以 二一犧牲間隙壁於開孔側壁，开> 成-閉極介電 曰棍r1底°卩，形成一閘極導體層而填滿開孔，移除該第 =犧牲層與該犧牲間隙壁，最後，形極 於該半導體基材。 乜雜源/及極 本發明力製造之錢半場效應f晶體具有㈣通道杜 冓，且並不會發生閘極與凹陷通道無法對準的問題。 200411832Page 7 200411832 Description of the invention (2) The lack of technology can be seen from this. Summary of the Invention: In view of the lack of conventional technology, the purpose of the present invention is to provide a method for manufacturing a metal-oxygen half-field effect transistor with a recessed channel, so as to avoid the problem that the gate and the recessed channel cannot be aligned. Another object of the present invention is to provide a method for manufacturing a metal-oxygen half-field with a recessed channel = transistor, which can enhance the Lii i oxygen-making half-field of the metal-oxygen half-field effect transistor effect transistor at -half ': first forming a The first sacrificial layer 3 is a semiconductor substrate, and then a second sacrificial layer is formed at the source 4: The first sacrificial layer and a part of the semiconductor substrate below it are removed, and the sacrificial spacers on the sidewalls of the openings are opened. -The closed-electrode dielectric is formed at the bottom of the rod r1 to form a gate conductor layer to fill the openings, remove the first sacrificial layer and the sacrificial spacer, and finally, form a pole shape on the semiconductor substrate. Miscellaneous sources and poles The half-field effect f crystals produced by the present invention have a ㈣ channel, and the problem of misalignment between the gate and the recessed channel does not occur. 200411832

實施方式： 請參照第2A〜2L圖，為繪示本發明製作且凹陷 應電晶體之剖面結構流程示意圖1二之以f 、氧半％效應電晶體為例，說明本發明技術内容。、 f先’如第2A圖所示，先於具有一隔離區。之 ί材2』」P型:夕）上沉積一蝕刻終止層22與-第-犧牲層 隐雜；隔離區2 1可為習知技術形成之淺溝渠隔離區， ^區21之材質可為二氧化石夕，而㈣終止層。之材質可 :虱乳化矽或二氧化矽，第一犧牲層23之材質可為二氧化 ’、、:後第2 B圖巾’再圖案化第一犧牲層2 3，例如以微影 製程與蝕刻技術圖案化第一犧牲層。 第2^：圖中，於半導體基材2〇形成一源/汲極25。其中， 可如習知離子植入24技術摻雜磷或砷於半導體基材2〇，以 形成此源/汲極2 5。 第2D圖中，於未被覆蓋有第一犧牲層23之半導體基材20 上方填入一第二犧牲層2 6。例如可如習知技術先沉積第二 犧牲層26，再化學機械研磨第二犧牲層26而停止於第一犧Embodiments: Please refer to FIGS. 2A to 2L for a schematic flow chart of the cross-sectional structure of a recessed transistor manufactured and produced according to the present invention. The second is to take f and oxygen half-% effect transistors as examples to illustrate the technical content of the present invention. , F first ', as shown in Fig. 2A, before having an isolation region. "Material 2" "P-type: evening) an etch stop layer 22 and -first-sacrifice layer are deposited; the isolation region 21 can be a shallow trench isolation region formed by conventional techniques, and the material of region 21 can be On the eve of the dioxide, the plutonium terminates the layer. The material can be: lice emulsified silicon or silicon dioxide, and the material of the first sacrificial layer 23 can be dioxide, and the second sacrificial layer B can be used to pattern the first sacrificial layer 2 3, for example, by a lithography process and The etching technique patterns the first sacrificial layer. Figure 2 ^: In the figure, a source / drain electrode 25 is formed on the semiconductor substrate 20. The source / drain electrode 25 can be formed by doping phosphorus or arsenic on the semiconductor substrate 20 as in the conventional ion implantation 24 technique. In FIG. 2D, a second sacrificial layer 26 is filled on the semiconductor substrate 20 not covered with the first sacrificial layer 23. For example, the second sacrificial layer 26 can be deposited first as known in the art, and then the second sacrificial layer 26 is chemically and mechanically ground to stop at the first sacrificial layer.

200411832200411832

二犧牲層26之材質可為氮化 五、發明說明（4) 牲層23來予以達成。其中，第 石夕。 第2E圖中，移除第一犧牲 與部分半導體基材2〇，以形 刻技術移除來予以達成，移 決定凹陷通道之深度。 層23與其下方之姓刻終止層μ 成一開孔27。其中，可利用蝕 除部分半導體基材2〇之多募可 第2 F圖中，於以餘刻技術 蝕刻終止層2 2與部分半導體 化步驟，而於開孔2 7底部形 此二氧化石夕層之厚度為100A 之半導體基材20表面，因此 第2G圖中，於開孔27形成 底部形成一閘極氧化層3 〇。 式，可先於第二犧牲層26表 一二氧化矽層，再回蝕刻此 隙壁29。其中，可以熱氧化 佳者，閘極氧化層3 〇之厚度 移除第一犧牲層23與其下方之 基材20之後，可再進行一熱氧 成一 一氧化碎層2 8，較佳者， 。此步驟是為了修復經蝕刻後 ’此步驟並非絕對必要。 一犧牲間隙壁2 ^，並於開孔2 7 其中’形成犧牲間隙壁2 9之方 面與開孔27之側邊及底部沉積 二氧化石夕層，以形成此犧牲間 技術形成此閘極氧化層3 〇，較 為12〜70A。 第2H圖中，於開孔27中形成一閘極導體層31，接著，再 經由一離子植入技術摻雜磷或砷於閘極導體層3 1中。直 中’形成閘極導體層31之方式’可先於第二犧牲層2^面The material of the second sacrificial layer 26 may be nitrided. V. Description of the Invention (4) The animal layer 23 is used to achieve this. Among them, the first Shi Xi. In Fig. 2E, the first sacrifice and part of the semiconductor substrate 20 are removed, and the removal is performed by the etch technique, and the shift determines the depth of the recessed channel. The layer 23 forms an opening 27 with the termination layer μ under it. Among them, a part of the semiconductor substrate 20 can be etched. As shown in FIG. 2F, the stop layer 22 and a part of the semiconductorization step are etched by the remaining technique, and the dioxide is formed at the bottom of the opening 27. The thickness of the evening layer is 100A on the surface of the semiconductor substrate 20, so in FIG. 2G, a gate oxide layer 3 is formed at the bottom of the opening 27. For example, a silicon dioxide layer can be formed before the second sacrificial layer 26, and then the gap wall 29 can be etched back. Among them, those that can be thermally oxidized, after removing the first sacrificial layer 23 and the substrate 20 below the thickness of the gate oxide layer 30, a thermal oxygen can be further formed into an oxide fragment layer 28. The better, . This step is to repair the etched post. This step is not absolutely necessary. A sacrificial spacer 2 ^ is deposited on the side of the opening 2 7 where the sacrificial spacer 29 is formed and the side and bottom of the opening 27 are deposited to form the inter-sacrificial technique to form the gate oxide Layer 3 0, 12 ~ 70A. In FIG. 2H, a gate conductor layer 31 is formed in the opening 27, and then, the gate conductor layer 31 is doped with phosphorus or arsenic through an ion implantation technique. The method of “forming the gate conductor layer 31” may be before the second sacrificial layer 2 ^

第10頁 200411832Page 10 200411832

與開孔27中沉積一多晶矽& (未顯示於圖 此多晶矽層而停止於第二犧牲層2 6。 ’再回蝕刻 第2 I圖中，以蝕刻技術移除第二犧声 22與犧牲間隙壁29。若第二犧牲層26之^質為^刻終止層 可使用澄#刻方式，以含有熱鱗酸之钱刻液移二 層26。若蝕刻終止層22與犧牲間隙壁29之材質 > 犧牲 石夕，則可使用澄姓刻，*，以含有*氟酸之餘 刻終止層22與犧牲間隙壁29，或者亦可使用乾蝕 $ = 除蝕刻終止層22與犧牲間隙壁29 〇 ^ A抄 第2J圖中’於該半導體基材20形成一輕摻雜汲極 (lightly doped drain，LDD )區 32。其中，可如習知離 子植入33技術摻雜磷或砷於半導體基材2〇，以形成1輕捧 雜源/汲極3 2。當然，可於離子植入後再進行一快速加熱 回火（rapid thermal anneal, RTA )步驟，以修復經兩 次離子植入（第2 C圖與第2 J圖）被破壞之晶格結構。 第2K圖中，於閘極導體層31之側壁形成一矽化遮蔽間隙 壁34。其中，形成矽化遮蔽間隙壁34之方式可先沉積一遮 蔽層（未顯示於圖中），再回蝕刻此遮蔽層以形成此矽化 遮蔽間隙壁3 4，遮蔽層之材質可為二氧化矽或氮化矽。 最後，如第2L圖所示，為了降低閘極導體層31與源/汲A polycrystalline silicon is deposited in the opening 27 (not shown in the figure, and the polycrystalline silicon layer is stopped at the second sacrificial layer 26. 'Re-etch the second sacrificial figure 2I, and remove the second sacrificial sound 22 and the sacrificial by the etching technique. Spacer wall 29. If the quality of the second sacrificial layer 26 is an etch stop layer, the second layer 26 can be engraved with a scaly engraving method using the Cheng #etching method. If the etching stop layer 22 and the sacrificial spacer 29 are Material> For the sacrificial stone, you can use the engraving of Cheng, *, to stop the layer 22 and the sacrificial spacer 29 with * fluoric acid, or use dry etching $ = In addition to the etching stop layer 22 and the sacrificial spacer 29 〇 A in Figure 2J, 'a lightly doped drain (LDD) region 32 is formed on the semiconductor substrate 20. Among them, phosphorus or arsenic can be doped on the semiconductor substrate 20 as in the conventional ion implantation 33 technique. Semiconductor substrate 20 to form 1 light source / drain 32 2. Of course, a rapid thermal annealing (RTA) step can be performed after ion implantation to repair the ion implantation twice. (Fig. 2C and Fig. 2J), the damaged lattice structure is formed. In Fig. 2K, it is formed on the side wall of the gate conductor layer 31 A silicide shielding spacer 34. Among them, a method for forming the silicide shielding spacer 34 may be to deposit a shielding layer (not shown in the figure), and then etch back the shielding layer to form the silicide shielding spacer 34. The material can be silicon dioxide or silicon nitride. Finally, as shown in Figure 2L, in order to reduce the gate conductor layer 31 and the source / sink

第11頁 200411832 五、發明說明（6) 極25之阻值，以矽化遮蔽間隙壁34為遮罩進行自行對準石夕 化物（self-aligned silicide，salici.de)製程，以於 閘極導體層3 1表面與源/沒極2 5表面形成一金屬；ε夕化物層 3 5，金屬矽化物層3 5之材質可為矽化始、石夕化鎳或；g夕化 鈦，至此，則完成N型金氧半場效應電晶體之製作。 由於本發明僅以一道光罩定義出閘極區域（第2B圖）， 然後於此閘極區域形成開孔2 7 (並同時形成凹陷通道） (第2E圖），再於開孔27中形成閘極氧化層30與閘極導體 層31 (第2H圖），而非如習知技術分別以兩道光罩形成閘 極與凹陷通道，因此，本發明可避免發生閘極與凹陷通道 無法對準的問題。 而且，習知技術係單以微影製程與蝕刻技術就決定了閘 極寬度。然而，本發明形成開孔27 (第2£：圖）後，於開孔 27中形成犧牲間隙壁29 (第2(；圖），再於開孔27中形成閘 極導體層31 (第2H圖），最後移除犧牲間隙壁29 (第21圖 )而僅留下閘極導體層31。因此，本發明最初是藉由微影 製程與蝕刻技術形成開孔27寬度，而最後形成之閘極導體 層31 (或閘極）寬度則小於開孔27寬度，對於不斷往線寬 縮小進化的半導體技術而言，本發明相對於習知方式不需 要較高的微影製程與蝕刻技術的解析度，本發明相對於習 知方式在製程控制上較為簡易。 200411832 - —" μηημμμ 五、發明說明（7) _ 另外，習知技術是先進行第_ f 源/汲極，然後進行第-次快迷加 乂开技成輕摻雜 極侧邊形成間隙:壁後，再進行第二' 驟，接者於閘 汲極，最後進行第二次快速力形成源/ 係進行了兩次離子植入與兩次快火；：7技術Page 11 200411832 V. Description of the invention (6) The resistance value of pole 25 is self-aligned silicide (salici.de) process with silicified shielding gap 34 as a mask for the gate conductor A metal is formed on the surface of the layer 31 and the surface of the source / inverter 25; the material of the epsilon layer 35 and the metal silicide layer 35 may be silicidation, petrified nickel, or titanium; so far, then Completed the fabrication of N-type metal-oxide half-field effect transistor. Since the present invention only defines a gate region with a photomask (FIG. 2B), then an opening 27 (and a recessed channel) is formed in this gate region (FIG. 2E), and then formed in the opening 27 The gate oxide layer 30 and the gate conductor layer 31 (FIG. 2H), instead of using two photomasks to form the gate and the recessed channel as in the conventional technology, therefore, the present invention can prevent the gate and the recessed channel from being misaligned. The problem. Moreover, the conventional technique simply determines the gate width by lithography and etching techniques. However, according to the present invention, after the opening 27 (second: FIG. 2) is formed, a sacrificial spacer 29 (second (2; FIG.)) Is formed in the opening 27, and the gate conductor layer 31 (second 2H is formed in the opening 27). Figure), and finally the sacrificial spacer 29 (Figure 21) is removed and only the gate conductor layer 31 is left. Therefore, the present invention initially forms the width of the opening 27 by the lithography process and the etching technology, and finally the gate is formed. The width of the electrode conductor layer 31 (or gate) is smaller than the width of the opening 27. For the semiconductor technology that continues to shrink and evolve toward the line width, the present invention does not require a higher lithography process and etching technology than the conventional method. Compared with the conventional method, the present invention is relatively simple in terms of process control. 200411832-" μηημμμ V. Description of the Invention (7) _ In addition, the conventional technique is to first perform the _f source / drain, and then perform the- The second step is to add light to the side of the lightly doped electrode to form a gap: after the wall, perform the second step, then connect to the gate drain, and finally perform the second rapid force formation source / system for two ions. Implantation and Two Fast Fires: 7 Techniques

^月^行第一次離子植入24以形成源/汲：“、第】， 圖），接者於移除閘極導體層31 f„托、 （第2C 隙㈣（第㈣才“3第1犧牲間 =雜源/汲極32 (第2J圖），最後 ^成輕 ;驟因進行了兩次離子植入與-欠快= L in 行兩次快速加熱回火步驟，而本發：i 進仃一久快速加熱回火步驟，本發明相對於 區域因為進行快速加熱回火步驟而擴 比習去枯ΐ r在線寬縮小進化的半導體技術而言，、本發明 比S知技術較能避免短通道效應問題。 月 近幾年發展之矽覆絕緣層晶圓 ^Hrrinsulator，S0I) ’主要是在石夕晶圓下添 二ϊ 層’用來避免電氣效應，以降低電源消 曰圓技i τ = ΐ失’加快元件的處理速度，矽覆絕緣層 =固=可應用在需要較低電源消耗的設備上（如行動電 ί:二ί 因此’本發明之半導體基材20除了可以為- ::::卜，亦可以為-矽覆絕緣層晶圓。當半導體基材20 為夕覆絕緣層晶圓時，則可藉由移除部分半導體基材20 第13頁 200411832The first ion implantation 24 was performed to form a source / drain: ", section", figure), and then the gate conductor layer 31 f is removed, (the 2C gap (the first section is "3") The first sacrifice interval = heterogenous source / drain 32 (Figure 2J), and finally it becomes light; the reason is that the ion implantation was performed twice and-less fast = L in to perform two rapid heating and tempering steps. : I enters the rapid heating and tempering step for a long time. Compared with the semiconductor technology of line width reduction and evolution, the present invention is better than the known technology compared with the known technology in the area. Avoid short-channel effects. Silicon-coated insulating wafers developed in recent years ^ Hrrinsulator, S0I) 'Mainly add two layers of silicon under Shixi wafers' to avoid electrical effects and reduce power consumption i τ = loss' accelerates the processing speed of the component, silicon-clad insulation layer = solid = can be applied to equipment that requires lower power consumption (such as mobile power ί: 二 ί) Therefore, in addition to the semiconductor substrate 20 of the present invention can be -:::: Bu, can also be-silicon-clad insulation layer wafer. When the semiconductor substrate 20 is a silicon-clad insulation layer wafer , May be formed by removing portions of the semiconductor substrate 20 Page 13 200 411 832

第14頁 200411832 圖式簡單說明 本發明的較佳實施例於前述之說明文字中輔以下列圖形做 更詳細的闡述，其中： 第1圖為繪示習知技術製作之具凹陷通道之金氧半場效 應電晶體之剖面結構示意圖；以及 第2A〜2L圖為繪示本發明製作具凹陷通道之N型金氧半場 效應電晶體之剖面結構流程示意圖。 圖式標記說明·’ 1 0 半導體基材11 源/>及極 12閘極13間隙壁 1 4 凹陷通道 20半導體基材21隔離區 2 2蝕刻終止層2 3第一犧牲層 24離子植入25 源/汲極 · 2 6第二犧牲層2 7開孔 2 8二氧化矽層2 9犧牲間隙壁 30閘極氧化層31閘極導體層 3 2輕摻雜源/没極3 3 離子植入 34矽化遮蔽間隙壁35 金屬矽化物層Page 14 200411832 Schematic illustration of the preferred embodiment of the present invention is supplemented by the following figures in the preceding explanatory text for a more detailed explanation, where: Figure 1 shows the metal oxide with recessed channels made by conventional techniques Schematic diagram of the cross-sectional structure of a half-field effect transistor; and FIGS. 2A to 2L are schematic diagrams showing the cross-sectional structure of a N-type metal-oxygen half-field effect transistor with a recessed channel according to the present invention. Description of the drawing symbols' 1 0 semiconductor substrate 11 source / > and electrode 12 gate 13 gap wall 1 4 recessed channel 20 semiconductor substrate 21 isolation region 2 2 etch stop layer 2 3 first sacrificial layer 24 ion implantation 25 source / drain 2 6 second sacrificial layer 2 7 openings 2 8 silicon dioxide layer 2 9 sacrificial spacer 30 gate oxide layer 31 gate conductor layer 3 2 lightly doped source / main 3 3 ion implantation Into 34 silicide to shield the bulkhead 35 metal silicide layer

第15頁Page 15

Claims (1)

Translated fromChinese

200411832200411832申請專利範圍 1 製: = = = = :場效應電晶體之製造方*’該 第:、犧牲層於二半導體基材上方； 材； 原/汲極於未覆蓋有該第一犧牲層之該半導體基 形成:第二犧牲層於該源/汲極上方； 成：S3第一犧牲層與其下方之部分該半導體基材，以形 开=成一犧牲間隙壁於該開孔侧壁； 形成一閘極介電層於該開孔底部； 形成一閘極導體層而填滿該開孔； 移除該第二犧牲層與該犧牲間隙壁；以及 形成一輕摻雜源/汲極於該半導體基材。 2 曰如申請專利範圍第丨項之具凹陷通道之金氧半場效應電 曰曰體之製造方法，其中該半導體基材之材質選自矽晶圓與 石夕覆絕緣層晶圓群組之一。 曰如申請專利範圍第1項之具凹陷通道之金氧半場效應電 曰曰體之製造方法，其中形成該第一犧牲層於該半導體基材 上方之前，更包括形成一蝕刻終止層於該半導體基材上 方。 如申請專利範圍第3項之具凹陷通道之金氧半場效應電Patent application scope 1 system: = = = =: maker of field effect transistor * 'the first: the sacrificial layer is above the two semiconductor substrates; the material; the original / drain electrode is not covered by the first sacrificial layer Forming a semiconductor substrate: a second sacrificial layer is above the source / drain; forming: a first sacrificial layer of S3 and a portion of the semiconductor substrate below it, forming a sacrificial gap wall on the side wall of the opening; forming a gate A dielectric layer is formed at the bottom of the opening; a gate conductor layer is formed to fill the opening; the second sacrificial layer and the sacrificial spacer are removed; and a lightly doped source / drain is formed on the semiconductor substrate material. 2 The manufacturing method of a metal-oxygen half-field effect electric body with a recessed channel as described in the scope of the patent application, wherein the material of the semiconductor substrate is selected from the group consisting of a silicon wafer and a stone-covered insulating layer wafer . The manufacturing method of a metal-oxygen half-field effect electric body with a recessed channel as described in the first patent application scope, wherein before forming the first sacrificial layer over the semiconductor substrate, it further includes forming an etch stop layer on the semiconductor. Above the substrate. For example, the metal-oxygen half-field effect electricity with a recessed channel in the scope of patent application No. 3第16頁 200411832 六、申請專利範圍 ___ 晶體之製造方法，苴 與氮氧化矽群紐之：：y遠蝕刻終止層之材質選自二氧化矽 5 ·如申清專利範圍第^ 晶體之製造方法，复由之具凹陷通道之金氧半場效應電 該半導體基材，更移除該第一犧牲層與其下方之部分 止層。 括移除該第一犧牲層下方之該蝕刻終 6·如申請專利範圍第3項之具 晶體之製造方法，中 、之金乳+、效應電 壁，更包括移卜β ^移除a亥第一犧牲層與該犧牲間隙 土 叉已枯移除該蝕刻終止層。 7. 如申請專利範圍第丄項之具凹陷通道之金氧 晶體之製造方法，1中吁筮植从a 牛努效應電 其中δ亥第一犧牲層之材質為二氧化矽。 8. 如申請專利範圍第η之具凹陷通道之金氧 晶體之製造方法’其中該第二犧牲層之材質為氮化矽' 9. 如申請專利範圍第1項之具凹陷通道之金氧 晶體之，法，其中以姓刻技術移除該第一犧:效二電复 下方之部分該半導體基材，其之後更包括有— ^ 而於該開孔底部形成一二氧化矽層之步驟。 …、乳化 場效應電 1 0·如申請專利範圍第1項之具凹陷通道之金氣半 I麵Page 16 200411832 VI. Patent application scope ___ The method of manufacturing crystals, 苴 and silicon oxynitride group: y The material of the far-etching stop layer is selected from silicon dioxide 5 · Such as applying for the patent scope of ^ crystal manufacturing In the method, a metal-oxygen half field effect with a recessed channel is applied to the semiconductor substrate, and the first sacrificial layer and a part of the stop layer below the semiconductor layer are removed. Including removing the etching finish under the first sacrificial layer 6. If there is a crystalline manufacturing method in item 3 of the scope of the patent application, the medium, the golden milk +, the effect electric wall, and the moving β ^ remove a Hai The first sacrificial layer and the sacrificial gap earth fork have dried up to remove the etch stop layer. 7. For the method for manufacturing a metal oxide crystal with a recessed channel in item (1) of the scope of the patent application, 1 calls for the plant to produce a Niu effect effect, wherein the material of the first sacrificial layer of δH is silicon dioxide. 8. For example, the method for manufacturing a metal oxide crystal with a recessed channel in the scope of patent application 'wherein the material of the second sacrificial layer is silicon nitride' 9. As the metal oxide crystal with a recessed channel in the scope of patent application No. 1 In other words, the first sacrificial technique is used to remove the first sacrifice: a part of the semiconductor substrate under the second electrode is compounded, and then a step of forming a silicon dioxide layer at the bottom of the opening is further included. …, Emulsification, field-effect electricity 1 0, such as the gold gas half I surface with recessed channels in the scope of patent application No. 1第17頁 200411832 六、申請專利範圍 驟其中形成該犧牲間隙壁於該開孔侧壁’ 5亥第二犧牲層表面與該開孔之側邊 沉積一二氧化石夕層於 及底部；以及 回蝕刻該一氧化矽層，以形成該犧牲間隙壁 11申制請Λ利範圍第1項之具凹陷通道之金氧半場效應電 晶體之製如·方法，其中形成該輕摻雜源/汲極於該半導體 基材之後，更包括有一快速加熱回火步驟。 12.2H專利範圍第1項之具凹陷通道之金氧半場效應電 晶體之IL把方法，其中形成該輕摻雜源/汲極於該半導體 基材之後，更至少包括下列步驟： 形成一矽化遮蔽間隙壁於該閘極導體層之侧壁；以及 形成一金屬矽化物層於該閘極導體層表面與該汲 表面。 13·如申請專利範圍第12項之具凹陷通道之金氧半應 電晶體之製造方法，其中該遮蔽層之材質選自二 矽^ 氮化矽群組之一。 ％ 14·如申請專利範圍第12項之具凹陷通道之金氧半場效應 電晶體之製造方法，其令該金屬矽化物層之材質選自矽化 鈷、梦化鎳與矽化鈦群組之一。 第18頁 200411832 六、申請專利範圍Page 17 200411832 Sixth, the scope of the patent application is that the sacrificial spacer is formed on the side wall of the opening, and the second sacrificial layer on the surface of the opening and the side of the opening are deposited with a layer of dioxide on the bottom; and The silicon monoxide layer is etched to form the sacrificial spacer 11. The method for manufacturing a metal-oxygen half-field effect transistor with a recessed channel according to item 1 in the first range is as follows. The lightly doped source / drain is formed. After the semiconductor substrate, a rapid heating and tempering step is further included. 12.1H The method of IL of a metal-oxygen half field effect transistor with a recessed channel in the first item of the patent scope, wherein after forming the lightly doped source / drain on the semiconductor substrate, the method further includes at least the following steps: forming a silicide mask The spacer wall is on the side wall of the gate conductor layer; and a metal silicide layer is formed on the surface of the gate conductor layer and the drain surface. 13. The method for manufacturing a metal-oxygen semi-resistive transistor with a recessed channel according to item 12 of the application, wherein the material of the shielding layer is selected from one of the two silicon ^ silicon nitride groups. % 14. According to the method for manufacturing a metal-oxygen half-field effect transistor with a recessed channel according to item 12 of the application, the material of the metal silicide layer is selected from the group consisting of cobalt silicide, dream nickel and titanium silicide. Page 18 200411832 VI. Scope of patent application1 5 · —種自我對準閘極之製造方法，係應用於形成—且 陷通道之金氧半場效應電晶體，該製造方法至虹、凹 步驟·· · 夕匕括下列 形成一圖案化第一犧牲層於一半導體基材上方， 一閘極位置； 乂疋義 形成一圖案化第二犧牲層於未覆蓋有該圖案化第一 層之该半導體基材上方，以定義一源/汲極位置； 移除該圖案化第一犧牲層與下方之部份該半導體基材， 以形成一開孔； 土 形成一犧牲間隙壁於該開孔側壁； 形成一閘極介電層於該開孔底部； 形成一閘極導體層而填滿該開孔；以及 移除#亥圖案化第二犧牲層與該犧牲間隙壁。 =·如申請專利範圍第15項之自我對準閘極之製造方法， :該半導體基材之材質選自矽晶圓與矽覆絕緣層晶圓群 复·如申請專利範圍第丨5項之自我對準閘極之製造方法， 更、形成該圖案化第一犧牲層於該半導體基材上方之前， 匕括形成一蝕刻終止層於該半導體基材上方。 •如申請專利範圍第1 7項之自我對準閘極之製造方法，1 ··· A kind of self-aligned gate electrode manufacturing method, which is used to form a gold-oxygen half-field effect transistor with a trapped channel. The manufacturing method goes to the rainbow and concave steps. A sacrificial layer over a semiconductor substrate, a gate position; meaning a patterned second sacrificial layer over the semiconductor substrate not covered with the patterned first layer to define a source / drain Position; removing the patterned first sacrificial layer and a portion of the semiconductor substrate below to form an opening; soil forming a sacrificial spacer on the side wall of the opening; forming a gate dielectric layer in the opening A bottom; forming a gate conductor layer to fill the opening; and removing the #Hai patterned second sacrificial layer and the sacrificial spacer. = · If the manufacturing method of self-aligned gate electrode in item 15 of the scope of patent application: The material of the semiconductor substrate is selected from the group of silicon wafers and silicon-clad insulating layer wafers. The method for manufacturing a self-aligned gate electrode further comprises forming an etch stop layer on the semiconductor substrate before forming the patterned first sacrificial layer on the semiconductor substrate. • If the method of manufacturing self-aligned gates is applied for under item 17 of the patent scope,第19頁 200411832 六、申請專利範圍 其中該蝕刻 、、，丨正尽Page 19 200411832 6. Scope of patent application19·如申請專利範圍第17項之自我對準間極之 其中移除該圖案化第二犧牲層與該犧牲間 ^ ’ 除該蝕刻終止層。 土更包括移 20. 如申請專利範圍第15項之具凹陷 之製造方法，其中該第一犧牲層之材質為二自氧我化 21. 如申請專利範圍第15項之具凹陷通道之自 之製造方法，其中該第二犧牲層之材質為氮化矽%準閘極 2 2 ·如申請專利範圍第1 5項之具凹陷通道之自 之製造方法，其中以蝕刻技術移除該圖案化第一、準閘極 其下方之部分該半導體基材，其之後更包括有一犧牲層與 化而於遠開孔底部形成一二氧化；g夕層之步驟。進行熱氧 23·如申請專利範圍第丨5項之自我對準閘極之製生 其中形成該犧牲間隙壁於該開孔側壁，至少 造方法 驟： 匕括下列步 開孔之側邊 沉積一二氧化矽層於該第二犧牲層表面與該 及底部；以及 ^ w 回#刻該二氧化;ε夕層，以形成該犧牲間隙壁19. The self-aligned electrode of item 17 of the scope of application for a patent, wherein the patterned second sacrificial layer and the sacrificial layer are removed ^ ′ except the etch stop layer. The soil further includes the method of manufacturing a recessed product according to item 15 of the scope of patent application, wherein the material of the first sacrificial layer is self-oxidation. The manufacturing method, wherein the material of the second sacrificial layer is a silicon nitride% quasi-gate 2 2. The manufacturing method with a recessed channel as described in claim 15 of the patent application, wherein the patterned section is removed by an etching technique. 1. A part of the semiconductor substrate just below the quasi-gate, further comprising a sacrificial layer and a step of forming a dioxide at the bottom of the far-opening hole; Perform the hot oxygen 23. For example, the self-aligned gate electrode of item 5 of the application scope of the patent application, wherein the sacrificial spacer is formed on the side wall of the opening, at least the method is as follows: A silicon dioxide layer on the surface and the bottom of the second sacrificial layer; and the second oxide layer is etched to form the sacrificial spacer第20頁Page 20