SYSTEMS AND MODULATION METHODS THAT INCLUDE THE OVERLAYING OF ANGOSTA BAND SIGNALS AND COMPENSATION OFCC DISC LEVEL FIELD OF THE INVENTION This invention relates to modulation systems and methods, and more particularly to modulation systems and methods that modulate digital input signals. BACKGROUND OF THE INVENTION Modulation methods and systems are widely employed in transmitters to modulate an information input including voice and / or data in a carrier. The carrier can be a final carrier or an intermediate carrier. The carrier frequency can be found in UHF, VHF, RF, microwave or any other frequency band. Modulators are also known as "mixers" or "multipliers". For example, a modulator for the telephony radio transmitter is used in a mobile radiotelephone. As is known to those skilled in the art, modulation methods and systems for digital input signals generally include a digital-to-analog element convert (DAC) that converts a digital input signal into an analog signal. A low-pass filter that is also known as a "filter against secondary elements" filters the analog signal to produce a filtered analog signal. A modulator modulates the filtered analog signal on a carrier. The modulator includes a multiplier connected to a local oscillator such as, for example, a Voltage Controlled Oscillator (VCO), and with the filtered analog signal. The carrier including the filtered analog signal can then be transmitted through an antenna. In modern communication systems, dual mode modulation systems and methods are often desired which can modulate two types of communication signals. For example, in radio mobile phones, it is often important to offer a modulator that operates in either narrow band FM mode or multiple division access mode.
Code (CDMA). More particularly, in order to offer a mobile telephone radio that can be used with both an IS-19-AMPS analog system and a broadband Extended Spectrum Broadband CDMA (DSSS) systemIS-95, it is desirable to offer dual mode modulation systems and methods. Unfortunately, it can be difficult to offer dual mode modulation systems and methods that can handle the different bandwidths of the AMPS and CDMA signals. Particularly, the narrowband AMPS FM signal has a bandwidth of approximately 12.5 KHz, while the broadband CDMA signal has a bandwidth of approximately 615 KHz, or approximately one order of magnitude higher.
In modern radiotelephones, mobile radiotelephones continue to have an increasingly smaller size, cost and energy consumption. In order to meet these objectives, it is generally desirable to share circuits in dual-mode radiotelephones. A shared circuit can decrease the number of components that are used in the modulator thus allowing a decrease in the size of the same. Shared components can also decrease the power consumption of the dual-mode modulation system, which can allow an increase in battery time. Finally, the fact of sharing components can allow a reduction in the cost of the component, thus allowing a reduction in the overall cost of the radiotelephone. Figure 1 illustrates a first conventional double mode modulator. As shown in Figure 1, an IQ modulator 10, also known as a "quadraphase modulator" or "a quadrature modulator" includes a quadrature divider 20, also known as a 90 ° phase shifter and a pair of multipliers 16a, 16b connected to the quadrature divider. A local oscillator 15, such as a Voltage Controlled Oscillator (VCO), is connected to the quadrature divider 20 to produce local oscillator signals with a 90 ° phase shift. I data lia and Q data llb are connected to a respective multiplier or mixer 16a, 16b, respectively. Digital input data are converted into analog data through a Digital to Analog I (DAC) converter 14a and Q DAC 14b respectively. The outputs of the DACS 14a and 14b respectively are applied to low pass filters 12a and 12b respectively to provide the I and Q data inputs lia and llb respectively. The modulator modulates the input data in a carrier 13 by summing the outputs of the multipliers 16a, 16b in addition node 218, and transmits the modulated carrier 13 through an antenna. The DACS 14a and 14b, low pass filters 12a and 12b and IQ10 modulator can be used to modulate a high bandwidth CDMA signal such as a Direct Sequence Extended Spectrum (DSSS) signal on a carrier. Since the signal is digitally generated, it is filtered from low pass through the filters 12a and 12b to allow the passage of information while removing secondary elements and digitally generated noises.In order to use the IQ modulator 10 of the Figure 1 in a double mode, as for example for a narrow band FM signal, a separate FM DAC 19 and a separate FM low pass filter can be provided 17. A baseband circuit generates an FM voltage signal that is applied to VCO tuning line, to modulate the FM information on 1 carrier for transmission in accordance with the AMPS standard.As the FM voltage signal is digitally generated, it is filtered from low pass by a low pass filter FM 17 for letting the information pass while removing the digitally generated secondary elements and noise The low pass filter 17 generally has a different bandpass characteristic of low pass filters or 12a and 12b that are part of the CDMA modulator due to widely differing bandwidths of the FM and CDMA signals. Accordingly, in this dual-mode mode, a separate FM DAC 19 and a separate FM low pass filter 17 are provided. Modulation systems in accordance with Figure 1 have been designed in many integrated circuit chip environments developed for CDMA standards that also include AMPS functionality. Unfortunately, this technique employs DACS and low pass filters which can increase the size, cost and / or power consumption of the modulator. A second dual mode modulation system is illustrated in Figure 2. In this figure, an IQ modulator 210 including a quadrature splitter 220, a pair of multipliers 216a and 216b, a summing node 218 and a VCO 215 are provided to produce a modulated carrier 213. However, in contrast to Figure 1 the DACS and low pass filters are shared for the double mode operation. Particularly, the I DAC and Q DAC 214a and 214b respectively are used for both wideband CDM operation and narrowband FM operation. Low-pass filters 212a and 212b are also used for broadband CDMA operation and narrowband FM operation. Unfortunately, due to the very different bandwidths of the CDMA signal and FM signal, the low pass filters 212a and 212b must have different bandpass characteristics when in different modes. In order to divide the low pass filter, the band pass frequency is switched according to the mode. Accordingly, while these switched filters 212a and 212b are employed in both modes they can be expensive in terms of their implementation and can consume an excessive amount of energy and / or require an excessive area in a radio telephone. In high performance communication systems, it may also be desirable to provide high carrier suppression. In order to provide high carrier suppression, a low DC level must be produced in the modulation system. For example, the carrier suppression required for FM modulation in an AMPS IS-19 analog system can be approximately -35dBC. In order to offer an acceptable design margin, it may be preferred that the nominal carrier suppression is -14dBc, which can be translated into a signal with a difference in differential DC level of 14 mV when generating a peak-to-peak differential information signal of 2 V in a balanced system.
A low DC level difference in the digital input signal can be provided using conventional techniques. Unfortunately, however, the modulation system can generate its own CC slope. More specifically, the analog digital element converter and / or the low pass filter can generate DC slopes. The difference in DC that is generated in the digital-to-analog element converter can be reduced by using high-performance digital-to-analog element converters. Unfortunately, these digital-to-analog element converters can be expensive and complex. The CC slope can be reduced in the low pass filter by providing a passive pass filter with high tolerance components. Unfortunately, such a filter outside passive lacquer can be expensive and complex, and can consume too much space on a portable telephone radio. COMPENDIUM OF THE INVENTION It is therefore an object of the present invention to offer improved modulation systems and methods. It is another object of the present invention to provide dual mode modulation systems and methods for a first signal and a second narrower band signal than the first signal. It is another object of the present invention to offer dual-mode modulation systems and methods for a first signal and a second narrower band signal than the first signal that components of the modulation system can share in order to provide dual-mode modulation. Compact, economical and / or low energy consumption. It is another object of the present invention to offer modulation systems and methods that can generate low DC levels. These and other objects are provided in accordance with the present invention, by modulating a narrow band signal, such as for example a narrowband FM signal in a modulator that modulates a broadband signal, such as the CDMA signal, for example. by oversampling the narrowband signal and by applying the oversampled narrowband signal to the modulator. By oversampling the narrow band signal, the same fixed low pass filter can be used both for the wideband signal and for the oversampled narrowband signal. Therefore, different low pass filters and switched low pass filters are not required. In a particular aspect of the present invention, a CDMA modulator including a sampler is used for dual-mode modulation by applying a narrow-band FM signal to the CDMA modulator such that the CDMA modulator overbalances the FM signal and modulates the FM signal oversampled. The CDMA modulator includes a fixed low pass filter having a bandpass encompassing a CDMA signal and the oversampled FM signal such that the same fixed low pass filter is used to filter both the CDMA signal and an FM signal. The CDMA modulator can be particularly useful in a radio telephone where the CDMA signal can be a direct sequence extended spectrum signal and the FM signal can be an analog cellular telephone signal. Dual-mode modulation systems in accordance with the present invention include means for modulating a signal applied on a carrier and means for applying a first signal to the modulation means, thus modulating the first signal on a carrier. The oversampling means is included to oversample a second narrower band signal than the first signal. The systems also include means for applying the second narrow band signal oversampled to the modulation means to thereby modulate the second narrowest band signal in a carrier. The modulation means preferably comprises a digital-to-analog element converter and a low-pass filter that filters the analog output of the digital-to-analog element converter, where the low-pass filter has a bandpass covering the first signal, and the second narrow band signal oversampled, such that the same fixed low pass filter is used to filter both the first signal and the second narrow band signal oversampled, when the modulation means comprises an IQ modulator having inputs I and Q, the oversampling means preferably comprises a first sampler and a second sampler.
The dual-mode modulation systems according to the present invention also include means for sampling an applied signal, means for converting the sampled signal into an analog signal, means for filtering the low-pass analog signal and means for modulating the filtered analog signal. low pass in a carrier. Double mode modulation systems also include means for applying a first signal on the sampling means, in order to modulate the first signal on a carrier in this way using the sampling means, the conversion means and the filter means of low step and to apply a second narrower band signal than the first signal to the sampling means, in order to thereby oversample the second signal modulate the second signal on a carrier using the sampling means, conversion means and means of low-pass filtration. Accordingly, the same non-switched filters can be used for both wideband and narrowband signals in order to thereby allow a reduction in cost, space and / or power consumption. Dual-mode modulation systems and methods in accordance with the present invention also compensate for the DC slope that is introduced by a digital-to-analog element converter and / or the low-pass filter. The compensation is preferably provided in the digital domain, in order to reduce the CC level difference within acceptable limits for the modulation that is being used. More preferably, compensation is provided by subtracting from the sampled signal a digital value representing the CC slope in the filtered analog signal that is input by the digital-to-analog element converter and / or the pass filter low. Modulation systems in accordance with the present invention include a digital-to-analog element converter that converts the sampled signal into an analog signal. The analog signal is filtered by a low pass filter in order to produce a filtered analog signal. The digital-to-analog element converter and / or the low-pass filter introduce a DC slope in the filtered analogue signal. A modulator modulates the filtered analog signal on a carrier. A DC offset compensator compensates for the DC offset in the filtered analog signal that is input by the digital to analog element converter and / or the low pass filter. DC slope gauges in accordance with the present invention preferably include a sensor that detects the DC slope in the filtered analog signal. A converter of digital analog elements responds to the sensor, to convert the detected CC slope into a digital signal with unevenness. A subtractor responds to the analog-to-digital element converter to subtract the digital signal with DC slope from the sampled signal, and to apply the sampled signal minus the digital signal with DC slope, to the digital-to-analog element converter. Therefore, the detected slope is subtracted in the digital domain. A demultiplier can also be included which responds to the converter of analogue to digital elements, in order to demultiplate the digital signal with a DC slope in a digital signal with a difference in DC level decremented. The subtractor then responds to the demultiplicator, to subtract the digital signal from the unbalanced DC slope of the sampled signal. The subtractor does not have to continually detect the CC slope in the filtered analog signal, but can do so on an intermittent basis and preferably periodically. For example, the DC slope compensator may include an engaging element that responds to the converter of analogue to digital elements to intermittently engage the digital signal with DC slope and to apply the digital signal hooked with DC slope to the subtracter, in such a way that the digital signal hooked with CC slope is subtracted from the signal sampled. When the analog-to-digital element converter is synchronized with a first clock speed, the engaging element can be synchronized at a second clock speed lower than the first clock speed. The sensor may comprise a low pass filter that detects the DC level difference in the filtered analog signal. In one embodiment, the analog-to-digital element converter is a converter of analogue to digital delta-sigma elements of a bit. In another mode, the polarity inverter responds to the sensor, in order to periodically invert the polarity of the signal detected with a DC level difference. The analogue to digital element converter converts the signal with detected DC slope with inverted polarity into the digital signal with slope, thus reducing the effect of the internal DC slope of the analogue to digital element converter. The DC slope offset can be usefully employed with dual band modulators where the sampled signal comprises a signal selected between a first digital input signal and a second digital band input signal narrower than the first digital input signal. For example, the invention can be employed with a first digital input signal that is a CDMA signal, and with a second digital input signal that is an FM signal. More specifically, the CDMA signal may be a direct sequence spread spectrum signal, and the FM signal may be an analog cellular telephone signal. The present invention can also be used in IQ modulators, which are also known as "quadraphase modulators" or"quadrature modulators" that modulate analog signals filtered in phase and quadrature in a carrier. Analog modulation methods can also be provided. Accordingly, the modulation systems and methods for a digital input signal can provide low DC level regardless of the introduction of DC slope by the digital to analog element converter and / or the low pass filters thereof. It does not require the use of costly and high performance digital to analog element converters. It is not required to use low pass filters outside high performance flake. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a first conventional double mode modulation system and method. Figure 2 is a block diagram of a second conventional double mode modulation system and method. Figure 3 is a block diagram of dual-mode modulation systems and methods that include DC slope compensation in accordance with the present invention. Figures 4A and 4B, which when placed tips form Figure 4, are a block diagram of a second embodiment of dual mode modulation systems and methods that include a CC slope offset in accordance with the present invention. Figure 5 is a block diagram of a one-bit digital delta-sigma analog-to-digital converter that can be used to compensate for the CC slope in accordance with the present invention. Figure 6 illustrates another embodiment of an analog-to-digital element converter that can be used to compensate for a DC slope in accordance with the present invention. Figure 7 illustrates the operation of a polarity inverter that can be employed in Figure 6. Figure 8 is a block diagram of modulation systems and methods in accordance with the present invention. Figures 9A 9B which, when placed together as indicated in Figure 9, illustrate a first embodiment of dual mode IQ modulation systems and methods in accordance with the present invention.
Figure 10 illustrates a second embodiment of dual mode IQ modulation system and methods in accordance with the present invention. Figures HA and 11B, which when placed together as indicated in Figure 11, illustrate the mode of one-way IQ modulation systems and methods according to the present invention. DETAILED DESCRIPTION OF PREFERRED MODALITIES The present invention will now be described more fully with reference to the accompanying drawings in which preferred embodiments of the present invention are illustrated.
This invention however can be incorporated in many different forms and should not be considered as limited to modalities presented herein. On the contrary, these embodiments are provided in such a way that this disclosure is complete and complete, and will provide the scope of the present invention to those skilled in the art. Similar reference numbers refer to similar elements throughout the description. Referring now to Figure 3, a block diagram of dual-mode modulation systems and methods in accordance with the present invention is illustrated. As shown in Figure 3, dual-mode modulation system and methods include a dual IQ 310 module that includes a VCO 315, a pair of multipliers 316a and 316b, a quadrature splitter 320, and a sum mode 318. The interconnection of these elements to form a quadrature modulator are known to those skilled in the art and will not be described here in more detail. As shown also, an IQ 310 modulator accepts I 311a inputs as well as Q 311b inputs and produces an output 313 that modulates these inputs on a carrier. Still with reference to Figure 3, dual mode modulation systems and methods in accordance with the present invention include a pair of fixed low pass filters 312a and 312b. Low pass filters include a bandpass that allows the passage of broadband signals, such as DSSS signals according to CDMA. An I DAC 314a and a Q DAC 314b are also included. Still with reference to Figure 3, a pair of samplers 330a and 330b, which are also known as sampler I and sample Q, are also included, respectively. Second invention, and as shown in Figure 3, a source is broadband signals, such as for example DSSS 350 signal source and a narrowband signal source such as FM 340 signal source are both applied to the samplers 330a and 330b. A DSSS 350 signal source can produce a DSSS-I and DSSS-Q signal that are applied to the sampler 330a and the sampler 330b, respectively. An FM signal source 330 can produce an FMI signal and an FMQ signal that are applied to the sampler I 330a and the sampler Q 330b, respectively. It will be understood that the DSSS 350 signal source and the FM 340 signal source can be generated as baseband signals in dual mode radiotelephones. The generation of DSSS signals and FM signals in dual-mode radiotelephones are well known to those skilled in the art and do not require further description here. Still referring to Figure 3, it can be seen that the samplers 330a and 330b and the DACs 314a and 314b operate at a sampling rate. Sampling- Sampling rate Sampling can be controlled by a signal that is applied to a control line 335. The sampling rate is generally established through the sampling rate for the broadband signals 350. Accordingly, when the narrowband signals 340 are applied to the sampler 330a and 330b, the sampler acts to oversample the signals of narrow band. By oversampling the narrow band signals, the same DACs and low pass filters 314 and 312, respectively, can be used for wide band and narrow band signals. It will be understood that as part of broadband signal modulation, broadband signals may also be oversampled by samplers 330a and 330b. In this case, the narrowband signals are highly oversampled by the samplers 330a and 330b. It will also be understood that the sampling rate does not have to be identical for broadband and narrowband signals. However, the Sampling rate sampling is generally maintained at such a rate that the same fixed low pass filters 312a and 312b can be employed for wideband and narrowband signals. Accordingly, a dual mode modulator can employ the same non-switched low pass filters to modulate the broadband signals and the oversampled narrow band signals to thereby save cost, space and / or energy. The present invention can employ the same fixed low pass filter (without switching) for both the FM signal and the extended spectrum signal fed to the IQ modulator. Several low-pass filters are not required, such as low-pass filters. In order to employ the same fixed low pass filter, the FM signal is highly oversampled in the DAC preferably at the same sampling rate as the spread spectrum signal. To be sampled at this speed in the DAC is oversampled, interpolated at this highly oversampled speed. For an IS-95 signal, the sample rate can be 8X or 4.9152MHz. For convenience, the sample rate for the FM signal can be a divider of a reference clock rate that is close to the sample rate IS-95 (19.2MHz / 4 or 4.8MHz). Secondary sampling elements (~ 5MHz) can be reduced by the low pass filter to meet the secondary element performance specifications of the transmitter for both AMPS and CDMA. Through significant oversampling of the FM signal, the sampling noise floor from the DAC can be decreased to acceptable levels for AMPS transmission (<60dBc). The extended spectrum signal is not so highly oversampled, on the contrary it is normally oversampled (8X). The sampling noise floor for the DAC for this mode can be decreased to acceptable levels for the IS-95 transmission (< 45dBc). The spurious free dynamic range for any mode is preferably greater than the difference between the highest signal and the noise floor (> 60dB for APMS and> 45dB for CDMA). Thus, the quality of the IQ modulator is preferably sufficient to meet modulation specifications in the AMPS mode, which are generally more severe than in the CDMA mode. It is also the case of a conventional system of Figure 2, where the IQ modulator is shared and the low pass filter is switched. The present invention can be applied to systems and methods of modulation that share an IQ modulator with an FM signal(narrow band) and an extended-spectrum signal of direct sequence (broadband). The analog FM signal is converted into a digital signal at a certain speed. If the conversion speed is low, then the sampling / interpolation speed can be increased to the desired final sampling rate. During the A / D conversion, it is possible to immediately oversample the desired final velocity. The present invention can also be applied to systems and modulation methods that share an IQ modulator with a non-extended digital signal (narrow band) and a direct-sequence extended spectrum (broadband) signal. Thus, the present invention can be used in mixed AMPS / CDMA (IS-95) radiotelephones, mixed GSM / WCDMA radiotelephones (third-generation broadband cellular standards), and other radiotelephones combining broadband signals with narrowband signals. Still with reference to Figure 3, a CC slope offset according to the invention will be described below. Although the sampled I and Q signals 333a and 333b may have a DC slope, the DC slope introduced by at least one of the analog digital element converters 314a and 314b and the low pass filters 312a and 312b may produce a vertical drop. of CC unacceptably high. The digital-to-analog element converters 314a and 314b and the pass filter 312a and 312b are collectively involved as sources of DC slope by shaded blocks 324a and 324b. In accordance with the invention, DC slope compensators 22a and 322b are provided which compensate for the DC slope in the filtered analog signal311a and 311b which is input by at least one digital-to-analog element converter 314a and 314b and the at least one low-pass filter 312a and 312b. As shown, the DC slope equalizers 322a and 322b act on the sampled signals 33a and 33b in the digital domain to compensate for the DC shift in the filtered analog signals 311a and 311b which is input by at least one of the inverters of the inverter. digital elements to analog 314a and314b and the low pass filters 312a and 312b, in order to reduce the CC slope in this way within acceptable limits for the modulation scheme used. More specifically, as shown in FIG. 3, each of the DC slope equalizers 322a and 322b preferably includes a DC sensor 321a, 321b which detects the DC level difference in the filtered analog signal 311a, 311b. A digital analog element (ADC) converter 323a, 323b converts the detected DC level difference 329a, 329b, into a digital CC slope signal 331a, and 331b. A subtractor 326a, 326b subtracts the digital signal with DC ramp 331a, 331b from the sampled signal 333a, 333b and applies the sampled signal minus the signal with DC ramp 327a, 327b, to the digital-to-analog element converter 314a, 314b. Therefore, the difference in CC generated in the forward path is detected and converted into a digital value. The digital value representing the CC offset is then subtracted from the incoming sampled signal 333a, 333b. As also shown in Figure 3, the digital CC slope signal does not have to be calculated on the same frequency as the conversion of digital to analog elements by the digital-to-analog element converts 314a and 314b to compensate for the CC slope. On the contrary, the CC slope can be determined intermittently, preferably periodically. Accordingly, as shown in FIG. 1, engaging elements 325a and 325b can be used to intermittently and periodically engage the digital signals with CC slope 311a and 311b, in such a way that the digital signals with DC level difference hooks 332a and 332b are subtracted from the sampled signals 333a and 333b. Therefore, as will be described below, the engaging elements 325a and 325b and / or the analog-to-digital element converters 323a, 323b can be synchronized at lower frequencies than the digital-to-analog element converters 314a and 314b, since the unevenness of CC Generally it will not vary as fast as the sampled signals 333a and 333b. In a particular example, the CC offset can be detected once per second or at other intervals. It will be understood that in Figure 3 two separate DC slope equalizers 322a and 322b are provided for the two input signal paths. However, it will be understood that a single DC level difference compensator can be used for both the input signal path I and the input signal path Q. Referring now to FIG. 4, another mode of the IQ modulator will be described. double mode according to the present invention. In Figure 4, an optional demodulator 460a, 460b is employed between a respective digital analogue element converter 323a, 323b and a respective engaging element 325a, 325b. The demultiplicator decreases digital signals with CC slope 329a, 329b in digital signals with decremented DC level difference 321a ', 329b'. The demultiplication can be used in order to apply a demultiplication factor to the digital signal produced by the analog-to-digital element converters 323a, 323b. For example, when a differential DC voltage is detected by the CC sensors 3521a, 321b of FIG. 4, a reduction factor may be employed. Also, in Figure 4, an optional amplifier 461a, 461b is employed between a respective low pass filter 312a, 312b and a respective modulator 316a, 316b, to provide amplification, if necessary. As shown in FIG. 4, the DC slope compensators 322a, 322b can also compensate for a DC drop in the amplifiers 461a, 461b. As also shown in Figure 4, the synchronization for the analog-to-digital element converters 323a, 323b, for the digital-to-analog element converters 314a, 314b and for the engaging elements 325a, 325b can also be provided from a clock common 462. It will be understood that the voltage controlled oscillator 315 is also preferably engaged on the same reference as the common clock 462. As shown in Fig. 4, the digital-to-analog element converters 314a and 314b are preferably synchronized by the clock 462. The analog to digital element converters 323a and 323b are preferably synchronized a first clock speed that is less than 1 clock speed 462 divided by M (-rM) circuits 463a, 463b in addition, the engaging elements 425a, 425b are engaged at a second clock speed that is even lower than the first clock speed divided by N (-HN) cir 464a, 464b. The first clock speed and the second clock speed which are less than the clock speed 462 can be used, since it is not required that the CC drop is detected as frequently as the sampled signals 333a, 333b are digitally converted, that the CC slope changes generally less rapidly than the signal sampled itself. The sensors CC 321a, 321b of Figure 4 can be provided by passive low pass filters with a low angular frequency. A low angular frequency can be used since only the DC components should be detected. The subtraction in the digital domain can also occur at a low speed, which is preferably controlled by the division of the clock 462. DC offset gauges of Figure 4 can also cancel a CC drop that is as large as the Bitio Less Significant (LSB) of the digital to analog element converter 414a, 414b. The cancellation of the DC slope that can be achieved can be limited by the CC slope introduced by the analog-to-digital element converters 323a, 323b in the CC slope differences 322a, 322b. Accordingly, analogue to digital element converters 323a, 323b with low DC level difference are preferably used. U analog to digital element converter 323a, 323b preferred is a 1-bit delta-sigma converter. A 1-bit converter can be used in such a way that the feedback path within the delta-sigma converter can be obtained using a direct feedback connection without the need for components to intervene. Figure 5 illustrates a block diagram of a digital analog element converter 323 'delta-sigma of a bit. As shown in FIG. 5, the analog-to-digital element converter 323 'includes an integrator 70, a comparator 71, and a decimation / low pass filter 72. The output of the comparator 71 is retro-fitted to the input through the a summing node 73. The design of a 1-bit delta-sigma digital-to-analog converter is well known to those skilled in the art, and is described, for example, in Candy and Temes textbooks entitled "Oversampling Delta-Sigma Data Conversion", (Delta-Sigma Oversampling Data Converters) IEEE Press, 1992, in the chapter entitled "Oversampling Methods for A / D and D / A Conversion", (Oversampling Methods for A / Conversion) D and D / A), pages 1-25, the disclosure of which is incorporated herein by reference. Consequently, the DC slopes introduced per element in the forward path of the delta-sigma converter can be nullified. Thus, the only contributor to the DC gap can be the analog difference amplifier represented by the sum mode 73. The DC level difference can be reduced in this difference amplifier 73, such as, for example, by selecting a pass filter. under decimation 72 that has a curve at 10 Hz. Thus, the difference amplifier 73 can operate at a very low frequency, such as for example 10 KHz. The amplifier 73 can therefore be constructed with a large geometry, low frequency transistors which can have an excellent match of components when used in a process that also includes the high frequency digital to analog converters 314a, 314b. This good correspondence can produce low DC levels in the delta-sigma converter. Preferably, the angular frequency of the sensor 321 can be chosen to be low enough to attenuate the modulation, and thus maintain the modulation outside of the feedback loop. The frequency of the 1-bit delta-sigma converter is preferably selected in such a way that this modulation is removed without secondary errors. The engagement speed by the engaging element 325 is preferably sufficiently low such that the open loop system has settled. The resolution of the feedback is preferably within a less significant bit of the converter of digital-to-analog elements 314. This resolution can be determined by means of the oversampling relationship between the input and output of the decimation filter / low pass 72.
The greatest error correction may be available for the first subtraction. This correction can be achieved in one stage. Alternatively, this correction may be smoother through a digital filter that may be placed between the engaging element 325 and the subtracter 326. Alternatively, the transition may be smoother by forcing the engaging element to travel only 1 bit. less significant by hooking moment. The selection can be made based on the desired speed to initially set the compensation. Thereafter, the DC slope compensator can operate in a tracking mode, and the same technique can be employed. Figure 6 illustrates another embodiment of an analog-to-digital element converter system 80 that can employ any type of analog-to-digital element converter 323. As shown in Figure 6, a polarity inverter 81 is included that periodically reverses the polarity of the signal with detected CC slope. The operation of the polarity inverter 31 is schematically described in FIG. 7. With reference to FIG. 6, the analog-to-digital element converter 323 converts the signal 82 with periodically detected DC voltage dip with polarity reversal into a digital signal with unevenness . Since alternating samples have been inverted, even samples and odd samples are then hooked into a first engaging member 82a and second engaging member 82b. Before subtraction by a subtractor 83, one of the samples, such as for example the odd samples in the engaging element 82b are delayed by a delay 84. The subtraction of the polarity inversion samples of the block 85 can be synchronized using the clock 462, where the clock 862 is divided between R and applied to the polarity inverter 81 and the analog-to-digital element converter 323 by a first and second division between R (- ^ - R) circuits 86, 87. A slower clock produced by the division between R by P (- ^ R * P) circuits 88 can be used to synchronize the subtractor 83. The analog-to-digital element converter system 80 of FIG. 6 can produce a low DC level difference due to the following relations: Mo = CCdelevel "'" ^ measurement i = CCdelevel'T't'measurement f and CCdelevel = (M0"M?) / 2 where M0 is the error measured in an inverter state 81, Mi is the error measured in another state of the inverse 81, CCesmveí is the slope signal of CC 311 and Emeasurement is the error CC of the measurement system of Figure 6, which is considered constant between measurements.
When the polarity is changed or reversed, the measured DC level difference sign changes, but the CC error in the measurement system remains unchanged. The error is measured in an M0 state of the inverter and is measured again in the other Mi state. These two measurements are subtracted from each other and demultiplied by the demultiplicator 460 in the digital domain after the converter of analogue to digital elements 80. This subtraction can remove any DC error in the converter of analogue to digital elements 80. In order to align the even samples with odd samples, a delay of 84 can be used. Thus, a DC error in the analogue to digital element converter in the analogue to digital element converter can be reduced. Referring now to Figure 8, a block diagram of modulation systems and modulation methods for a digital input signal according to the present invention is shown. As shown in Figure 8, modulation systems and methods in accordance with the present invention include a Digital-to-Analog Element Converter (DAC) 814 that converts an input digital signal 833 into an analog signal 828. A low pass filter 812, also known as secondary anti-element filter, filters the analog signal 828 to produce a filtered analog signal 811. A modulator 816 modulates the filtered analog signal 811 in a carrier generated by a controlled source, such as, for example, a Voltage Controlled Oscillator (VCO) 815. The input modulated signal 813 is then transmitted through a transmission antenna 834. Another transmission circuit may also be included, as is known to those skilled in the art. Modulation systems and methods in accordance with that described in the preceding paragraph are well known to those skilled in the art. Unfortunately, however, even when the digital input signal 833 can have a low DC level difference, the DC slope that is introduced in at least one of the digital-to-analog element converter 814 and low-pass filter 812 can produce a vertical drop. of CC unacceptably high. The converter of digital-to-analog elements 814 and low-pass filter 812 are collectively marked as sources of DC slope by a shaded block 824. In accordance with the invention, a DC slope compensator 822 is provided which compensates for the unevenness of the CC in the filtered analog signal 811 input by at least one of the digital-to-analog element converter 814 and low-pass filter 812. As shown, the DC slope compensator 822 acts on the digital input signal 833 in the digital domain to compensate for the DC slope in the filtered analog signal 811 introduced by at least one of the digital-to-analog element converter 814 and low-pass filter 812 in order to reduce the DC slope within acceptable limits for the modulation scheme employed . More specifically, as shown in Figure 8, the DC slope compensator 822 preferably includes a DC sensor 821 which detects the DC slope in the filtered analog signal 811. An analog to digital element converter (ADC) 823 converts the detected DC level difference 829 in a digital DC level signal 831. A subtractor 826 subtracts the digital DC level signal 831 from the digital input signal 833 and applies the digital input signal minus the DC level signal 827 to the converter of digital-to-analog elements 814. Consequently, the difference in CC generated in the forward path is detected and converted into a digital value. The digital value representing the CC slope is then subtracted from the incoming digital input signal 833. As also shown in FIG. 8, the digital DC slope signal does not have to be calculated on the same frequency as the conversion of digital to analog elements through the converter of digital-to-analog elements 814 to compensate the CC slope. On the contrary, the CC slope can be determined intermittently, preferably periodically. Accordingly, as shown in FIG. 8, an engaging element 825 can be used to intermittently and periodically hook the digital DC level signal 831, such that the digital hooked DC level signal 832 is subtracted from the digital input signal 833. Thus, as will be described below, the engaging element 825 and / or the analog-to-digital element converter 823 can be synchronized at lower frequencies than the digital-to-analog element converter 814, since the unevenness DC generally does not vary as rapidly as the digital input signal 833. In a particular example, the DC level difference can be detected once per second, or at other intervals. Figure 9 illustrates a dual-mode IQ modulation system in accordance with the present invention. As shown, an IQ 910 modulator includes a quadrature divider 920, which is also known as a 90 ° phase splitter, and a pair of multipliers 916a, 916b connected to the quadrature divider. The VCO 915 is connected to the quadrature divider 920 to produce local oscillator signals shifted in phase to 90 °. A digital input signal I 933a and a digital input signal Q 933b are provided in respective I and Q paths of the IQ modulation system. The elements in the path I are designated by a reference character a and the elements in the path Q are designated by the reference character b. The IQ 910 modulator modulates the filtered analog signals I and Q 911a and 911b, respectively, on a carrier, summing the outputs of the multipliers 916a and 916b in the sum mode 918. The modulated input signal is transmitted through an antenna 934. The digital-to-analog element converters 914a and 914b, low pass 912a and 912b as well as the IQ 910 modulator can be used to modulate a high band CDMA signal such as a Direct Sequence Extended Spectrum (DSSS) signal, on a carrier. Since the signal is digitally generated. It is filtered by low pass filters 912a and 912b, to allow the passage of information while removing the secondary elements and digitally generated noises. In order to employ the IQ 910 modulator of Figure 9 in a dual mode, as for example for a narrow band FM signal, a separate 914c FM digital-to-analog element converter and a 912c FM low pass filter can be provided. separated. The components in the modulation path of the digital FM 933c input signal are marked with a reference character c. A baseband circuit generates the digital FM 933c input signal that is applied to the VCO 915 voice line to modulate the FM information on the carrier for transmission in accordance with the AMPS standard. The low pass filter 912c generally has a different bandpass characteristic than the low pass filters 912a and 912b which are part of the CDMA modulator, due to the very different bandwidths of the FM and CDMA signals. It will be understood that in Figure 9 three separate DC slope equalizers 922a, 922b and 922c are provided for the three input signal paths. However, it will be understood that a single DC level difference compensator can be used for both the digital input signal path I and the digital input signal path Q. In addition, a single DC level compensator can be used for all three paths of the input signal of FIG. 9. A second dual-mode modulation system is illustrated in FIG. 10. In this figure, the converters of digital-to-analog elements and low-pass filter are shared by the double-mode operation. Particularly, I DAC 1014a and Q DAC 1014b are used for both broadband CDMA operation and narrowband FM class operations. Low-pass filters and 1012a 'and 1012b' are also used for broadband CDMA operation and narrowband FM operation. Due to the very different bandwidths between the CDMA signal and the FM signal, the low pass filters 1012a 'and 1012b' must have different bandpass characteristics when two different modes are found. In order to share the low pass filters, the band pass frequency is switched according to the mode. Referring now to Figure 11, one mode of a one-way IQ modulator will be described in accordance with the present invention. In Figure 11, an optional demodulator 1160a, 1160b, is employed between a converter of respective analogue to digital elements 1123a, 1123b and a respective engaging element 1125a, 1125b. The demultiplicator decreases the digital DC slope signal 1129a, 1129b in a digital downmixed signal of DC 1129a ', 1129b'. The demultiplication can be used in order to apply a reduction factor to the digital signal produced by the analogue to digital element converter 1123a, 1123b. For example, when a differential DC voltage is detected by the CC sensors 1121a, 1121b of FIG. 11, it may be necessary to use a multiplication factor. Also, in 1 to FIG. 4, an optional amplifier 1161a, 1161b is employed between the respective low pass filters 1112a, 1112b, and the respective modulator 1116a, 1116b, to provide amplification, if necessary. As shown in Figure 11, the DC slope compensators 1122a, 1122b can also compensate for the DC slope in the amplifiers 1162a, 1161b.
As also shown in Figure 11, the synchronization for the analog-to-digital element converters 1123a, 1123b, for the digital-to-analog element converters 1114a, 1114b, and for the engaging elements 1125a, 1125b can also be provided from a common clock 1162. It will be understood that the voltage controlled source 1115 is also preferably appropriate on the same reference as the common clock 1162. As shown in Fig. 11, the digital-to-analog element converters 1114a and 1114b are preferably synchronized by the clock 1162. The analog to digital element converters 1123a, 1123b are preferably synchronized at a first clock speed that is less because the clock speed 1162 employing the division between M (- ^ M) circuits 1163a, 1163b. In addition, the engaging elements 1125a and 1125b are engaged at a second clock speed that is even smaller than the first clock rate using division between N (-i-N) circuits 1164a, 1164b. A first clock speed and a second clock speed that are lower than the clock speed 1162 can be used, since the DC level difference does not need to be detected as frequently as the input signals 1133a, 1133b are converted to digital, since that the CC slope changes generally less rapidly than the input signal itself.
The DC sensors 1121a, 112b of Figure 11 can be provided through passive low pass filters with a low angular frequency. A low angular frequency can be used because only the DC component has to be detected. The subtraction in the digital domain can also occur at a low speed which is preferably controlled by the division of the clock 1162. DC offset gauges of Figure 11 can cancel a CC drop that is as small as the Least Significant Bit ( LSB) of the digital-to-analog element converter 1114a, 1114b. The cancellation of the DC slope that can be achieved can be limited by the difference in CC introduced by the analogue to digital element converters 1123a, 1123b in the CC leveling compensators 1122a, 1122b. Accordingly, analog-to-digital converters 1123a, 1123b of low DC level are preferably used. A preferred analog-to-digital element converter 1123 a, 1123b is a one-bit delta-sigma converter. A one-bit converter can be used in such a way that the feedback path within the delta-sigma converter can be obtained using a direct feedback connection without the need for component intervention. A converter 23 'of analogue to digital delta-sigma elements of a bit of FIG. 5 can be used. An analog-to-digital element converter system 80 can also be employed which can employ any type of analog-to-digital element converter 23 as shown in Figure 6. In the drawings and specifications, typically preferred embodiments of the invention were presented, and even when specific terms are employed, they are used in a generic and descriptive sense only and not to limit the scope of the present invention presented in the following claims.