KR970007617A - - Google Patents

Info

Publication number: KR970007617A
Authority: KR; South Korea
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Ceased

KR19960029910A

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1995-07-27

1996-07-24Application filedfiledCritical

1997-02-21Publication of KR970007617ApublicationCriticalpatent/KR970007617A/ko

StatusCeasedlegal-statusCriticalCurrent

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

Landscapes

Physics & Mathematics (AREA)
Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Computational Mathematics (AREA)
Pure & Applied Mathematics (AREA)
Mathematical Analysis (AREA)
Mathematical Optimization (AREA)
General Engineering & Computer Science (AREA)
Computing Systems (AREA)
Mathematical Physics (AREA)
Theoretical Computer Science (AREA)
Computer Hardware Design (AREA)
Logic Circuits (AREA)

KR19960029910A1995-07-271996-07-24CeasedKR970007617A (ko)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US08/507,893US5570039A (en)	1995-07-27	1995-07-27	Programmable function unit as parallel multiplier cell

Publications (1)

Publication Number	Publication Date
KR970007617Atrue KR970007617A (ko)	1997-02-21

Family

ID=24020561

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
KR19960029910ACeasedKR970007617A (ko)	1995-07-27	1996-07-24

Country Status (3)

Country	Link
US (1)	US5570039A (ko)
JP (1)	JPH0950367A (ko)
KR (1)	KR970007617A (ko)

Families Citing this family (78)

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US20020088822A1 (en)*	1995-08-14	2002-07-11	Dresser, Inc.	Multiproduct fuel dispenser using a common meter
US5805477A (en)*	1996-09-26	1998-09-08	Hewlett-Packard Company	Arithmetic cell for field programmable devices
US6069487A (en)	1997-10-14	2000-05-30	Altera Corporation	Programmable logic device circuitry for improving multiplier speed and/or efficiency
JP3185727B2 (ja)*	1997-10-15	2001-07-11	日本電気株式会社	プログラマブル機能ブロック
GB9727414D0 (en)	1997-12-29	1998-02-25	Imperial College	Logic circuit
US6140839A (en)*	1998-05-13	2000-10-31	Kaviani; Alireza S.	Computational field programmable architecture
US6323680B1 (en)	1999-03-04	2001-11-27	Altera Corporation	Programmable logic device configured to accommodate multiplication
WO2000052824A1 (en)	1999-03-04	2000-09-08	Altera Corporation	Programmable logic device with carry-select addition
US7119576B1 (en)	2000-09-18	2006-10-10	Altera Corporation	Devices and methods with programmable logic and digital signal processing regions
US6628140B2 (en)*	2000-09-18	2003-09-30	Altera Corporation	Programmable logic devices with function-specific blocks
US7346644B1 (en)	2000-09-18	2008-03-18	Altera Corporation	Devices and methods with programmable logic and digital signal processing regions
US6771162B1 (en)*	2000-10-12	2004-08-03	Fairchild Semiconductor Corporation	Active cell crosspoint switch
US6959316B2 (en)*	2001-02-01	2005-10-25	Nokia Mobile Phones Limited	Dynamically configurable processor
DE60228083D1 (de)*	2001-05-16	2008-09-18	Nxp Bv	Rekonfigurierbare logik-vorrichtung
JP3613396B2 (ja)*	2001-06-25	2005-01-26	日本電気株式会社	機能ブロック
DE10159480B4 (de)*	2001-12-04	2006-05-24	Daimlerchrysler Ag	Steuervorrichtung
US7164288B2 (en)*	2003-02-19	2007-01-16	Koninklijke Philips Electronics N. V.	Electronic circuit with array of programmable logic cells
EP1606878A1 (en)*	2003-02-19	2005-12-21	Koninklijke Philips Electronics N.V.	Electronic circuit with array of programmable logic cells
US7082592B1 (en)	2003-06-16	2006-07-25	Altera Corporation	Method for programming programmable logic device having specialized functional blocks
US7698358B1 (en)	2003-12-24	2010-04-13	Altera Corporation	Programmable logic device with specialized functional block
US8620980B1 (en)	2005-09-27	2013-12-31	Altera Corporation	Programmable device with specialized multiplier blocks
US8041759B1 (en)	2006-02-09	2011-10-18	Altera Corporation	Specialized processing block for programmable logic device
US8266198B2 (en)	2006-02-09	2012-09-11	Altera Corporation	Specialized processing block for programmable logic device
US8301681B1 (en)	2006-02-09	2012-10-30	Altera Corporation	Specialized processing block for programmable logic device
US8266199B2 (en)	2006-02-09	2012-09-11	Altera Corporation	Specialized processing block for programmable logic device
US7570505B2 (en)*	2006-03-23	2009-08-04	Toshiba America Research, Inc.	Memory based computation systems and methods for high performance and/or fast operations
US7836117B1 (en)	2006-04-07	2010-11-16	Altera Corporation	Specialized processing block for programmable logic device
US7822799B1 (en)	2006-06-26	2010-10-26	Altera Corporation	Adder-rounder circuitry for specialized processing block in programmable logic device
US8386550B1 (en)	2006-09-20	2013-02-26	Altera Corporation	Method for configuring a finite impulse response filter in a programmable logic device
US7930336B2 (en)	2006-12-05	2011-04-19	Altera Corporation	Large multiplier for programmable logic device
US8386553B1 (en)	2006-12-05	2013-02-26	Altera Corporation	Large multiplier for programmable logic device
US7814137B1 (en)	2007-01-09	2010-10-12	Altera Corporation	Combined interpolation and decimation filter for programmable logic device
US8650231B1 (en)	2007-01-22	2014-02-11	Altera Corporation	Configuring floating point operations in a programmable device
US7865541B1 (en)	2007-01-22	2011-01-04	Altera Corporation	Configuring floating point operations in a programmable logic device
US8645450B1 (en)	2007-03-02	2014-02-04	Altera Corporation	Multiplier-accumulator circuitry and methods
US7949699B1 (en)	2007-08-30	2011-05-24	Altera Corporation	Implementation of decimation filter in integrated circuit device using ram-based data storage
US8959137B1 (en)	2008-02-20	2015-02-17	Altera Corporation	Implementing large multipliers in a programmable integrated circuit device
US8244789B1 (en)	2008-03-14	2012-08-14	Altera Corporation	Normalization of floating point operations in a programmable integrated circuit device
EP2141585A1 (en)*	2008-06-27	2010-01-06	Panasonic Corporation	Combined adder circuit array and and/or plane
US8626815B1 (en)	2008-07-14	2014-01-07	Altera Corporation	Configuring a programmable integrated circuit device to perform matrix multiplication
US8255448B1 (en)	2008-10-02	2012-08-28	Altera Corporation	Implementing division in a programmable integrated circuit device
US8307023B1 (en)	2008-10-10	2012-11-06	Altera Corporation	DSP block for implementing large multiplier on a programmable integrated circuit device
US8805916B2 (en)	2009-03-03	2014-08-12	Altera Corporation	Digital signal processing circuitry with redundancy and bidirectional data paths
US8549055B2 (en)	2009-03-03	2013-10-01	Altera Corporation	Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
US8468192B1 (en)	2009-03-03	2013-06-18	Altera Corporation	Implementing multipliers in a programmable integrated circuit device
US8645449B1 (en)	2009-03-03	2014-02-04	Altera Corporation	Combined floating point adder and subtractor
US8886696B1 (en)	2009-03-03	2014-11-11	Altera Corporation	Digital signal processing circuitry with redundancy and ability to support larger multipliers
US8706790B1 (en)	2009-03-03	2014-04-22	Altera Corporation	Implementing mixed-precision floating-point operations in a programmable integrated circuit device
US8650236B1 (en)	2009-08-04	2014-02-11	Altera Corporation	High-rate interpolation or decimation filter in integrated circuit device
US8412756B1 (en)	2009-09-11	2013-04-02	Altera Corporation	Multi-operand floating point operations in a programmable integrated circuit device
US8396914B1 (en)	2009-09-11	2013-03-12	Altera Corporation	Matrix decomposition in an integrated circuit device
US8539016B1 (en)	2010-02-09	2013-09-17	Altera Corporation	QR decomposition in an integrated circuit device
US7948267B1 (en)	2010-02-09	2011-05-24	Altera Corporation	Efficient rounding circuits and methods in configurable integrated circuit devices
US8601044B2 (en)	2010-03-02	2013-12-03	Altera Corporation	Discrete Fourier Transform in an integrated circuit device
US8458243B1 (en)	2010-03-03	2013-06-04	Altera Corporation	Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering
US8484265B1 (en)	2010-03-04	2013-07-09	Altera Corporation	Angular range reduction in an integrated circuit device
US8510354B1 (en)	2010-03-12	2013-08-13	Altera Corporation	Calculation of trigonometric functions in an integrated circuit device
US8539014B2 (en)	2010-03-25	2013-09-17	Altera Corporation	Solving linear matrices in an integrated circuit device
US8862650B2 (en)	2010-06-25	2014-10-14	Altera Corporation	Calculation of trigonometric functions in an integrated circuit device
US8589463B2 (en)	2010-06-25	2013-11-19	Altera Corporation	Calculation of trigonometric functions in an integrated circuit device
US8577951B1 (en)	2010-08-19	2013-11-05	Altera Corporation	Matrix operations in an integrated circuit device
US8645451B2 (en)	2011-03-10	2014-02-04	Altera Corporation	Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en)	2011-05-09	2017-03-21	Altera Corporation	Programmable device using fixed and configurable logic to implement recursive trees
US8812576B1 (en)	2011-09-12	2014-08-19	Altera Corporation	QR decomposition in an integrated circuit device
US9053045B1 (en)	2011-09-16	2015-06-09	Altera Corporation	Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en)	2011-09-16	2015-02-03	Altera Corporation	Computing floating-point polynomials in an integrated circuit device
US8762443B1 (en)	2011-11-15	2014-06-24	Altera Corporation	Matrix operations in an integrated circuit device
US8543634B1 (en)	2012-03-30	2013-09-24	Altera Corporation	Specialized processing block for programmable integrated circuit device
US9098332B1 (en)	2012-06-01	2015-08-04	Altera Corporation	Specialized processing block with fixed- and floating-point structures
US8996600B1 (en)	2012-08-03	2015-03-31	Altera Corporation	Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en)	2012-11-26	2015-12-08	Altera Corporation	Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en)	2013-03-14	2015-11-17	Altera Corporation	Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en)	2013-07-03	2016-05-24	Altera Corporation	Programmable device using fixed and configurable logic to implement floating-point rounding
US9379687B1 (en)	2014-01-14	2016-06-28	Altera Corporation	Pipelined systolic finite impulse response filter
US9684488B2 (en)	2015-03-26	2017-06-20	Altera Corporation	Combined adder and pre-adder for high-radix multiplier circuit
US10942706B2 (en)	2017-05-05	2021-03-09	Intel Corporation	Implementation of floating-point trigonometric functions in an integrated circuit device
US11374574B2 (en)	2019-12-27	2022-06-28	Kepler Computing Inc.	Linear input and non-linear output threshold logic gate
US12289104B1 (en)*	2021-09-02	2025-04-29	Kepler Computing Inc.	Ferroelectric or paraelectric based low power multiplier array

Family Cites Families (7)

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US4870302A (en)*	1984-03-12	1989-09-26	Xilinx, Inc.	Configurable electrical circuit having configurable logic elements and configurable interconnects
USRE34363E (en)*	1984-03-12	1993-08-31	Xilinx, Inc.	Configurable electrical circuit having configurable logic elements and configurable interconnects
US4642487A (en)*	1984-09-26	1987-02-10	Xilinx, Inc.	Special interconnect for configurable logic array
KR920003908B1 (ko)*	1987-11-19	1992-05-18	미쓰비시뎅끼 가부시끼가이샤	승산기(乘算器)
US5384497A (en)*	1992-11-04	1995-01-24	At&T Corp.	Low-skew signal routing in a programmable array
JPH06276086A (ja)*	1993-03-18	1994-09-30	Fuji Xerox Co Ltd	フィールドプログラマブルゲートアレイ
US5386156A (en)*	1993-08-27	1995-01-31	At&T Corp.	Programmable function unit with programmable fast ripple logic

1995
- 1995-07-27USUS08/507,893patent/US5570039A/ennot_activeExpired - Lifetime
1996
- 1996-07-23JPJP8192622Apatent/JPH0950367A/jaactivePending
- 1996-07-24KRKR19960029910Apatent/KR970007617A/konot_activeCeased

Also Published As

Publication number	Publication date
JPH0950367A (ja)	1997-02-18
US5570039A (en)	1996-10-29

Publication	Publication Date	Title
IN186494B (ko)	2001-09-15
KR970007617A (ko)	1997-02-21
IN181930B (ko)	1998-11-14
IN185675B (ko)	2001-03-31
ECSDI950244S (ko)	1996-11-04
IN187029B (ko)	2001-12-29
IN186172B (ko)	2001-07-07
IN183763B (ko)	2000-04-01
IN183503B (ko)	2000-01-22
IN183050B (ko)	1999-08-28
IN181854B (ko)	1998-10-03
AU1627395A (ko)	1995-06-30
CN3035300S (ko)	1995-09-20
CN3033771S (ko)	1995-08-02
CN3037433S (ko)	1995-11-22
CN3037189S (ko)	1995-11-08
CN3036648S (ko)	1995-10-25
CN3036647S (ko)	1995-10-25
CN3036463S (ko)	1995-10-18
CN3035871S (ko)	1995-10-04
CN3035870S (ko)	1995-10-04
CN3035869S (ko)	1995-10-04
CN3035868S (ko)	1995-10-04
CN3035323S (ko)	1995-09-20
CN3030296S (ko)	1995-02-22

Legal Events

Date	Code	Title	Description
1996-07-24	PA0109	Patent application	Patent event code:PA01091R01D Comment text:Patent Application Patent event date:19960724
1996-10-17	A201	Request for examination
1996-10-17	PA0201	Request for examination	Patent event code:PA02012R01D Patent event date:19961017 Comment text:Request for Examination of Application Patent event code:PA02011R01I Patent event date:19960724 Comment text:Patent Application
1997-02-21	PG1501	Laying open of application
1999-07-24	E902	Notification of reason for refusal
1999-07-24	PE0902	Notice of grounds for rejection	Comment text:Notification of reason for refusal Patent event date:19990724 Patent event code:PE09021S01D
1999-09-27	E601	Decision to refuse application
1999-09-27	PE0601	Decision on rejection of patent	Patent event date:19990927 Comment text:Decision to Refuse Application Patent event code:PE06012S01D Patent event date:19990724 Comment text:Notification of reason for refusal Patent event code:PE06011S01I

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KR970007617A - - Google Patents

Info

Links

Classifications

Landscapes

Applications Claiming Priority (1)

Publications (1)

Family

ID=24020561

Family Applications (1)

Country Status (3)

Families Citing this family (78)

Family Cites Families (7)

Also Published As

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