제1도는 종래의 다층 배선 공정단면도.1 is a cross-sectional view of a conventional multilayer wiring process.
제2도는 본 발명의 다층 배선 공정단면도.2 is a cross-sectional view of a multilayer wiring process of the present invention.
*도면의 주요부문에 대한 부호의 설명* Explanation of symbols for main parts of drawing
1 : 기판 2 : 하부 배선막1 substrate 2 lower wiring film
3 : 질화막 4 : 산화막3: nitride film 4: oxide film
5 : 절연막 6 : 텅스텐 플러그5: insulating film 6: tungsten plug
7 : 상부 배선막7: upper wiring film
본 발명은 반도체 집적회로의 다층 배선 형성방법에 관한 것으로 특히 고집적화된 기억소자 회로에 있어서 메모리 셀(단차가 높은 부분)과 주변 회로부(단차가 낮은 부분)와의 단차차이에 의해 발생하는 사진 식각 공정 및 배선 패턴의 왜곡을 방지하기에 적당하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring of a semiconductor integrated circuit, and in particular, in a highly integrated memory device circuit, a photolithography process caused by a step difference between a memory cell (a high step) and a peripheral circuit (a step) is provided. This is to prevent distortion of the wiring pattern.
종래의 다층 배선 형성방법은 제1a도에 도시된 바와같이 기판(11)위에 하부 배선막(12)을 형성하고 (b)와 같이 산화막(13)을 형성한 후 SOG나 폴리미드등의 평탄화용 절연막(14)과 산화막(15)을 차례로 형성한다. 그리고 (c)와 같이 마스킹 공정에 의해 비어 홀을 형성하고 상부 배선막(16)을 형성한다.In the conventional multi-layered wiring forming method, as shown in FIG. 1A, the lower wiring film 12 is formed on the substrate 11, and the oxide film 13 is formed as shown in (b). The insulating film 14 and the oxide film 15 are sequentially formed. As shown in (c), the via hole is formed by the masking process, and the upper wiring film 16 is formed.
그러나, 상기와 같은 종래 기술에 있어서는 메모리 셀과 주변회로부 사이의 단차에 의하여 층간절연막을 샌드위치 구조로 평탄화하고 비어 홀을 형성하면 메모리 셀부의 비어 홀보다 주변회로부의 비어 홀의 어스팩트 율(Aspect Ratio)이 증가하게 되므로 상부 배선막(16)을 스퍼터법으로 형성할 때 스텝 커버리지가 낮아져 배선의 신뢰성이 저하되기 쉽다. 또한, 비어 홀 식각시 하부 배선막(12)이 손상을 입어 상부 배선막(16)과 하부 배선막(12)의 접촉저항이 증가되는 결점이 있다.However, in the conventional technology as described above, when the interlayer insulating film is flattened into a sandwich structure by the step between the memory cell and the peripheral circuit portion, and the via hole is formed, the aspect ratio of the via hole of the peripheral circuit portion is larger than the via hole of the memory cell portion. Since this increases, the step coverage is lowered when the upper wiring film 16 is formed by the sputtering method, so that the reliability of the wiring tends to be lowered. In addition, when the via hole is etched, the lower wiring layer 12 may be damaged, resulting in an increase in contact resistance between the upper wiring layer 16 and the lower wiring layer 12.
본 발명은 이와같은 종래의 결점을 해결하기 위하여 안출한 것으로 메모리 셀과 주변회로부와의 단차를 없애기 위하여 배선 평탄화를 이루도록 함과 아울러 상부 배선막과 하부 배선막과의 접촉 저항을 낮출 수 있는 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned shortcomings, and in order to eliminate the step difference between the memory cell and the peripheral circuit portion, the planarization of the wiring and the contact resistance between the upper wiring film and the lower wiring film can be lowered. The purpose is to provide.
이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제2도에 의하여 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described with reference to the accompanying drawings.
먼저 (a)와 같이 기판(1)위에 하부 배선막(2)을 형성하고 패터닝한 후 질화막(3)을 단차높이 이상으로 퇴적한다. 그리고 (b)와 같이 단차가 낮은 부위의 비어가 형성될 부분에 질화막(3)이 남도록 패터닝한다. 다음에 (c)와 같이 산화막(4)을 형성하고 (d)와 같이 상기 산화막(4)위에 SOG나 폴리미드등의 절연막(5)을 도포하여 표면의 평탄화를 이루도록 한다.First, as shown in (a), the lower interconnection film 2 is formed and patterned on the substrate 1, and the nitride film 3 is deposited above the step height. Then, the patterning is performed such that the nitride film 3 remains in the portion where the via of the low step portion is to be formed, as shown in (b). Next, an oxide film 4 is formed as shown in (c), and an insulating film 5 such as SOG or polyamide is coated on the oxide film 4 as shown in (d) to planarize the surface.
이어서 (e)와 같이 절연막(5)과 산화막(4)과의 식각 선택비가 1이 되게 블랭키트 에치 백하여 질화막(3)이 표면에 드러나도록 한 후 (f)와 같이 질화막(3)을 제거하여 비어 홀을 형성한다. 그리고 (g)와 같이 상기 비어 홀에 텅스텐 플러그(6)를 형성하고 (h)와 같이 단차가 높은 부분에 비어 홀을 형성한 후 상부 배선막(7)을 형성한다.Next, as shown in (e), the blank kit is etched back so that the etching selectivity between the insulating film 5 and the oxide film 4 becomes 1 so that the nitride film 3 is exposed on the surface, and then the nitride film 3 is removed as shown in (f). To form via holes. The tungsten plug 6 is formed in the via hole as shown in (g), and the upper wiring film 7 is formed after the via hole is formed in a high step portion as shown in (h).
이상에서 설명한 바와같은 본 발명은 메모리 셀과 주변회로부와의 단차를 배선 평탄화를 이루어 해결함으로써 이후의 사진 식각 공정이나 배선 패턴의 왜곡을 방지할 수 있으며, 비어 필렛(Fillet) 접촉면이 비어 식각에 의한 손상을 피할 수 있어 하부 배선막(2)과 상부 배선막(7)과의 접촉 저항을 감소시킬 수 있다. 또한, 비어 홀의 깊이를 낮춤으로써 상부 배선막(7)의 스텝 커버리지를 향상시킬 수 있어 배선의 신뢰성을 높일 수 있는 효과가 있다.As described above, the present invention can prevent the distortion of the photolithography process or the wiring pattern by performing the planarization of the step between the memory cell and the peripheral circuit part, and the via fillet contact surface is formed by the via etching. Damage can be avoided and the contact resistance between the lower wiring film 2 and the upper wiring film 7 can be reduced. In addition, by decreasing the depth of the via hole, the step coverage of the upper wiring film 7 can be improved, thereby improving the reliability of the wiring.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910007580AKR930006721B1 (en) | 1991-05-10 | 1991-05-10 | Method of multi-layering of semiconductor integrated circuit |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910007580AKR930006721B1 (en) | 1991-05-10 | 1991-05-10 | Method of multi-layering of semiconductor integrated circuit |
| Publication Number | Publication Date |
|---|---|
| KR920022481A KR920022481A (en) | 1992-12-19 |
| KR930006721B1true KR930006721B1 (en) | 1993-07-23 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910007580AExpired - Fee RelatedKR930006721B1 (en) | 1991-05-10 | 1991-05-10 | Method of multi-layering of semiconductor integrated circuit |
| Country | Link |
|---|---|
| KR (1) | KR930006721B1 (en) |
| Publication number | Publication date |
|---|---|
| KR920022481A (en) | 1992-12-19 |
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