KR20170129475A - 금속 배선 형성 방법 및 이를 이용한 반도체 장치의 제조 방법 - Google Patents
금속 배선 형성 방법 및 이를 이용한 반도체 장치의 제조 방법Download PDFInfo
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- KR20170129475A KR20170129475AKR1020160060210AKR20160060210AKR20170129475AKR 20170129475 AKR20170129475 AKR 20170129475AKR 1020160060210 AKR1020160060210 AKR 1020160060210AKR 20160060210 AKR20160060210 AKR 20160060210AKR 20170129475 AKR20170129475 AKR 20170129475A
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- layer
- forming
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Abstract
Description
본 발명은 금속 배선 형성 방법 및 이를 이용한 반도체 제조 장치의 제조 방법(및 그러한 방법에 의해 제조된 반도체 장치)에 관한 것이다.
반도체 소자의 크기가 점차 축소됨에 따라 배선 구조에서 금속 배선의 선저항과 금속 배선을 둘러싸고 있는 층간 절연층(inter-layer dielectric)의 유전율에 의해 소자의 응답 속도가 저하되는 문제가 야기되었다. 이러한 문제는 RC 지연(Resistance-Capacitance delay)이라 하는데, RC 지연을 해결하기 위해 금속배선을 기존의 알루미늄에서 저항이 더 낮은 구리로, 금속배선을 둘러싸고 있는 층간 절연층을 좀더 낮은 유전율을 갖는 물질로 대체하고 있다.
종래 기술에 따르면, CMP(Chemical-Mechanical Planarization) 공정 후 배선층 위에 SiCN 층이 증착된다. 이러한 SiCN 층은 배선 공정 중에 식각 가스(특히 건식 식각 가스) 혹은 수분(H2O)이 다공성 구조의 저유전율 층간 절연층으로 침투하는 것을 막는 기능을 수행하며 ESL(etch stop layer) 층으로 사용되어 왔다. 그러나 소자의 크기가 점점 작아짐에 따라 더 얇은 두께의 SiCN 층의 요구가 있고, (유전율의 제한 등으로 인해) 100 Å보다 얇은 두께의 SiCN 막으로는 하부막인 저유전율(low-k) 막으로 수분이나 습기가 침투하는 것을 차폐하는 데 한계를 보이고 있다.
본 발명은 기존의 캡핑층인 SiCN 층보다 얇은 두께에서도 수분이나 습기로부터 하부 저유전율(low-k) 층을 보호하는 우수한 차폐특성(hermetic feature)을 갖는 박막을 증착하는 방법에 관한 것이다.
본 발명의 기술적 사상에 의한 실시예들의 일 측면에 따르면, 금속 배선 형성 방법은, 저 유전층(low-k dielectric layer) 증착 단계; 상기 저 유전층에 트렌치(trench)를 형성하는 단계; 상기 트렌치에 배리어층(barrier layer)를 형성하는 단계; 상기 배리어 층 상에 금속을 충진하는 단계; 상기 금속에 대한 평탄화(planarization) 단계; 및 상기 평탄화된 금속 상에 캡핑층(capping layer)을 형성하는 단계;를 포함하고, 상기 캡핑층은 적어도 2개의 층을 포함하고, 100Å이하의 두께를 가질 수 있다.
금속 배선 형성 방법의 일 예에서, 상기 캡핑층을 형성하는 단계는, 제1 질화층 및 제2 질화층을 증착하는 단계;를 포함할 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 제1 질화층 및 제2 질화층을 증착하는 단계는, AlN 층 증착 단계; 및 SiN 층 증착 단계;를 포함할 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 AlN 층은 플라즈마 원자 층 증착법(PEALD)을 이용하여 형성될 수 있다. 이 경우 일 예로서 상기 AlN 층 증착 단계는 복수의 사이클들을 포함하고, 상기 복수의 사이클들 각각은, Al 소스 기체 공급단계; 퍼지 기체 공급 단계; 반응 기체를 공급하고 플라즈마로 상기 반응 기체를 활성화하는 단계; 및 퍼지 기체 공급 단계;를 포함하고, 상기 퍼지 기체는 상기 사이클들 동안 반응 공간에 지속적으로 공급될 수 있다. 상기 Al 소스기체는 TMA(TriMethyl Aluminaum, Al(CH3)3)를 포함하고, 상기 반응 기체는 질소 및 수소의 혼합 기체를 포함할 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 SiN 층은 펄스화된 플라즈마 화학 기상 증착법(pulsed PECVD)을 이용하여 형성될 수 있다. 이 경우 일 예로서 상기 SiN 층 증착 단계는 복수의 사이클들을 포함하고, 상기 복수의 사이클들 각각은, Si 소스 기체 공급 단계; 퍼지 기체 공급 단계; 반응 기체를 공급하고 플라즈마로 상기 반응 기체를 활성화하는 단계; 및 퍼지 기체 공급 단계;를 포함하고, 상기 반응기체, 상기 퍼지 기체, 및 상기 플라즈마는 상기 사이클들 동안 반응 공간에 지속적으로 공급될 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 Si 소스 기체는 실란 기체를 포함할 수 있다. 또한 예시적으로 상기 Si 소스 기체는 SiH4, BDEAS(Bis(diethylamino) Silane), 및 DIPAS(Diisopropylamino Silane) 중 적어도 하나를 포함할 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 반응 기체는 질소 및 수소의 혼합 기체를 포함할 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 SiN 층의 두께는 적어도 30 옹스트롬일 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 제1 질화층 및 제2 질화층을 증착하는 단계는 플라즈마 처리 단계를 포함하고, 상기 플라즈마 처리 단계는 적어도 하나의 사이클을 포함하며, 상기 사이클은, 질소 함유 기체 공급 단계; 플라즈마로 상기 질소 함유 기체를 활성화하는 단계; 및 퍼지 기체 공급 단계;를 포함하며, 상기 사이클에 의해, 금속 상부의 산화 금속이 금속으로 환원될 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 캡핑층 형성 단계는 섭씨 250도 내지 섭씨 350도의 온도 범위에서 진행될 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 제1 질화층 및 상기 제2 질화층은 동일한 반응기에서 인-시튜(in-situ)로 형성될 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 AlN 층의 두께와 상기 SiN 층의 두께의 비율은 1:1.5 내지 1:2일 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 AlN 층 및 상기 SiN 층을 포함하는 상기 캡핑층은, 섭씨 85도의 온도 및 85%의 습도 조건에서 17시간 동안 노출된 경우, 50MPa 이하의 박막 스트레스 변화량을 가질 수 있다.
금속 배선 형성 방법의 다른 예에서, 상기 AlN 층 증착 단계 동안 공급되는 플라즈마 파워 및 상기 SiN 층 증착 단계 동안 공급되는 플라즈마 파워의 비율은 10:1 내지 8:1일 수 있다.
본 발명의 기술적 사상에 의한 실시예들의 일 측면에 따르면, 반도체 장치의 제조 방법은, 저 유전층(low-k dielectric film) 증착 단계; 상기 저 유전층에 트렌치(trench)를 형성하는 단계; 상기 트렌치에 배리어 층(barrier film)을 형성하는 단계; 상기 배리어 층 상에 구리를 충진하여 구리층을 형성하는 단계; 상기 구리층에 대한 평탄화(planarization)를 수행하는 단계; 상기 평탄화된 구리층에 플라즈마를 인가하는 단계; 플라즈마 강화 원자층 증착(Plasma Enhanced Atomic Layer Deposition, PEALD) 방법을 이용하여, 상기 평탄화된 구리층 상에 AlN 층을 형성하는 단계; 및 상기 AlN 층을 형성한 반응기와 동일한 반응기에서 인-시튜(in-situ)로, 상기 AlN 층 상에 SiN 층을 형성하는 단계를 포함하고, 상기 AlN 층의 두께 및 상기 SiN 층의 두께의 합은 50 옹스트롬 내지 100 옹스트롬 이며, 상기 AlN 층의 형성 단계 및 상기 SiN 층의 형성 단계는 섭씨 250도 내지 섭씨 350도의 온도범위에서 수행되는 것을 특징으로 하는, 반도체 장치의 제조 방법.
본 발명의 기술적 사상에 의한 실시예들의 일 측면에 따르면, 반도체 장치의 제조 방법은, 제1 유전층을 형성하는 단계; 상기 제1 유전층 내에 제1 금속층을 형성하는 단계; 및 상기 제1 유전층 및 상기 제1 금속층 상에 100 옹스트롬 미만의 두께를 갖는 캡핑층을 형성하는 단계를 포함하고, 상기 캡핑층을 형성하는 단계는, 질화알루미늄 층을 형성하는 제1 단계; 및 상기 질화알루미늄 층 상에 질화실리콘 층을 형성하는 제2 단계를 포함할 수 있다.
본 발명의 기술적 사상에 의한 실시예들의 일 측면에 따르면, 반도체 장치는, 제1 금속층; 상기 제1 금속층의 측면을 둘러싸는 제1 유전층; 상기 제1 금속층의 적어도 일부 및 상기 제1 유전층과 접촉하는 질화알루미늄 층; 상기 질화알루미늄 층 상의 질화실리콘 층; 상기 제1 금속층의 상면, 상기 질화알루미늄 층의 측면, 및 상기 질화실리콘 층의 측면과 접촉하는 제2 금속층; 및 상기 제2 금속층의 측면을 둘러싸는 제2 유전층을 포함하고, 상기 질화알루미늄 층의 두께 및 상기 질화실리콘 층의 두께의 합은 100 옹스트롬 미만일 수 있다.
본 발명의 기술적 사상에 의한 실시예들에 따르면, 기존의 캡핑층인 SiCN 막 대신에 AlN 박막을 증착하고 그 위에 SiN 박막이 증착된다. 이러한 이중 층 구조를 통해 기존의 SiCN층 보다 얇은, 수 나노미터 단위의 얇은 두께의 캡핑층을 구현하면서도 우수한 차폐특성(hermetic feature)이 달성될 수 있다.
도 1 내지 도 8은 본 발명에 따른 금속 배선 형성 방법을 나타낸다.
도 9는 본 발명에 따른 금속 배선 형성 방법 및 반도체 제조 장치의 제조 방법을 개략적으로 나타내는 흐름도이다
도 10은 본 발명에 따른 또다른 금속 배선 형성 방법 및 반도체 제조 장치의 제조 방법을 개략적으로 나타내는 흐름도이다.
도 11내지 도 12는 본 발명에 따른 또 다른 금속 배선 형성방법을 나타낸다.
도 13은 하부 기판 상에서 본 발명에 따른 이중 층 구조가 적절한 차폐 특성을 갖는지를 파악하기 위한 실험의 개략도이다.
도 9는 본 발명에 따른 금속 배선 형성 방법 및 반도체 제조 장치의 제조 방법을 개략적으로 나타내는 흐름도이다
도 10은 본 발명에 따른 또다른 금속 배선 형성 방법 및 반도체 제조 장치의 제조 방법을 개략적으로 나타내는 흐름도이다.
도 11내지 도 12는 본 발명에 따른 또 다른 금속 배선 형성방법을 나타낸다.
도 13은 하부 기판 상에서 본 발명에 따른 이중 층 구조가 적절한 차폐 특성을 갖는지를 파악하기 위한 실험의 개략도이다.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.
본 발명의 실시예들은 당해 기술 분야에서 통상의 지식을 가진 자에게 본 발명을 더욱 완전하게 설명하기 위하여 제공되는 것이며, 아래의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래의 실시예들로 한정되는 것은 아니다. 오히려, 이들 실시예는 본 개시를 더욱 충실하고 완전하게 하며 당업자에게 본 발명의 사상을 완전하게 전달하기 위하여 제공되는 것이다.
본 명세서에서 사용된 용어는 특정 실시예를 설명하기 위하여 사용되며, 본 발명을 제한하기 위한 것이 아니다. 본 명세서에서 사용된 바와 같이 단수 형태는 문맥상 다른 경우를 분명히 지적하는 것이 아니라면, 복수의 형태를 포함할 수 있다. 또한, 본 명세서에서 사용되는 경우 “포함한다(comprise)” 및/또는 “포함하는(comprising)”은 언급한 형상들, 숫자, 단계, 동작, 부재, 요소 및/또는 이들 그룹의 존재를 특정하는 것이며, 하나 이상의 다른 형상, 숫자, 동작, 부재, 요소 및/또는 그룹들의 존재 또는 부가를 배제하는 것이 아니다. 본 명세서에서 사용된 바와 같이, 용어 “및/또는”은 해당 열거된 항목 중 어느 하나 및 하나 이상의 모든 조합을 포함한다.
본 명세서에서 제1, 제2 등의 용어가 다양한 부재, 영역 및/또는 부위들을 설명하기 위하여 사용되지만, 이들 부재, 부품, 영역, 층들 및/또는 부위들은 이들 용어에 의해 한정되어서는 안됨은 자명하다. 이들 용어는 특정 순서나 상하, 또는 우열의 의미하지 않으며, 하나의 부재, 영역 또는 부위를 다른 부재, 영역 또는 부위와 구별하기 위하여만 사용된다. 따라서, 이하 상술할 제1 부재, 영역 또는 부위는 본 발명의 가르침으로부터 벗어나지 않고서도 제2 부재, 영역 또는 부위를 지칭할 수 있다.
이하, 본 발명의 실시예들은 본 발명의 이상적인 실시예들을 개략적으로 도시하는 도면들을 참조하여 설명한다. 도면들에 있어서, 예를 들면, 제조 기술 및/또는 공차에 따라, 도시된 형상의 변형들이 예상될 수 있다. 따라서, 본 발명의 실시예는 본 명세서에 도시된 영역의 특정 형상에 제한된 것으로 해석되어서는 아니 되며, 예를 들면 제조상 초래되는 형상의 변화를 포함하여야 한다.
도 1 내지 도 8은 본 발명의 기술적 사상에 의한 실시예들에 따른 금속 배선 형성 방법(및 반도체 제조 장치의 제조 방법)을 개략적으로 나타내는 단면도들이다.
먼저 도 1을 참조하면, 기판(10) 상에 회로 요소(20)가 형성된다. 비록 도면에는 회로 요소(20)가 단순한 사각 형태로 표현되었지만, 회로 요소(20)는 다양한 형상을 가질 수 있다. 예를 들어 회로 요소(20)는 메모리 소자의 게이트 구조물 또는 커패시터 구조물일 수도 있고, 이미지 소자의 포토다이오드 또는 구동 트랜지스터일수도 있다. 회로 요소(20)의 주변에는 절연층(30)이 형성될 수 있다.
비록 도면에는 회로 요소(20)가 기판(10)으로부터 돌출된 구조물로 도시되었지만, 회로 요소(20)는 기판(10) 내로 형성된 도핑 영역일 수도 있고, 기판(10) 내부에 형성된 구조물(예를 들어 매립된 게이트 구조물)일 수도 있다. 이 경우 절연층은 기판(10)에 포함되는 구성요소가 될 것이다.
도 2를 참조하면, 회로 요소(20) 상에 층간 절연층(1)이 형성된다. 층간 절연층(1)은 절연층(30) 상에 형성될 수 있다. 선택적인 실시예에서, 층간 절연층(1)은 절연층(30)과 동시에 형성될 수도 있다. 층간 절연층(1)의 두께는 비아 구조물에 적합한 두께를 얻도록 증착될 수 있다.
도 3을 참조하면, 층간 절연층(1)을 식각하여 회로 요소(20)를 노출시킨다. 도 3에는 이중 트렌치의 비아 홀 구조(즉, 상부 홀(UH)과 하부 홀(LH)의 두께가 다른 홀 구조)가 도시되었지만, 비아 홀 구조는 그에 제한되지 않음에 유의한다. 비아 홀 구조는 단일 트렌치의 형상을 가질 수도 있고, 다중 트렌치의 형상을 가질 수도 있다.
이중 트렌치의 비아 홀 구조를 형성하기 위해, 다음과 같은 공정이 이용될 수 있다.
- 제1 단계 : 층간 절연층(1) 상에 제1 두께의 오프닝을 갖는 제1 감광 패턴을 형성
- 제2 단계 : 상기 제1 감광 패턴을 마스크로 층간 절연층(1)을 1차 식각하여 상기 제1 두께를 갖는 상부 홀(UH)을 형성
- 제3 단계 : 상부 홀(UH)의 측벽과 접촉하며 상부 홀(UH) 하면 일부를 노출시키는 제2 감광 패턴을 형성
- 제4 단계 : 상기 제2 감광 패턴을 마스크로 층간 절연층(1)을 2차 식각하여 상기 제1 두께보다 작은 제2 두께를 갖는 하부 홀(LH)을 형성
- 제5 단계 : 상기 제2 감광 패턴(및 상기 제1 감광 패턴)을 제거
전술한 공정은 단지 예시일 뿐이며, 이중 트렌치의 비아 홀 구조를 형성하기 위해 다른 공정이 적용될 수도 있다. 예를 들어 층간 절연층(1)을 형성하는 공정 동안, 하부 층간 절연층을 형성하고, 상기 하부 층간 절연층 상에 제2 두께의 오프닝을 갖는 식각 저지층을 형성한 후, 식각 저지층 상에 상부 층간 절연층을 형성할 수 있다. 이 경우 상부 층간 절연층을 식각하면 식각 저지층 및 제2 두께의 오프닝이 노출되게 되는데, 식각 저지층 아래의 하부 절연층은 식각이 이루어지지 않지만 오프닝 아래의 하부 절연층은 식각된다. 따라서 상기 상부 층간 절연층에는 제1 두께를 갖는 상부 홀이 형성되고 상기 하부 층간 절연층에는 제2 두께를 갖는 하부 홀이 형성될 것이다.
도 4를 참조하면, 이중 트렌치의 비아 홀 상에 확산 방지층(3)을 형성한다. 확산 방지층(3)은 비아 구조물의 금속 원소가 주변의 층간 절연층(1)으로 확산하는 것을 방지하는 역할을 할 수 있다. 확산 방지층(3)은 예를 들어 Ta, TaN, Ti, TiN, W, WN, TaSiN, TiSiN, 및 WSiN 중 적어도 하나를 포함할 수 있다.
도 5를 참조하면, 확산 방지층(3) 상에 금속층(2)을 형성한다. 금속층(2)은 예를 들어 구리를 포함할 수 있고, 주변 물질과의 열팽창 계수 차를 고려하여 기타 다른 금속 물질로 형성될 수도 있다. 비록 도 5에 도시되지는 않았지만, 예를 들어 구리를 이용한 금속층(2) 형성 시 먼저 확산 방지층(3) 상에 구리 시드층이 형성되고, 상기 구리 시드층을 이용하여 금속층이 형성될 수도 있다.
도 6을 참조하면, 평탄화 공정(Planarization process)을 이용하여 금속층(2) 일부를 제거하여 금속층(2)의 상부 표면을 평탄화시킨다. 상기 평탄화를 위해 화학 기계 연마(Chemical Mechanical Polishing, CMP) 공정이 이용될 수 있다.
도 7 및 도 8을 참조하면, 평탄화 공정이 진행된 금속층(2) 상에 이중 층 구조의 캡핑층이 형성될 수 있다. 상기 캡핑층은 후속 배선 공정에서 건식 식각 가스, 수분(H2O), 산소(O2), 또는CMP등에 사용되는 수용성 화학종 등이 층간 절연층(1) 또는 구리 배선으로 확산/침투하는 것(in-diffusion)을 막는 역할을 할 수 있다.
상기 수분 혹은 산소가 층간 절연층(1)에 침투할 경우, 층간 절연층(1)의 유전율이 증가하고 RC 지연이 증가하면서 소자의 응답 속도가 감소하는 문제가 발생할 수 있다. 본 발명의 기술적 사상에 따르면, 상기 이중층 구조의 캡핑층을 도입함으로써, 그러한 문제가 방지될 수 있다. 또한, 캡핑층은 2개의 금속 층을 형성하기 위해 하부 금속층(2) 상에 상부 층간 절연층이 형성되는 경우, 하부 금속층(2)에서 상부 층간 절연층(1)으로 금속 성분이 확산(out-diffusion)되는 것을 막는 역할도 하며, 금속층(2)이 부식되는 것을 방지하는 역할도 수행할 수 있다.
본 발명자는, 기존의 SiCN 단일층으로 구성된 캡핑층이 소자의 크기가 감소함에 따라(그리고 캡핑층의 두께가 얇아짐에 따라) 수분이나 습기에 대한 차폐특성이 감소하게 된다는 문제점을 인식하고, 얇은 두께의 캡핑층에서도 우수한 차폐특성을 가질 수 있는 막을 증착하는 방법을 발명하였다.
이러한 방법의 일 예로서, 다음과 같은 공정이 수행될 수 있다.
- 금속층(2) 상에 제1 층(4)을 증착하는 단계(도 7 참조)
- 제1 층(4) 상에 제2 층(5)을 증착하는 단계(도 8 참조)
상기 제1 층(4) 및 제2 층(5)의 두께의 합은 100 Å 이하일 수 있다. 또한, 상기 제1 층(4) 및 제2 층(5)은 예를 들어 모두 질화층일 수 있다. 따라서, 본 발명의 기술적 사상에 따른 이중 층 구조의 캡핑층을 형성하는 단계는, 제1 질화층 및 제2 질화층을 증착하는 단계를 포함할 수 있다. 제1 질화층 및 제2 질화층은 순차로 증착될 수 있으며, 예를 들어 동일한 반응기에서 인-시튜(in-situ)로 형성될 수도 있다.
바람직한 실시예에서, 상기 제1 층(4)은 질화알루미늄(AlN) 층이고, 상기 제2 층(5)은 질화실리콘(SiN) 층일 수 있다. 예를 들어, 질화알루미늄(AlN) 층은 플라즈마 원자 층 증착법(PEALD)을 이용하여 형성될 수 있다. 또한, 질화실리콘(SiN) 층은 플라즈마 원자층 증착법(PEALD) 또는 펄스화된 플라즈마 화학 기상 증착법(Pulsed-PECVD, P-PECVD)을 이용하여 형성될 수 있다. 따라서 상기 캡핑층 형성 단계는 저온(예를 들어, 250 내지 350)의 온도 범위에서 진행될 수 있다.
PEALD 방법에서 전구체(precursor)와 플라즈마는 교대로, 단속적으로(intermittently) 반응기로 공급되는 과정을 반복할 수 있다. 한편 P-PECVD 방법에서는 플라즈마는 지속적으로 반응기로 공급되는 반면, 전구체(precursor)는 단속적으로(intermittently) 공급이 될 수 있다.
도 9는 본 발명의 기술적 사상에 의한 실시예들에 따른 금속 배선 형성 방법 및 반도체 제조 장치의 제조 방법을 개략적으로 나타내는 흐름도이다. 이 실시예들에 따른 제조 방법은 전술한 실시예들에 따른 제조 방법의 변형예일 수 있다. 이하 실시예들간 중복되는 설명은 생략하기로 한다.
도 9를 참조하면, 금속층(2) 상에 이중층 구조의 캡핑층을 형성하는 공정은 다음과 같은 단계로 수행될 수 있다.
제1 단계(S110) : 플라즈마 처리(plasma treatment),
제2 단계(S120) : PEALD에 의한 AlN 증착,
제3 단계(S130) : Pulsed PECVD에 의한 SiN증착
상기 제1 단계 내지 제3 단계(S110-S130)는 250내지 350의 온도 범위내의 동일 온도 조건에서 한 반응기에서 연속으로(in-situ) 진행한다.
먼저 제1 단계(S110)인 플라즈마 처리 공정은, 전공정 단계인 CMP (Chemical-Mechanical Planarization) 공정에서 금속층(2)(예를 들어, 구리 배선) 위에 형성된 산화금속(예를 들어, 산화 구리(CuO))을 금속(예를 들어, 구리(Cu))로 환원시키는 단계이다.
본 발명에서는 NH3, N2 및 H2의 혼합기체를 기판(10)이 탑재된 반응 공간으로 공급하면서 플라즈마를 활성화시킨다. 상기 플라즈마의 파워는 50W내지 300W의 범위일 수 있다. 상기 플라즈마 활성화에 의해 산화금속의 환원이 이루어짐과 동시에 평탄화된 금속층(도 6의 2) 표면에 잔류하는 공정 잔류물이 제거될 수 있다.
제1 단계(S110)는 플라즈마 활성화 단계 및 퍼지 단계의 사이클로 이루어지며, 본 실시예서는 상기 사이클을 1회만 진행하였다. 그러나 선택적인 실시예에서 상기 사이클은 복수 회 수행될 수도 있음에 유의한다.
상기 제1 단계(플라즈마 처리 단계)에서의 공정 조건을 요약하면 다음과 같다.
- 공정 온도 : 250 ~350
- 반응 기체 : N2/H2/NH3 (혼합 기체)
- 플라즈마 파워 : 100~300W
- 공정 압력 : 2~4 Torr
- 공정 시퀀스(sequence) : 플라즈마 점화(Plasma ignition) / 퍼지(Purge)
- 반복 횟수 : 1 사이클(cycle)
본 실시예에서는 반응 공간 내에서 플라즈마를 발생시키는 방법을 사용하였으나, 선택적인 실시예에 따르면, 리모트 플라즈마로 활성종을 생성시켜 상기 활성종이 반응 공간내로 공급됨으로써 플라즈마 처리 단계가 수행될 수도 있다.
제2 단계(S120)인 AlN 층 증착은 PEALD방법에 의해 진행된다. 본 실시예에서는, Al 소스로서 TMA(Trimethyl aluminum; Al(CH3)3)가 사용되었고 반응기체로는 N2/H2 혼합 기체가 사용되었다. AlN 층 증착은 TMA 공급 / 퍼지 / N2/H2 혼합 기체와 함께 플라즈마 공급 / 퍼지로 구성된 4단계를 일 사이클로 하여, 본 실시예에서는 AlN층이 20 Å의 두께가 될 때까지 상기 사이클을 18회 반복하였다. 본 실시예 에서는 상기 기본 사이클을18회 반복하였다.
상기 제2 단계(AlN 층 증착 단계)에서의 공정 조건을 요약하면 다음과 같다.
- 공정 온도 : 250 ~350
- 소스 기체 : TMA(trimethylaluminum)
- 반응 기체 : N2/H2 (혼합 기체)
- 퍼지 기체 : Ar
- 플라즈마 파워 : 200~400W
- 공정 압력 : 2~4 Torr
- 공정 시퀀스 : TMA 공급 / 퍼지 / 플라즈마 점화 / 퍼지
- 반복 횟수 : 18 사이클 (20 Å)
본 실시예에서는 반응 공간 내에서서 플라즈마를 발생시키는 방법을 사용하였으나, 전술한 바와 같이, 리모트 플라즈마로 활성종을 생성시켜 상기 활성종이 반응 공간내로 공급됨으로써 플라즈마 처리 단계가 수행되는 선택적인 실시예가 이용될 수도 있다.
제3 단계(S130)인 SiN 층 증착은 Pulsed PECVD 방법에 의해 진행된다. 본 실시예에서는 Si 소스로서 실란(SiH4)을 사용하였고 반응기체로는 N2/H2 혼합 기체를 사용하였다. 본 실시예에서, SiN 층 증착은 반응기체, 퍼지기체, 및 플라즈마를 지속적으로 공급하면서, 실란(SiH4)을 단속적으로 공급하였다. 바람직한 실시예에서, 실란(SiH4)은 0.2초간 공급되고, 퍼지기체는 2초간 공급하는 것을 1 사이클로 하여, SiN층이 30Å의 두께가 될 때까지 상기 사이클을 반복(50회)하였다.
상기 제3 단계(SiN 층 증착 단계)에서의 공정 조건을 요약하면 다음과 같다.
- 공정 온도 : 250 ~350
- 소스 기체 : SiH4
- 반응 기체 : N2/H2 (혼합 기체)
- 퍼지 기체 : Ar
- 플라즈마 파워 : 20-50W
- 공정 압력 : 2~4 Torr
- 공정 시퀀스 : SiH4 공급 / 퍼지
- 반복 횟수 : 50 사이클 (30Å)
본 실시예에서는 반응 공간 내에서서 플라즈마를 발생시키는 방법을 사용하였으나, 전술한 바와 같이, 리모트 플라즈마로 활성종을 생성시켜 상기 활성종이 반응 공간내로 공급됨으로써 플라즈마 처리 단계가 수행되는 선택적인 실시예가 이용될 수도 있다. 또한 본 실시예에 실란 계열의 소스기체로서 SiH4가 사용되었으나, SiH4 외에 다른 실란 계열의 소스 기체가 사용될 수 있다. 즉, 제3 단계(S130)의 소스 기체로서, 예를 들어 BDEAS(bisdiethylaminosilane), BEMAS(bisethylmethylaminosilane), DIPAS(diisoprophylaminosilane) 등을 포함하는 아미노실란(aminosilane)계열의 실리콘 소스기체, DCS(dichlorosilane), TCS(trichlorosilane), HCD(hexachlorodisilane)등을 포함하는 염화실란계열의 실리콘 소스 기체, 또는 이들의 조합이 사용될 수 있다.
전술한 실시예에 따르면, 캡핑층으로서 AlN/SiN이중 층 구조를 증착함으로써, 투습 방지 특성 평가시 우수한 특성을 확인할 수 있었다. 금속(구리) 배선 공정에서 저유전율 층간 절연층으로의 습기 침투 방지 및 구리의 층간 절연층으로의 확산이 방지될 수 있다. 즉, 발명자는 기존의 두꺼운 SiCN층 대신 얇은 AlN/SiN 층을 구현하고 이를 통해 우수한 투습 방지 특성을 확보함으로써, 소자크기가 축소됨에 따라 요구되는 100Å이하의 두께를 갖는 박막 형성이 달성될 수 있음을 발견하였다.
또한, 전술한 실시예에 따르면, 기존의 열공정(thermal process)대신 플라즈마 공정을 적용함으로써, 보다 저온에서 하부 저유전율(low-k) 층의 변형 및 손상이 최소화될 수 있다. 이외에 PEALD공정으로 막을 증착함으로써, 기존의 CVD에 의한 막보다 더욱 치밀하고 균일한 막을 증착할 수 있고, 보다 얇은 두께에서 보다 우수한 투습 방지 특성을 가진 박막을 증착할 수 있다. 이러한 효과를 보다 효율적으로 달성하기 위한 플라즈마 파워의 비율은 전술한 실시예에서 얻어진 수치와 같다. 즉, AlN 층 증착 단계 동안 공급되는 플라즈마 파워로서 200 내지 400W가 되고, SiN 층 증착 단계 동안 공급되는 플라즈마 파워로서 20 내지 50W가 되는 것이 그것이다. 발명자는 이러한 플라즈마 파워의 비율이 상기 AlN 층 증착 단계 동안 공급되는 플라즈마 파워 및 상기 SiN 층 증착 단계 동안 공급되는 플라즈마 파워의 비율로서 10:1 내지 8:1이 되는 것이 최적임을 발견하였다.
이외에도, 전술한 실시예에 따르면, 하나의 반응기에서 인-시튜(in-situ) 연속 공정으로 이중-층(bi-layer)을 증착함으로써, 대기에 노출 및 그에 의한 변형 없이 우수한 투습방지 특성을 가진 막이 증착될 수 있다.
도 10은 본 발명의 기술적 사상에 의한 실시예들에 따른 금속 배선 형성 방법 및 반도체 제조 장치의 제조 방법을 개략적으로 나타내는 흐름도이다. 이 실시예들에 따른 제조 방법은 전술한 실시예들에 따른 제조 방법의 변형예일 수 있다. 이하 실시예들간 중복되는 설명은 생략하기로 한다.
도 10을 참조하면, 제1 단계(S110)는 t0 내지 t2 시간 동안 이루어지는 플라즈마 처리(plasma treatment) 단계이다. 제1 단계(S110) 동안, CMP전공정(forward process)에 의해 금속배선(예를 들어, 구리배선) 표면 상에 형성된 산화금속(예를 들어, 산화구리)을 금속 원소로 환원시키는 과정이다.
예를 들어, 금속배선으로서 구리배선이 사용될 수 있고, 반응 기체로서 불활성 퍼지기체(예를 들어 N2)가 사용될 수 있다. 이 경우 소스기체(예를 들어 전구체)는 공급되지 않을 것이다.
선택적인 실시예에서, 반응 기체로서 NH3가 공급될 수 있고, 이를 플라즈마로 활성화시켜 산화구리가 환원될 수 있다. 이 경우 퍼지 기체가 별도로 공급될 수도 있을 것이다.
상기 제1 단계(S110)는 x회 반복될 수 있으나, 본 발명에 따른 한 실시예에서 상기 제1 단계(S110)는 1회만 진행되었다.
제2 단계(S120)는 t2 내지 t6 시간 동안 진행되는 PEALD 증착 공정이다. 상기 제2 단계(S120) 동안, 소스기체인 전구체(precursor) 및 반응기체(reactant)가 순차적으로 공급될 수 있다. 보다 구체적으로 t2 내지 t3 시간 동안 소스 기체가 공급되고, t4 내지 t5 시간 동안 반응 기체가 공급될 수 있다. 퍼지 기체는 t2 내지 t6 시간 동안 공급될 수 있다.
t4 내지 t5의 시간 동안 플라즈마가 공급되면서 반응기체가 활성화(activation)될 수 있고, 이렇게 활성화된 반응 기체는 미리 원자 층 단위의 두께로 증착된 소스기체와 반응하여 기판(10) 상에 막이 증착될 수 있다. 예시적인 실시예에서, 상기 제2 단계(S120) 동안, 소스기체로 TMA(trimethylaluminum; Al(CH3)3), 반응기체로 질소(N2)와 수소(H2)의 혼합기체 혹은 NH3를 사용하여 AlN층이 증착될 수 있다.
상기 t2 내지 t6시간 동안 이루어지는 단계들을 하나의 사이클로 하여, m회 반복하여 복수의 원자층이 증착될 수 있다. 바람직하게는, 상기 사이클이 반복되어 10 Å 이상의 두께를 갖는AlN층이 증착될 수 있다. 더욱 바람직하게는 AlN층은 20 Å 내지 30 Å의 두께를 갖도록 형성될 수 있다.
비록 도 10에는 상기 제2 단계(S120) 동안 반응 기체가 플라즈마가 공급되는 t4 내지 t5 시간 동안(즉, t4 이후에) 공급되는 것으로 도시되어 있지만, 상기 반응 기체는 플라즈마가 공급되는 시점인 t4 이전부터 공급될 수도 있다. 따라서, 반응 공간 내에 반응기체 밀도가 보다 균일해질 수 있다. 따라서, 상기 t4 이전의 시점에서 반응기체가 공급됨으로써, 반응공간 내에 활성종 밀도가 균일해지고 증착되는 막의 특성, 예를 들어 WERR(Wet Etch Rate Ratio)이 보다 균일해 질 수 있다.
일부 실시예들에서 퍼지 기체로서 아르곤(Ar) 등의 불활성 기체가 사용될 수 있다. 퍼지 기체는 t2내지 t6의 기간 동안 지속적으로 반응기로 공급될 수 있다. 이 경우 전술한 바와 같이 반응기체로서 질소(N2)와 수소(H2)의 혼합기체 혹은 암모니아(NH3)가 공급될 수 있다.
선택적인 실시예에서, 퍼지 기체로서 질소(N2)기체가 사용될 수도 있다. 질소 기체는 반응성 퍼지기체(reactive purge gas)로 사용될 수도 있고, 이 경우 질소 기체는 플라즈마가 공급될 때에만 활성화되어 소스기체와 반응을 하여 AlN층을 형성할 수 있다.
제3 단계(S130)는 SiN 박막을 증착하는 단계로서, 펄스화된(Pulsed) PECVD 방법을 이용하여 증착될 수 있다. 상기 펄스화된 PECVD 방법에 의한 증착은 제2 단계(S120)의 PEALD 방법에 의한 증착이 이루어지는 반응기와 동일한 반응기에서 인-시튜(in-situ)로 진행될 수 있다.
전술한 제2 단계(S120)에서 증착되는 AlN층은 대기에 노출시 산화될 수 있다. 따라서 동일한 반응기에서 계속적으로 제3 단계(S130)를 진행하여 AlN/SiN층이 인-시튜(in-situ)로 증착될 수 있다.
상기 제3 단계(S130)에서 반응기체, 퍼지기체 그리고 플라즈마는 t6 내지 t10시간 동안 지속적으로 공급되는 반면, 소스기체는 t7시간 동안 단속적으로 공급된다. 상기 t6 내지 t10기간을 일 사이클로 하여 상기 사이클을 n회 반복하면서 원하는 두께의 SiN 박막이 증착될 수 있다. 제3 단계(S130)에서, 반응기체로서 질소(N2)와 수소(H2)의 혼합기체 혹은 암모니아(NH3)가 사용될 수 있다. 일 실시예에서, SiN 박막은 30Å 이상의 두께로 증착될 수 있다. 바람직한 실시예에서, SiN 박막은 30Å 내지 60Å의 두께로 증착될 수 있다.
전술한 바와 같이 AlN 층은 20 Å 내지 30 Å의 두께를 갖고, SiN 박막은 30Å 내지 60Å의 두께를 가질 수 있으므로, AlN 층의 두께와 상기 SiN 층의 두께의 비율은 1:1.5 내지 1:2일 수 있다. 다만 이러한 AlN 층의 두께와 상기 SiN 층의 두께 그리고 이들 간의 비율은 100 Å 미만의 설계가 요구되는 공정조건을 충족하기 위해(그러면서도 우수한 차폐특성을 갖도록) 도입된 조건이다(도 13 참조). 따라서 본 발명의 기술적 사상에 따른 이중막 구조의 개별 두께(즉, 개별 층의 두께)가 전술한 수치에 제한되지 않음에 유의한다.
선택적인 실시예에서, 상기 제1 단계 내지 제3 단계(S110-S130) 동안, 공정 온도는 250~350 범위의 저온으로 유지될 수 있다. 따라서 다충 금속층 구조물을 형성하는 동안, 하부의 층간 절연층(특히 저유전율 층)의 손상이 방지될 수 있다. 또한, 상기 제1 내지 제3 단계들 동안 플라즈마가 인가됨으로써 반응속도가 빨라져, 기존의 열반응 공정(thermal ALD process) 대비 증착 속도가 개선되어 단위 시간당 생산성이 높아지는 효과가 달성될 수 있다. 또한 사이클 단위로 낮은 두께의 박막을 증착함으로써 박막 균일도가 개선될 수 있다.
도 11 및 도 12는 본 발명의 기술적 사상에 의한 또다른 실시예들에 따른 반도체 장치의 금속 배선 부분을 개략적으로 나타낸 단면도들이다. 이 실시예들에 따른 금속 배선 내지 금속 배선을 포함하는 반도체 장치는 전술한 실시예들에 따른 제조 방법이 적용되어 형성된 구조물일 수 있다. 이하 실시예들간 중복되는 설명은 생략하기로 한다.
도 11을 참조하면, 금속 배선은 예를 들어 구리 배선일 수 있고, 로직 소자 또는 메모리 소자에 적용될 수 있다. 상기 금속 배선은 저 유전율 층(low-k dielectric layer)인 층간 절연층(1), 금속층(2), 확산 방지층(3), 및 캡핑층을 포함할 수 있다.
층간 절연층(1)은 예를 들어 2.5 이하의 저유전율을 갖는 물질로 형성될 수 있고, 예를 들어 TEOS(tetra ethoxy ortho silicate; Si(C2H5O)4) 기반의 물질(예를 들어 SiOC, SICOH 등)을 포함할 수 있다. 층간 절연층(1)은 다공성 구조를 가질 수 있다. 층간 절연층(1)은 금속층(2)과 확산 방지층(3)의 측면을 둘러쌀 수 있다.
확산 방지층(3)은 전술한 바와 같이 금속층(2)의 금속 원소가 확산되어 층간 절연층(1)의 막질에 영향을 주는 것을 방지하는 역할을 수행할 수 있다. 금속층(2)은 알루미늄 내지 구리와 같은 배선층으로서, 확산 방지층(3)과 금속층(2)을 하나의 구성요소로 지칭할 수도 있을 것이다(예를 들어, 금속층(2)으로 지칭).
캡핑층은 전술한 바와 같이 제1 층(4) 및 제2 층(5)으로 구성된 이중층 구조이며, 제1 질화층(예를 들어 질화알루미늄 층) 및 제2 질화층(예를 들어 질화실리콘 층)을 포함할 수 있다. 제1 층은 금속층(2)의 적어도 일부(예를 들어, 상면) 및 층간 절연층(1)과 접촉할 수 있다. 상기 접촉은 직접적인 접촉(즉, 2개의 구성요소 사이에 여하의 구성요소가 없는 접촉)일 수 있다. 제2 층은 제1 층 상에 위치될 수 있고, 선택적인 실시예에서 제1 층과 제2 층이 인-시튜로 형성됨으로써 양자가 직접적으로 접촉할 수 있다.
도 12는 2층의 배선 구조를 나타낸 것으로 도 11의 배선 구조(즉, 제1 금속층(2)) 상에 추가 배선 구조(즉, 제2 금속층(2'))가 형성된 모습을 나타낸다.
도 12를 참조하면, 제2 금속층(2')은 제1 금속층(2) 상에 형성될 수 있다. 보다 구체적으로, 예를 들어 제1 층이 질화알루미늄 층이고 제2 층이 질화실리콘 층인 경우, 제2 금속층(2')은 상기 제1 금속층(2)의 상면, 상기 질화알루미늄 층의 측면, 및 상기 질화실리콘 층의 측면과 접촉할 수 있다.
비록 도 12와 본 실시예에서는 제2 금속층이 부재번호 2'로 지칭되었지만, 금속층(또는 제2 금속층)은 부재번호 2'에 제한되어 해석되지 않음에 유의한다. 예를 들어, 전술한 바와 같이 상기 제2 금속층은 금속을 포함하는 확산 방지층(3')을 포함하는 것으로 해석될 수도 있다. 이 경우 제2 금속층은 상기 제1 금속층(2)의 상면, 상기 질화알루미늄 층의 측면, 및 상기 질화실리콘 층의 측면과 직접 접촉할 수 있다.
도 13은 하부 기판 상에서 본 발명에 따른 이중 층 구조가 적절한 차폐 특성을 갖는지를 파악하기 위한 실험을 나타낸다. 하부의 기판은 전술한 실시예들에 따른 금속층과 확산 방지층 및 층간 절연층(특히 TEOS)으로 구성된 구조이다. 특히 TEOS의 경우 물을 아주 잘 흡수하는데, 이러한 수분의 흡수로 인해 하부 기판의 부피가 팽창하게 되어 압축 응력이 발생하게 된다(우하단 Fail 부분 참조).
투습을 방지하기 위한 캡핑층의 조건으로, 85의 온도 및 85%의 습도 분위기에 17시간 동안 노출될 경우, 기판의 스트레스의 변화가 50Mpa 미만이 되어야 한다. 일반적으로 캡핑층의 두께가 작아질수록 투습에 취약하며, 종래의 SiCN 캡핑층은 100 Å 이하의 두께로 구현될 경우 전술한 조건 하에서의 스트레스 변화 차이가 50 Mpa 미만이 되도록 하는 요건을 만족하지 못하였다.
그러나 본 발명의 기술적 사상에 의한 실시예들에 따르면, 서로 다른 물질의 이중 층 구조를 도입함으로써, 이러한 스트레스 변화 조건이 만족될 수 있도록 하였다.
아래 표 1은 도 13의 실험을 본 발명 기술적 사상에 의한 실시예들 중 일 실시예에 의해 형성된 이중층 구조(AlN 20Å / SiN 30Å)에 대해 수분(H2O)에 대한 투습 방지특성(hermetic feature)의 평가 결과를 보여 준다.
| Slot No. | AlN 두께 | SiN 두께 | Si 전구체 | 스트레스 변화(△MPa) | Pass/Fail |
| 01 | 20 | 30 | BDEAS | -38 | Pass |
| 02 | 20 | 40 | BDEAS | -40 | Pass |
| 03 | 20 | 30 | SiH4 | -4 | Pass |
| 04 | 20 | 40 | SiH4 | -5 | Pass |
위 표 1에서 알 수 있듯이, 기존 SiCN층의 경우 100Å두께 이하에서 투습 방지 특성이 저하되는 것과 비교할 때 본 발명은 그보다 낮은 두께에서도 우수한 투습 방지 특성을 나타냄을 알 수 있다.
본 발명을 명확하게 이해시키기 위해 첨부한 도면의 각 부위의 형상은 예시적인 것으로 이해하여야 한다. 도시된 형상 외의 다양한 형상으로 변형될 수 있음에 주의하여야 할 것이다.
이상에서 설명한 본 발명이 전술한 실시예 및 첨부된 도면에 한정되지 않으며, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것은, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
Claims (21)
- 저 유전층(low-k dielectric layer) 증착 단계;
상기 저 유전층에 트렌치(trench)를 형성하는 단계;
상기 트렌치에 배리어층(barrier layer)를 형성하는 단계;
상기 배리어 층 상에 금속을 충진하는 단계;
상기 금속에 대한 평탄화(planarization) 단계; 및
상기 평탄화된 금속 상에 캡핑층(capping layer)을 형성하는 단계;를 포함하고,
상기 캡핑층은 적어도 2개의 층을 포함하고, 100 Å이하의 두께를 갖는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 1에 있어서,
상기 캡핑층을 형성하는 단계는,
제1 질화층 및 제2 질화층을 증착하는 단계;를 포함하는 금속 배선 형성 방법. - 청구항 2에 있어서,
상기 제1 질화층 및 제2 질화층을 증착하는 단계는,
AlN 층 증착 단계; 및
SiN 층 증착 단계;를 포함하는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 3에 있어서,
상기 AlN 층은 플라즈마 원자 층 증착법(PEALD)을 이용하여 형성되는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 4에 있어서,
상기 AlN 층 증착 단계는 복수의 사이클들을 포함하고,
상기 복수의 사이클들 각각은,
Al 소스 기체 공급단계;
퍼지 기체 공급 단계;
반응 기체를 공급하고 플라즈마로 상기 반응 기체를 활성화하는 단계; 및
퍼지 기체 공급 단계;를 포함하고,
상기 퍼지 기체는 상기 사이클들 동안 반응 공간에 지속적으로 공급되는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 5에 있어서,
상기 Al 소스기체는 TMA(TriMethyl Aluminaum, Al(CH3)3)를 포함하고, 상기 반응 기체는 질소 및 수소의 혼합 기체를 포함하는 것을 특징으로 하는, 금속 배선 형성 방법. - 청구항 3 또는 청구항 4에 있어서,
상기 SiN 층은 펄스화된 플라즈마 화학 기상 증착법(pulsed PECVD)을 이용하여 형성되는 것을 특징으로 하는 금속 배선 형성 방법 - 청구항 7에 있어서,
상기 SiN 층 증착 단계는 복수의 사이클들을 포함하고,
상기 복수의 사이클들 각각은,
Si 소스 기체 공급 단계;
퍼지 기체 공급 단계;
반응 기체 공급하고 플라즈마로 상기 반응 기체를 활성화하는 단계; 및
퍼지 기체 공급 단계;를 포함하고,
상기 반응기체, 상기 퍼지 기체, 및 상기 플라즈마는 상기 사이클들 동안 반응 공간에 지속적으로 공급되는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 8에 있어서,
상기 Si 소스 기체는 Si와 H 원소를 포함하는 Si 소스 기체인 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 9에 있어서,
상기 Si 소스 기체는 SiH4, BDEAS(Bis(diethylamino) Silane), 및 DIPAS(Diisopropylamino Silane) 중 적어도 하나를 포함하는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 8에 있어서,
상기 반응 기체는 질소 및 수소의 혼합 기체를 포함하는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 3에 있어서,
상기 SiN 층의 두께는 적어도 30 옹스트롬인 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 3에 있어서,
상기 제1 질화층 및 제2 질화층을 증착하는 단계 전에 플라즈마 처리 단계를 포함하고,
상기 플라즈마 처리 단계는 적어도 하나의 사이클을 포함하며,
상기 사이클은,
질소 함유 기체 공급 단계;
플라즈마로 상기 질소 함유 기체를 활성화하는 단계; 및
퍼지 기체 공급 단계;를 포함하며,
상기 사이클에 의해, 금속 상부의 산화 금속이 금속으로 환원되는 것읕 특징으로 하는 금속 배선 형성 방법. - 청구항 3에 있어서,
상기 캡핑층 형성 단계는 250 ℃ 내지 350 ℃의 온도 범위에서 진행되는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 3에 있어서,
상기 제1 질화층 및 상기 제2 질화층은 동일한 반응기에서 인-시튜(in-situ)로 형성되는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 4에 있어서,
상기 AlN 층의 두께와 상기 SiN 층의 두께의 비율은 1:1.5 내지 1:2인 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 16에 있어서,
상기 AlN 층 및 상기 SiN 층을 포함하는 상기 캡핑층은, 섭씨 85도의 온도 및 85%의 습도 조건에서 17시간 동안 노출된 경우, 50MPa 이하의 박막 스트레스 변화량을 갖는 것을 특징으로 하는 금속 배선 형성 방법. - 청구항 4에 있어서,
상기 AlN 층 증착 단계 동안 공급되는 플라즈마 파워 및 상기 SiN 층 증착 단계 동안 공급되는 플라즈마 파워의 비율은 10:1 내지 8:1인 것을 특징으로 하는 금속 배선 형성 방법. - 저 유전층(low-k dielectric film) 증착 단계;
상기 저 유전층에 트렌치(trench)를 형성하는 단계;
상기 트렌치에 배리어 층(barrier film)을 형성하는 단계;
상기 배리어 층 상에 구리를 충진하여 구리층을 형성하는 단계;
상기 구리층에 대한 평탄화(planarization)를 수행하는 단계;
상기 평탄화된 구리층에 플라즈마를 인가하는 단계;
플라즈마 증강 원자층 증착(Plasma Enhanced Atomic Layer Deposition, PEALD) 방법을 이용하여, 상기 평탄화된 구리층 상에 AlN 층을 형성하는 단계; 및
상기 AlN 층을 형성한 반응기와 동일한 반응기에서 인-시튜(in-situ)로, 상기 AlN 층 상에 SiN 층을 형성하는 단계를 포함하고,
상기 AlN 층의 두께 및 상기 SiN 층의 두께의 합은 50 Å 내지 100 Å 이며,
상기 AlN 층의 형성 단계 및 상기 SiN 층의 형성 단계는 250 ℃ 내지 350 ℃의 온도범위에서 수행되는 것을 특징으로 하는, 반도체 장치의 제조 방법. - 반도체 장치의 제조 방법으로서,
제1 유전층을 형성하는 단계;
상기 제1 유전층 내에 제1 금속층을 형성하는 단계; 및
상기 제1 유전층 및 상기 제1 금속층 상에 100 Å 미만의 두께를 갖는 캡핑층을 형성하는 단계를 포함하고,
상기 캡핑층을 형성하는 단계는,
질화알루미늄 층을 형성하는 제1 단계; 및
상기 질화알루미늄 층 상에 질화실리콘 층을 형성하는 제2 단계를 포함하는 것을 특징으로 하는, 방법. - 제1 금속층;
상기 제1 금속층의 측면을 둘러싸는 제1 유전층;
상기 제1 금속층의 적어도 일부 및 상기 제1 유전층과 접촉하는 질화알루미늄 층;
상기 질화알루미늄 층 상의 질화실리콘 층;
상기 제1 금속층의 상면, 상기 질화알루미늄 층의 측면, 및 상기 질화실리콘 층의 측면과 접촉하는 제2 금속층; 및
상기 제2 금속층의 측면을 둘러싸는 제2 유전층을 포함하고,
상기 질화알루미늄 층의 두께 및 상기 질화실리콘 층의 두께의 합은 100 Å 미만인 것을 특징으로 하는, 반도체 장치.
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| US10249577B2 (en) | 2019-04-02 |
| TW201806081A (zh) | 2018-02-16 |
| CN107393867A (zh) | 2017-11-24 |
| TWI643292B (zh) | 2018-12-01 |
| US20170338192A1 (en) | 2017-11-23 |
| CN107393867B (zh) | 2019-03-19 |
| KR102592471B1 (ko) | 2023-10-20 |
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