본 발명은 반도체 장치에 관한 것으로서, 더욱 상세하게는 2개의 반도체 칩이 인쇄회로기판에 실장되고 외부 접속 단자로서 솔더 볼을 갖는 멀티 칩 패키지와 이와 같은 멀티 칩 패키지들이 적층되어 형성된 적층 패키지에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a multi-chip package in which two semiconductor chips are mounted on a printed circuit board and having solder balls as external connection terminals, and a multi-layer package formed by stacking such multi-chip packages. .
최근 휴대 가능한 전자제품의 수요가 급속하게 늘어나면서 반도체 제품 경향 또한 박형화, 소형화, 및 경량화의 요구가 증대되고 있으며, 대용량의 데이터 저장을 위한 고 집적도의 요구도 급증하고 있다. 이러한 요구를 만족시키기 위해서 무엇보다도 일정한 면적에서 대용량의 집적도를 확보할 수 있도록 미세 회로 가공기술이 발달되어야 한다. 그러나, 미세 회로 가공 기술의 한계로 인하여 새로운 방안으로 제안된 것이 멀티 칩 패키지(multi chip package)와 적층 패키지(stack package)이다.Recently, as the demand for portable electronic products is rapidly increasing, the trend of semiconductor products is also increasing in demand for thinning, miniaturization, and lightening, and the demand for high integration for storing large amounts of data is rapidly increasing. In order to satisfy these demands, the microcircuit processing technology must be developed to secure a high density of integration in a certain area. However, due to the limitations of the microcircuit processing technology, new solutions have been proposed as multi chip packages and stack packages.
멀티 칩 패키지는 1개의 패키지 내에 2개 이상의 반도체 칩을 탑재하여 멀티 기능 및 고용량화를 구현시킨 반도체 칩 패키지이다. 멀티 칩 패키지는 특히 소형화와 경량화가 요구되는 휴대용 전화기 등에서 실장면적의 축소와 경량화를 위해 많이 적용되고 있다. 그리고, 적층 패키지는 2개 이상의 단위 반도체 칩 패키지를 전기적으로 서로 연결하여 고집적도를 구현시킨 반도체 칩 패키지이다. 멀티 칩 패키지나 적층 패키지는 각각의 반도체 소자를 내재하는 단위 반도체 칩 패키지 두 개를 이용하는 것보다 크기나 무게 및 실장면적에서 소형화와 경량화에 유리하다.The multi chip package is a semiconductor chip package in which two or more semiconductor chips are mounted in one package to realize multi-function and high capacity. Multi-chip packages are being applied to reduce the mounting area and light weight, especially in portable telephones that require miniaturization and light weight. The stack package is a semiconductor chip package in which two or more unit semiconductor chip packages are electrically connected to each other to realize high integration. Multi-chip packages or stacked packages are advantageous in size and weight in terms of size, weight, and mounting area, rather than using two unit semiconductor chip packages incorporating each semiconductor device.
멀티 칩 패키지는 일반적으로 복수 개의 반도체 소자를 적층시키는 방법과 병렬로 배열시키는 방법이 있다. 전자의 경우 반도체 소자를 적층시키는 구조이므로 공정이 복잡하고 한정된 두께에서 안정된 공정을 확보하기 어려운 단점이 있고, 후자의 경우 평면상에 두 개의 반도체 칩을 배열시키는 구조이므로 크기 감소에 의한 소형화의 장점을 얻기가 어렵다. 보통 소형화와 경량화가 필요한 패키지에 적용되는 형태로서 반도체 소자를 적층하는 형태가 많이 사용된다. 이와 같은 형태의 멀티 칩 패키지의 예를 소개하면 다음과 같다.In general, a multi-chip package has a method of stacking a plurality of semiconductor devices and a method of arranging them in parallel. The former has a disadvantage in that it is difficult to secure a stable process at a limited thickness due to the structure of stacking semiconductor elements. Difficult to obtain Usually, as a form applied to a package requiring miniaturization and light weight, a form of stacking semiconductor elements is frequently used. An example of such a multi-chip package is as follows.
도 1은 종래 기술에 따른 멀티 칩 패키지의 일 예를 나타낸 단면도이다.1 is a cross-sectional view showing an example of a multi-chip package according to the prior art.
도 1을 참조하면, 이 멀티 칩 패키지(110)는 제 1반도체 칩(111)과 제 2반도체 칩(113)이 다이패드(123)의 상면과 하면에 각각 부착되어 있고, 제 1반도체 칩(111)의 전극패드(112)와 제 2반도체 칩(113)의 전극패드(114)가 다이패드(123)와 소정의 간격으로 이격되어 있는 리드(121)의 내측 말단 부분의 상면과 하면에 도전성 금속선(131,132)으로 와이어 본딩(wire bonding)되어 전기적인 연결을 이루고 있으며, 외부환경으로부터의 보호를 위하여 에폭시 성형 수지(EMC; epoxy molding compound)와 같은 플라스틱 봉지재로 패키지 몸체(140)가 형성되어 있는 구조이다. 패키지 몸체(140)의 외부로 돌출된 외부리드(122)는 실장에 적합한 형태로 성형되어 있다.Referring to FIG. 1, in the multi-chip package 110, a first semiconductor chip 111 and a second semiconductor chip 113 are attached to the top and bottom surfaces of the die pad 123, respectively. The electrode pads 112 of the 111 and the electrode pads 114 of the second semiconductor chip 113 are electrically conductive on the upper and lower surfaces of the inner end portions of the leads 121 spaced apart from the die pads 123 at predetermined intervals. The wire bonding (wire bonding) to the metal wires (131,132) to form an electrical connection, the package body 140 is formed of a plastic encapsulant such as epoxy molding compound (EMC) for protection from the external environment It is a structure. The outer lead 122 protruding to the outside of the package body 140 is molded in a shape suitable for mounting.
이와 같은 멀티 칩 패키지는 많은 비용과 개발 기간이 소요되는 미세 회로 가공 기술을 통한 집적도 증가보다는 저비용 및 단기간에 개발이 가능하다는 것과 기존의 플라스틱 패키지 공정을 100% 활용할 수 있다는 장점을 가지고 있다. 그러나, 전술한 바와 같은 멀티 칩 패키지의 경우 리드프레임을 이용하고 있기 때문에 실장면적 축소나 열 방출 문제 및 집적도 증가에 따른 입출력 핀 수의 증가에 대응할 수 없다.Such a multi-chip package has the advantage of being able to be developed at low cost and in a short time rather than increasing the density through the micro-circuit processing technology, which requires a lot of cost and development time, and can utilize 100% of the existing plastic package process. However, since the above-described multi-chip package uses a lead frame, it cannot cope with an increase in the number of input / output pins due to a reduction in mounting area, heat dissipation, and an increase in integration.
따라서 본 발명의 목적은 일정한 면적에서 대용량 밀도를 확보함과 동시에 상기 문제점들을 해결한 인쇄회로기판을 이용하는 볼 그리드 어레이형 멀티 칩 패키지와 적층 패키지를 제공하는 데에 있다.Accordingly, an object of the present invention is to provide a ball grid array type multi-chip package and a laminated package using a printed circuit board which solves the above problems while securing a high density in a certain area.
도 1은 종래 기술에 따른 멀티 칩 패키지의 일 예를 나타낸 단면도,1 is a cross-sectional view showing an example of a multi-chip package according to the prior art,
도 2는 본 발명에 따른 멀티 칩 패키지의 실시예를 나타낸 단면도,2 is a cross-sectional view showing an embodiment of a multi-chip package according to the present invention;
도 3은 본 발명에 따른 적층 패키지의 실시예를 나타낸 단면도이다.3 is a cross-sectional view showing an embodiment of a laminated package according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; 멀티 칩 패키지11,15; 반도체 칩10; Multi-chip packages 11 and 15; Semiconductor chip
12,16; 전극패드13,17; 범프(bump)12,16; Electrode pads 13 and 17; Bump
20; 인쇄회로기판21; 베이스 기판20; A printed circuit board 21; Base substrate
22,26; 회로배선23,27; 접합패드22,26; Circuit wiring 23,27; Bonding pad
24,28; 볼 랜드패드25; 비아 홀(via hole)24,28; Ball land pad 25; Via hole
31,32; 보호막41,42; 봉지부31,32; Protective films 41 and 42; Encapsulation
45; 솔더 볼(solder ball)50; 적층 패키지45; Solder ball 50; Laminated package
이와 같은 목적을 달성하기 위한 본 발명에 따른 볼 그리드 어레이형 멀티 칩 패키지는 베이스 기판의 상면과 하면에 각각 소정의 회로배선과 그와 연결되어 형성된 접합패드 및 상면의 회로배선과 하면의 회로배선을 전기적으로 연결하는 비아 홀(via hole)이 형성되어 있는 인쇄회로기판과, 집적회로가 형성된 활성면에 복수의 전극패드와 그 전극패드에 접합되어 형성된 범프를 갖는 제 1칩과 제 2칩을 구비하고 있으며, 제 1칩의 범프가 인쇄회로기판의 상면에 형성된 접합패드에 접합되어 있고 제 2칩의 범프가 인쇄회로기판의 하면에 형성된 접합패드에 접합되어 있고, 인쇄회로기판의 일면에 형성된 회로배선과 전기적으로 연결되는 솔더 볼이 부착되어 있는 것을 특징으로 한다. 제 1칩과 제 2칩이 인쇄회로기판의 상면과 하면에 각각 플립 칩 본딩(flip chip bonding)되고 외부 접속 단자로서 인쇄회로기판 일면 전체에 배치될 수 있는 솔더 볼을 채택하고 있어서 보다 많은 용량 및 입출력 핀 수가 필요한 반도체 제품에 적용이 가능하다. 플립 칩 본딩으로 제 1칩과 제 2칩이 실장되기 때문에 실장 높이가 높지 않아 솔더 볼의 실장 높이 보다 낮을 수 있다. 따라서, 솔더 볼의 채택이 가능하다.The ball grid array multi-chip package according to the present invention for achieving the above object has a predetermined circuit wiring on the upper surface and the lower surface of the base substrate and the bonding pad and circuit wiring of the upper surface and the lower surface, respectively. A printed circuit board having a via hole for electrically connecting the first chip and a second chip having a plurality of electrode pads and bumps formed by bonding the electrode pads to an active surface on which an integrated circuit is formed; A bump of the first chip is bonded to a bonding pad formed on the upper surface of the printed circuit board, a bump of the second chip is bonded to a bonding pad formed on the lower surface of the printed circuit board, and a circuit formed on one surface of the printed circuit board It is characterized in that the solder ball is electrically connected to the wiring. The first and second chips are flip chip bonded to the upper and lower surfaces of the printed circuit board, respectively, and adopt solder balls that can be disposed on one surface of the printed circuit board as external connection terminals. It can be applied to semiconductor products that need input / output pin count. Since the first chip and the second chip are mounted by flip chip bonding, the mounting height is not high and may be lower than the mounting height of the solder ball. Therefore, the solder ball can be adopted.
이와 같은 본 발명에 따른 멀티 칩 패키지에 있어서, 제 1칩과 인쇄회로기판, 제 2칩과 인쇄회로기판의 사이에는 전기적인 연결 상태를 외부환경으로부터 보호하기 위하여 봉지부가 형성되는 것이 바람직하며, 수지 봉지재의 포팅(potting)에 의해 용이하게 형성될 수 있다. 이때, 봉지부는 제 1칩과 제 2칩의 배면이 노출되도록 하면 열 방출 효과가 향상될 수 있다.In the multi-chip package according to the present invention, it is preferable that an encapsulant is formed between the first chip and the printed circuit board, and the second chip and the printed circuit board to protect the electrical connection state from the external environment. It can be easily formed by potting the encapsulant. In this case, when the encapsulation part exposes the back surfaces of the first chip and the second chip, the heat dissipation effect may be improved.
그리고, 상기 목적을 달성하기 위한 본 발명에 따른 적층 패키지는, 전술한 바와 같은 본 발명에 따른 단위 멀티 칩 패키지 복수 개가 각각의 멀티 칩 패키지의 하면에 형성된 솔더 볼이 다른 멀티 칩 패키지의 상면에 형성된 회로배선과 전기적으로 연결되도록 부착된 것을 특징으로 한다.In addition, in the multilayer package according to the present invention for achieving the above object, a plurality of unit multi-chip package according to the present invention as described above is formed on the upper surface of the multi-chip package different solder balls formed on the lower surface of each multi-chip package It is characterized in that it is attached so as to be electrically connected to the circuit wiring.
이하 첨부 도면을 참조하여 본 발명에 따른 볼 그리드 어레이형 멀티 칩 패키지와 적층 패키지를 보다 상세하게 설명하고자 한다.Hereinafter, a ball grid array type multi chip package and a stack package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 멀티 칩 패키지의 실시예를 나타낸 단면도이다.2 is a cross-sectional view showing an embodiment of a multi-chip package according to the present invention.
도 2를 참조하면, 이 멀티 칩 패키지(10)는 인쇄회로기판(20)의 상면과 하면에 각각 제 1칩(11)과 제 2칩(15)이 플립 칩 본딩 기술이 적용되어 부착되어 있고 외부 접속 단자로서 솔더 볼(45)이 인쇄회로기판(20)의 하면에 부착되어 있는 구조를 갖는다. 구조를 좀 더 상세하게 살펴보기로 한다.Referring to FIG. 2, in the multi-chip package 10, the first chip 11 and the second chip 15 are attached to the upper and lower surfaces of the printed circuit board 20 by flip chip bonding technology. As an external connection terminal, the solder ball 45 is attached to the lower surface of the printed circuit board 20. Let's look at the structure in more detail.
인쇄회로기판(20)은 베이스 기판(21)의 상면과 하면에 구리 박막이 입혀진 후에 식각 공정을 거쳐 소정의 회로배선(22)과 접합패드(23,27) 및 볼 랜드패드(ball land pad; 24,28)가 형성되어 있다. 볼 랜드패드(24,28)는 접합패드(23,27)의 외측 영역에 형성되어 있다. 회로배선(22,26)과 접합패드(23,27) 및 볼 랜드패드(24,28)는 서로 연결되어 형성되어 전기적으로 상호 연결된다. 상면의 회로배선(22)과 하면의 회로배선(26)은 베이스 기판(21)을 관통하는 구멍에 도금 과정을 거쳐 내벽이 도금된 비아 홀(25)에 의해 서로 도통된다. 여기서, 접합패드(23,27)는 제 1칩(11)과 제 2칩(15)의 전극패드(12) 배열 상태에 대응되도록 형성되고, 볼 랜드패드(24,28)는 솔더 볼(45)의 배치 설계 구조에 따라 형성된다. 한편, 보호가 필요한 회로배선(22,26)들은 솔더 레지스트(solder resist)로 형성되는 보호막(31,32)에 의해 외부환경으로부터 보호된다.The printed circuit board 20 may include a predetermined circuit wiring 22, bonding pads 23 and 27, and ball land pads through an etching process after a thin copper film is coated on the top and bottom surfaces of the base substrate 21; 24, 28) are formed. The ball land pads 24 and 28 are formed in the outer region of the bonding pads 23 and 27. The circuit wirings 22 and 26, the bonding pads 23 and 27, and the ball land pads 24 and 28 are formed to be connected to each other and electrically connected to each other. The upper circuit wiring 22 and the lower circuit wiring 26 are connected to each other by the via hole 25 having the inner wall plated through a plating process in the hole penetrating the base substrate 21. Here, the bonding pads 23 and 27 are formed to correspond to the arrangement state of the electrode pads 12 of the first chip 11 and the second chip 15, and the ball land pads 24 and 28 are solder balls 45. ) Is formed according to the layout design structure. On the other hand, the circuit wirings 22 and 26 which need to be protected are protected from the external environment by the protective films 31 and 32 formed of solder resists.
제 1칩(11)과 제 2칩(15)은 집적회로가 형성된 활성면의 가장자리에 복수 개의 전극패드(12,16)가 형성되어 있는 에지 패드(edge)형으로서 플립 칩 본딩을 위하여 전극패드912,16)에 범프(13,17)가 형성되어 있는 것이다. 범프(13,17)로서는 공지된 솔더 범프(solder bump), 일렉트로-플레이팅 범프(electro-plating bump), 일렉트로레스 범프(electroless bump), 및 금 스터드 범프(Au stud bump) 등이 적용 가능하다.The first chip 11 and the second chip 15 are edge pads having a plurality of electrode pads 12 and 16 formed on the edge of the active surface on which the integrated circuit is formed. Bumps 13 and 17 are formed at 912 and 16. As the bumps 13 and 17, known solder bumps, electro-plating bumps, electroless bumps, gold stud bumps, and the like are applicable. .
제 1칩(11)은 인쇄회로기판(20) 상면의 접합패드(23)에 범프가 접합되어 실장되어 있고 제 2칩(15)은 인쇄회로기판(20) 하면의 접합패드(27)에 범프(17)가 접합되어 인쇄회로기판(20)에 실장되어 있다. 이와 같은 플립 칩 본딩 상태는 제 1칩(11)과 인쇄회로기판(20)의 사이와 제 2칩(15)과 인쇄회로기판(20)의 사이에 형성되는 봉지부(41,42)에 의해 결합력이 강화되고 전기적인 연결 상태가 외부 환경으로부터 보호된다. 이때, 제 1칩(11)과 제 2칩(15)의 배면은 열 방출에 유리하도록 노출되어 있다. 한편, 봉지부(41,42)는 사용되는 범프(23,27)에 따라 변화될 수 있다. 솔더 범프가 사용될 경우 에폭시 성형 수지와 같은 언더-필(under-fill)재가 사용될 수 있고 일렉트로-플레이팅 범프, 일렉트로레스 범프, 금 스터드 범프 등이사용될 경우 이방성 전도 접착제(anisotrpic conductive adhesive; ACA)나 이방성 전도 필름(anisotropic conductive film; ACF) 등과 같은 페이스트(paste) 또는 시이트형(sheet type)의 여러 가지 종류의 접착 수단의 적용이 가능하다.The first chip 11 is bump-bonded to the bonding pad 23 on the upper surface of the printed circuit board 20, and the second chip 15 is bumped on the bonding pad 27 on the lower surface of the printed circuit board 20. 17 are bonded and mounted on the printed circuit board 20. The flip chip bonding state is formed by the encapsulation portions 41 and 42 formed between the first chip 11 and the printed circuit board 20 and between the second chip 15 and the printed circuit board 20. Bonding strength is enhanced and electrical connections are protected from the external environment. At this time, the back surfaces of the first chip 11 and the second chip 15 are exposed to favor heat dissipation. Meanwhile, the encapsulation portions 41 and 42 may vary depending on the bumps 23 and 27 used. If solder bumps are used, an under-fill material such as an epoxy molding resin may be used, and if an electro-plating bump, electroless bumps, gold stud bumps, etc. are used, then anisotropic conductive adhesive (ACA) or It is possible to apply various kinds of bonding means, such as paste or sheet type, such as an anisotropic conductive film (ACF).
칩 실장, 예컨대 금 스터드 범프가 형성된 칩 실장은 이방성 전도 필름이 부착되어 있는 상태에서 제 1칩과 제 2칩의 범프와 인쇄회로기판의 접합패드를 일치시킨 후 150~200℃의 온도로 열압착을 통하여 이루어질 수 있다.Chip mounting, for example, chip mounting with gold stud bumps, is thermally compressed to a temperature of 150 to 200 ° C. after matching the bumps of the first chip and the second chip with the bonding pads of the printed circuit board with the anisotropic conductive film attached thereto. It can be done through.
도 3은 본 발명에 따른 적층 패키지의 일 실시예를 나타낸 단면도이다.3 is a cross-sectional view showing an embodiment of a laminated package according to the present invention.
도 3을 참조하면, 이 적층 패키지(50)는 복수의 반도체 칩(11a,15a,51a,55b)이 인쇄회로기판(20a,20b)에 플립 칩 본딩되어 있는 볼 그리드 어레이형 멀티 칩 패키지(10a,10b) 복수 개가 적층된 구조로서 상부에 위치한 멀티 칩 패키지(10a)의 솔더 볼(45a)을 매개로 하여 패키지간 전기적인 연결이 이루어진다. 여기서, 단위 볼 그리드 어레이형 멀티 칩 패키지(10a,10b)의 구조는 전술한 바와 동일한 구조이므로 설명을 생략하기로 한다.Referring to FIG. 3, the stacked package 50 includes a ball grid array type multi-chip package 10a in which a plurality of semiconductor chips 11a, 15a, 51a, and 55b are flip chip bonded to a printed circuit board 20a and 20b. 10b) A plurality of stacked structures are electrically connected between the packages through the solder balls 45a of the multi-chip package 10a. Here, since the structure of the unit ball grid array type multi-chip package 10a, 10b is the same structure as described above, a description thereof will be omitted.
각각의 단위 멀티 칩 패키지(10a)는 상면의 볼 랜드패드(24a,24b)가 하면에 볼 랜드패드(28a,28b)가 동일한 배열 형태를 이루도록 형성되어 있고 하면의 볼 랜드패드(28a,28b)에 솔더 볼(45a,45b)이 부착되어 있으므로 복수의 멀티 칩 패키지(10a,10b)를 적층할 경우 상면에 형성된 볼 랜드패드(42a,42b)를 이용할 수 있다. 즉, 상부에 위치한 멀티 칩 패키지(10a)의 솔더 볼(45a)과 하부에 위치한 멀티 칩 패키지(10b)의 상면에 형성된 볼 랜드패드(24b)가 접합되도록 하여 전기적 및 물리적인 연결이 이루어져 적층 패키지가 완성될 수 있다.Each of the unit multi-chip packages 10a is formed such that the ball land pads 24a and 24b on the upper surface of the unit multi chip package 10a have the same arrangement as the ball land pads 28a and 28b on the lower surface of the unit multi-chip package 10a. Since the solder balls 45a and 45b are attached to each other, the ball land pads 42a and 42b formed on the upper surface may be used when the plurality of multi-chip packages 10a and 10b are stacked. In other words, the solder ball 45a of the multi-chip package 10a disposed at the upper portion and the ball land pad 24b formed at the upper surface of the multi-chip package 10b disposed at the lower portion are bonded to each other, thereby making electrical and physical connection to form a stacked package. Can be completed.
단위 멀티 칩 패키지의 적층은 어느 하나의 멀티 칩 패키지의 상면에 형성된 볼 랜드패드 부분에 플럭스를 도포하고 멀티 칩 패키지들의 위치 정렬 후에 리플로우(reflow) 공정을 거쳐 용이하게 이루어질 수 있다. 여기서, 적층 패키지는 단위 멀티 칩 패키지 2개가 적층된 것을 소개하고 있으나 2개 이상의 멀티 칩 패키지로 이루어진 적층 패키지의 구현도 가능하다.Stacking of the unit multi-chip package may be easily performed by applying flux to the ball land pad portion formed on the upper surface of any one of the multi-chip packages and reflowing after alignment of the multi-chip packages. Here, the stack package is introduced by stacking two unit multi-chip packages, but it is also possible to implement a stack package consisting of two or more multi-chip packages.
이와 같은 적층 패키지는 리드프레임을 채택한 적층 패키지에 비하여 크기 면에서 유리하고 1개의 칩으로 이루어진 반도체 칩 패키지가 적층되어 구성되는 적층 패키지에 비해 용량이 2배가될 수 있다.Such a stack package is advantageous in size compared to a stack package adopting a lead frame, and may have a capacity doubled compared to a stack package in which a semiconductor chip package including one chip is stacked.
이상과 같은 본 발명에 의한 볼 그리드 어레이형 멀티 칩 패키지와 적층 패키지에 따르면, 일정한 면적에서 용량이 향상될 수 있다. 예컨대, 동일한 반도체 칩 두 개를 내재하여 용량이 2배가 될 수 있다. 또한, 인쇄회로기판을 이용하고 있기 때문에 실장면적 축소나 열 방출 문제 및 집적도 증가에 따른 입출력 핀 수의 증가에 효과적으로 대응할 수 있다.According to the ball grid array type multi-chip package and the stack package according to the present invention as described above, the capacity can be improved in a constant area. For example, the capacity may be doubled by embedding two identical semiconductor chips. In addition, since the printed circuit board is used, it is possible to effectively cope with the increase in the number of input / output pins due to the reduction of the mounting area, the heat dissipation problem, and the increase in the density.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010002828AKR20020061812A (en) | 2001-01-18 | 2001-01-18 | Ball grid array type multi chip package and stack package |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010002828AKR20020061812A (en) | 2001-01-18 | 2001-01-18 | Ball grid array type multi chip package and stack package |
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| KR20020061812Atrue KR20020061812A (en) | 2002-07-25 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010002828AWithdrawnKR20020061812A (en) | 2001-01-18 | 2001-01-18 | Ball grid array type multi chip package and stack package |
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| KR (1) | KR20020061812A (en) |
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