본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 5층 배선(3P-2M)구조의 TFT SRAM(Thin Film Transistor Static Random Access Memory) 셀의 레이아웃 (Layout) 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a layout of a TFT SRAM (Thin Film Transistor Static Random Access Memory) cell having a 5-layer wiring (3P-2M) structure and a method of manufacturing the same.
일반적으로, SRAM의 단위셀은 6개의 트랜지스터(6T)로 구성되는데, 구동트랜지스터(Drive transistor), 엑세스트랜지스터(Access transistor), 부하소자(Load element)로 구성된다.In general, the unit cell of the SRAM is composed of six transistors 6T, which is composed of a drive transistor, an access transistor, and a load element.
여기서, 상기 구동트랜지스터 및 엑세스트랜지스터는 NMOS를 이용하며, 상기 부하소자는 저항, PMOS, FCMOS(Full CMOS), 폴리실리콘부하소자(Polysilicon load) 또는 TFT(Thin Film Transistor)를 이용한다.Here, the driving transistor and the exciter transistor use an NMOS, and the load device uses a resistor, a PMOS, a full CMOS, a polysilicon load, or a thin film transistor (TFT).
최근에는 저전력, 대용량 메모리소자를 구현하기 위해 TFT를 부하소자로 적용하고 있다.Recently, TFTs have been applied as load devices to realize low power and high capacity memory devices.
상기와 같이 구성되는 SRAM의 단위셀에 있어서, 각 트랜지스터의 배치 및 형태는 소자마다 다르며, 특히, 부하소자인 TFT를 배치하기 위한 방법은 게이트의 위치에 따라 하부게이트(Bottom gate) TFT, 탑게이트(Top gate) TFT, 더블게이트 (Double gate) TFT로 다양하게 구분된다. 또한, 워드라인(Wordline; WL), 정비트라인(BL), 부비트라인(/BL), VCC라인, VSS라인을 구성하는 방법에 있어서도 다양한 형태의 셀 형태가 있다.In the unit cell of the SRAM configured as described above, the arrangement and shape of each transistor are different for each element, and in particular, a method for arranging TFTs as load elements is a bottom gate TFT and a top gate depending on the position of the gate. (Top gate) TFT, Double gate TFT is divided into various. In addition, there are various cell types in the method of configuring a word line (WL), a positive bit line (BL), a sub bit line (/ BL), a VCC line, and a VSS line.
도 1은 일반적인 TFT SRAM 셀의 등가회로도로서, 부하소자로서 P형 TFT(T1, T2)를 연결하고, 각각 게이트에 워드라인(WL)이 연결되고 드레인에 정비트라인(BL) 또는 부비트라인(/BL)이 연결된 엑세스트랜지스터(Q1, Q2), 상기 TFT(T1, T2)의 일측과 상기 엑세스트랜지스터(Q1, Q2)의 소스단이 공통으로 연결된 정셀노드 및 부셀노드(N1, N2)에 드레인단이 연결되고 상기 드레인단이 게이트에 서로 교차연결된 구동트랜지스터(Q3, Q4)로 구성된다. 그리고, 상기 TFT(T1, T2)의 타측은 전원전압(VCC)이 인가되고, 상기 구동트랜지스터(Q3, Q4)의 소스단에는 접지전원 (VSS)이 인가된다.1 is an equivalent circuit diagram of a typical TFT SRAM cell, in which a P-type TFT (T1, T2) is connected as a load element, a word line WL is connected to a gate, and a positive bit line BL or a sub bit line at a drain. To the positive cell node and the sub cell node N1 and N2 in which (/ BL) are connected to the common transistors Q1 and Q2 and one side of the TFTs T1 and T2 and the source terminal of the access transistors Q1 and Q2 are connected in common. A drain terminal is connected and the drain terminal is composed of drive transistors Q3 and Q4 cross-connected to each other. A power supply voltage VCC is applied to the other side of the TFTs T1 and T2, and a ground power supply VSS is applied to the source terminal of the driving transistors Q3 and Q4.
도 2는 종래기술에 따른 TFT SRAM의 레이아웃도로서, 종래기술에 따른 TFT SRAM은 셀의 상하부, 좌우 대칭구조를 갖는다.2 is a layout diagram of a TFT SRAM according to the prior art, and the TFT SRAM according to the prior art has a top and bottom, left and right symmetry structure of a cell.
도 2a에 도시된 바와 같이, 반도체기판(11)에 소자분리마스크를 이용하여 필드산화막(12)을 형성하여 활성영역(11a)을 정의한 후, 상기 반도체기판(11)상에 제 1 폴리실리콘을 증착하고, 상기 제 1 폴리실리콘을 선택적으로 식각하여 다수의 게이트라인(13)을 형성한다. 이 때, 상기 게이트라인(13)은 엑세스트랜지스터 및 구동트랜지스터의 게이트전극이며, 상기 엑세스트랜지스터의 게이트라인은 워드라인으로 이용된다. 계속해서, 상기 게이트라인(13)을 마스크로 이용한 불순물 이온주입으로 소스/드레인(도시 생략)을 형성한다.As shown in FIG. 2A, after the field oxide layer 12 is formed on the semiconductor substrate 11 by using an isolation mask, the active region 11a is defined, and then the first polysilicon is deposited on the semiconductor substrate 11. Depositing and selectively etching the first polysilicon to form a plurality of gate lines 13. In this case, the gate line 13 is a gate electrode of an exciter transistor and a driving transistor, and the gate line of the exciter transistor is used as a word line. Subsequently, a source / drain (not shown) is formed by impurity ion implantation using the gate line 13 as a mask.
이어서, 상기 게이트라인(13)을 포함한 전면에 제 1 층간절연막을 형성한 후, 상기 게이트라인(13)과 활성영역(11a)이 동시에 노출되는 정셀노드/부셀노드 콘택홀을 형성한다. 이상 버팅콘택(Butting)이라 한다.Subsequently, a first interlayer insulating layer is formed on the entire surface including the gate line 13, and then a positive cell node / bus cell node contact hole is formed in which the gate line 13 and the active region 11a are simultaneously exposed. This is called butting contact.
이어서, 상기 정셀노드/부셀노드 콘택홀을 포함한 전면에 제 2 폴리실리콘을 증착한 후, 상기 제 2 폴리실리콘을 선택적으로 패터닝하여 엑세스트랜지스터와 구동트랜지스터의 접합부분에 접속되어 상기 엑세스트랜지스터의 드레인에 접속된 비트라인으로부터 전송된 전하를 저장하는 정셀노드콘택/부셀노드콘택(14)을 형성한다.Subsequently, after depositing the second polysilicon on the front surface including the positive cell node and the bushel node contact hole, the second polysilicon is selectively patterned and connected to a junction portion of the excitation transistor and the driving transistor to be connected to the drain of the existor transistor. A positive cell node contact / bus cell node contact 14 that stores charges transferred from the connected bit line is formed.
이어서, 상기 정셀노드콘택/부셀노드콘택(14)을 포함한 전면에 제 2 층간절연막(도시 생략)을 형성한 후, 상기 제 2 층간절연막을 선택적으로 패터닝하여 VSS라인을 형성하기 위한 콘택홀을 형성하고, 상기 콘택홀상에 제 3 폴리실리콘을 형성한다. 계속해서 상기 제 3 폴리실리콘을 선택적으로 패터닝하여 상기 활성영역(11a)에 접속되는 VSS콘택(15a) 및 VSS라인(15b)을 형성한다.Subsequently, after forming a second interlayer insulating film (not shown) on the front surface including the positive cell node contact / bus cell node contact 14, a contact hole for selectively patterning the second interlayer insulating film to form a VSS line is formed. The third polysilicon is formed on the contact hole. Subsequently, the third polysilicon is selectively patterned to form a VSS contact 15a and a VSS line 15b connected to the active region 11a.
계속해서, TFT의 게이트전극에 접속되는 콘택홀을 형성하고, 상기 콘택홀을 포함한 전면에 제 4 폴리실리콘을 형성한 후, 상기 제 4 폴리실리콘을 선택적으로 패터닝하여 TFT의 게이트전극(16)을 형성한 후, 상기 TFT의 게이트전극(16)상에 제3 층간절연막, 즉, TFT의 게이트산화막을 형성한다.Subsequently, a contact hole connected to the gate electrode of the TFT is formed, and fourth polysilicon is formed on the entire surface including the contact hole, and then the fourth polysilicon is selectively patterned to form the gate electrode 16 of the TFT. After formation, a third interlayer insulating film, that is, a gate oxide film of the TFT, is formed on the gate electrode 16 of the TFT.
도 2b에 도시된 바와 같이, 상기 TFT의 게이트산화막상에 TFT의 활성층을 위한 제 5 폴리실리콘을 증착한 후, 상기 제 5 폴리실리콘을 선택적으로 패터닝하여 TFT의 채널 및 소스/드레인(17)을 형성한다. 상기 TFT의 소스/드레인(17) 형성시, VCC라인(18)이 동시에 형성된다.As shown in Fig. 2B, after depositing the fifth polysilicon for the active layer of the TFT on the gate oxide film of the TFT, the fifth polysilicon is selectively patterned to form the channel and source / drain 17 of the TFT. Form. In forming the source / drain 17 of the TFT, a VCC line 18 is formed at the same time.
도 2c에 도시된 바와 같이, 상기 활성영역(11a)을 노출시키는 콘택홀을 형성한 후, 상기 콘택홀에 접속되는 정비트라인(19a) 및 부비트라인(19b)을 형성한다.As shown in FIG. 2C, after forming a contact hole exposing the active region 11a, a positive bit line 19a and a sub bit line 19b connected to the contact hole are formed.
그러나, 상기한 종래기술에서는 6개의 배선층(5P-1M)이며, 마스크 공정의 오정렬로 인해 셀이 비대칭으로 형성되는 문제점이 있다. 그리고, VSS콘택 및 VSS라인으로서 폴리실리콘을 이용하므로 VSS콘택저항이 높고 비트라인 콘택저항이 높음에 따라 저 VCC특성 및 SER(Soft Error Rate) 특성이 저하되는 문제점이 있고, 또한 셀 구성을 위한 공정이 복잡하여 생산성 및 원가절감에 불리한 단점이 있다.However, in the above-described prior art, there are six wiring layers 5P-1M, and the cells are asymmetrically formed due to misalignment of the mask process. In addition, since polysilicon is used as the VSS contact and the VSS line, the low VCC characteristic and the soft error rate (SER) characteristic are deteriorated due to the high VSS contact resistance and the high bit line contact resistance. Complex process for construction has disadvantages in terms of productivity and cost reduction.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 마스크공정의 오정렬에 의한 셀의 비대칭효과(Asymmetry effect)를 방지하고 데이터의 저장부인 셀노드의 콘택저항을 감소시키는데 적합한 SRAM 셀의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, the manufacturing of SRAM cells suitable for preventing the asymmetry effect (cell) caused by the misalignment of the mask process and to reduce the contact resistance of the cell node, which is a data storage unit The purpose is to provide a method.
도 1은 일반적인 SRAM 셀의 등가회로도,1 is an equivalent circuit diagram of a typical SRAM cell,
도 2a 내지 도 2c는 종래기술에 따른 SRAM 셀의 제조 방법을 도시한 레이아웃도,2A to 2C are layout views showing a method of manufacturing an SRAM cell according to the prior art;
도 3a 내지 도 3f는 본 발명의 실시예에 따른 SRAM 셀의 제조 방법을 도시한 레이아웃도,3A to 3F are layout views illustrating a method of manufacturing an SRAM cell according to an embodiment of the present invention;
도 4는 도 3f의 A-A'선에 따른 SRAM 셀의 구조 단면도,4 is a structural cross-sectional view of the SRAM cell taken along the line AA ′ of FIG. 3F;
도 5는 도 3f의 B-B'선에 따른 SRAM 셀의 구조 단면도.FIG. 5 is a structural cross-sectional view of the SRAM cell taken along the line BB ′ of FIG. 3F.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21a : 활성영역 21b : 필드영역21a: active area 21b: field area
22a, 22b, 22c, 22d : 게이트라인 23a : 정셀노드콘택22a, 22b, 22c, 22d: Gate line 23a: Positive cell node contact
23b : 부셀노드콘택 24a : TFT의 채널23b: Busel node contact 24a: TFT channel
24b : TFT의 소스/드레인 24c : VCC라인24b: TFT source / drain 24c: VCC line
25a : VSS콘택 25b : VSS라인25a: VSS contact 25b: VSS line
26a : 정비트라인 26b : 부비트라인26a: positive bit line 26b: sub bit line
100 : 제 1 배선층 200 : 제 2 배선층100: first wiring layer 200: second wiring layer
300 : 제 3 배선층 400 : 제 4 배선층300: third wiring layer 400: fourth wiring layer
500 : 제 5 배선층500: fifth wiring layer
상기의 목적을 달성하기 위한 본 발명의 SRAM 셀의 제조 방법은 엑세스 트랜지스터, 구동 트랜지스터 및 하부게이트구조의 박막트랜지스터를 구비하는 에스램셀의 제조 방법에 있어서, 반도체기판에 대각선 대칭구조를 갖는 활성영역을 형성하는 단계; 상기 활성영역상에 횡방향으로 배선되며 대각선 대칭구조를 갖는 제 1 배선층을 형성하는 단계; 상기 제 1 배선층상에 종방향으로 배선되며 상기 제 1 배선층의 소정부분과 상기 활성영역을 교차결합시키는 제 2 배선층을 형성하는 단계; 상기 제 2 배선층상에 상기 제 2 배선층을 하부게이트로 이용하는 제 3 배선층을 형성하는 단계; 상기 제 3 배선층상에 횡방향으로 배선되며 상기 제 1 배선층 하부의 상기 활성영역에 접속되는 제 4 배선층을 형성하는 단계; 및 상기 제 4 배선층상에 상기 제 4 배선층과 교차하는 방향으로 배선되는 제 5 배선층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing an SRAM cell of the present invention for achieving the above object is a method of manufacturing an SRAM cell having an access transistor, a driving transistor, and a thin film transistor having a bottom gate structure, the active region having a diagonal symmetric structure on a semiconductor substrate Forming; Forming a first wiring layer on the active region in a transverse direction and having a diagonal symmetry structure; Forming a second wiring layer on the first wiring layer in a longitudinal direction and cross-linking a predetermined portion of the first wiring layer and the active region; Forming a third wiring layer on the second wiring layer, the third wiring layer using the second wiring layer as a lower gate; Forming a fourth wiring layer on the third wiring layer in a lateral direction and connected to the active region under the first wiring layer; And forming a fifth wiring layer on the fourth wiring layer in a direction crossing the fourth wiring layer.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
본 발명의 실시예에서 SRAM의 단위셀은 통상과 동일하게 도 1에 도시된 등가회로로 구성되는데, NMOS의 구동트랜지스터(Q1,Q4) 및 엑세스트랜지스터(Q2, Q3), 하부게이트구조의 P형 TFT의 부하트랜지스터로 구성된 6T(6 Transistor) 구조를 갖는다.In the embodiment of the present invention, the unit cell of the SRAM is composed of the equivalent circuit shown in FIG. 1 as in the usual manner, wherein the driving transistors Q1 and Q4 and the access transistors Q2 and Q3 of the NMOS and the P-type of the lower gate structure are illustrated. It has a 6T (6 Transistor) structure composed of TFT's load transistors.
도 3a 내지 도 3f는 본 발명의 실시예에 따른 SRAM 셀의 제조 방법을 도시한레이아웃도로서, 단위셀을 구성하는 구동트랜지스터, 엑세스트랜지스터, 풀업트랜지스터인 TFT의 레이아웃 형태 및 각각의 배선층을 연결시키기 위한 콘택 레이아웃을 도시하고 있다.3A to 3F are layout views illustrating a manufacturing method of an SRAM cell according to an exemplary embodiment of the present invention. The contact layout for this is shown.
도 3a에 도시된 바와 같이, 소자분리마스크를 이용하여 단위셀이 형성될 반도체기판(21)상에서 전기적으로 활성화되어야 할 활성영역(21a)과 비활성화되는 필드영역(21b)을 형성한다. 이 때, SRAM 단위셀의 활성영역(21a)은 대각선 방향의 대칭 구조이고, 중심부에 후속 VSS콘택이 형성될 영역(21c)을 포함하며 단위셀의 상단과 하단에 각각 1/2개씩의 정비트라인패드 및 부비트라인패드가 형성될 영역을 포함한다. 아울러, 후속 셀노드콘택이 형성될 영역도 포함한다.As shown in FIG. 3A, an active region 21a to be electrically activated and a field region 21b to be deactivated are formed on the semiconductor substrate 21 on which the unit cell is to be formed using the device isolation mask. At this time, the active region 21a of the SRAM unit cell has a diagonally symmetrical structure, includes a region 21c in which a subsequent VSS contact is to be formed at the center thereof, and each half is maintained at the top and bottom of the unit cell. And a region where the line pad and the sub bit line pad are to be formed. It also includes the region where subsequent cell node contacts will be formed.
이어서, 상기 활성영역(21a)상에 폴리실리콘(P1), 실리콘, 살리사이드 또는 메탈 중 어느 하나를 형성한 후, 선택적으로 패터닝하여 상기 반도체기판(21)의 활성영역(21a)을 가로지르는 방향 즉, 횡방향으로 엑세스트랜지스터의 게이트라인 (22a, 22b)과 구동트랜지스터의 게이트라인(22c, 22d)을 형성한다. 이 때, 상기 구동트랜지스터의 게이트라인(22c, 22d)은 후속 VSS콘택이 형성될 영역(21c)을 중심으로 상하부에 횡방향으로 대칭구조를 갖고 인접셀(도시 생략)과 서로 고립되어 배치되며, 후속 셀노드콘택을 형성하기 위한 패드 역할을 한다. 이처럼 구동트랜지스터의 게이트라인(22c, 22d)을 후속 셀노드콘택 형성을 위한 패드로 이용하는 이유는 게이트라인과 소스/드레인이 동시에 오픈되는 버팅콘택(Butting contact)을 사용하지 않기 때문이다. 이처럼, 버팅콘택을 이용하지 않으면 종횡비(Aspect ratio)가 작은 콘택을 형성할 수 있다.Subsequently, any one of polysilicon (P1), silicon, salicide or metal is formed on the active region 21a, and then selectively patterned to cross the active region 21a of the semiconductor substrate 21. That is, the gate lines 22a and 22b of the excitation transistor and the gate lines 22c and 22d of the driving transistor are formed in the transverse direction. In this case, the gate lines 22c and 22d of the driving transistor have a symmetrical structure in the transverse direction at the top and bottom with respect to the region 21c where the next VSS contact is to be formed, and are isolated from each other with adjacent cells (not shown). It serves as a pad for forming subsequent cell node contacts. The reason why the gate lines 22c and 22d of the driving transistor is used as a pad for forming subsequent cell node contacts is because a butting contact in which the gate line and the source / drain are open at the same time is not used. As such, when the butting contact is not used, a contact having a small aspect ratio may be formed.
그리고, 상기 엑세스트랜지스터의 게이트라인(22a, 22b)은 상기 구동트랜지스터의 게이트라인(22c, 22d)에 소정간격 이격되어 서로 대칭구조를 갖고 측방으로 인접하는 셀의 엑세스트랜지스터의 게이트라인과 연결되며 워드라인으로 이용된다.The gate lines 22a and 22b of the exciter transistor are spaced apart from the gate lines 22c and 22d of the driving transistor by a predetermined distance, and are connected to the gate lines of the side transistors adjacent to each other. Used as a line.
여기서, 상기 구동트랜지스터의 게이트라인(22c, 22d)과 엑세스트랜지스터의 게이트라인(22a, 22b)은 제 1 폴리실리콘 레벨(Polysilicon level; P1)로서 제 1 배선층(100)이라 하며, 단위셀의 대각선방향으로 서로 대칭된다.Here, the gate lines 22c and 22d of the driving transistor and the gate lines 22a and 22b of the existor transistor are referred to as the first wiring layer 100 as the first polysilicon level P1 and are diagonally formed in the unit cell. Are symmetrical to each other in the direction.
도면에 도시되지 않았지만, 후속 공정으로 상기 제 1 배선층(100)을 마스크로 이용한 불순물 이온주입으로 상기 활성영역(21a)에 각 트랜지스터의 소스/드레인을 형성한다.Although not shown in the figure, a source / drain of each transistor is formed in the active region 21a by impurity ion implantation using the first wiring layer 100 as a mask in a subsequent process.
도 3b에 도시된 바와 같이, 상기 게이트라인(22a, 22b, 22c, 22d)을 포함한 전면에 제 1 층간절연막(도시 생략)을 형성한 후, 상기 제 1 층간절연막을 선택적으로 패터닝하여 후속 정셀노드콘택(NC) 및 부셀노드콘택(/NC)을 위한 콘택홀을 형성하는데, 이 때, 상기 콘택홀 형성으로 인해 구동트랜지스터의 게이트라인(22c, 22d)과 활성영역(21a)의 소정부분이 노출된다. 또한, 상기 활성영역(21a)의 정비트라인패드 및 부비트라인패드가 형성될 부분도 식각하여 콘택홀을 형성한다.As shown in FIG. 3B, after forming a first interlayer insulating film (not shown) on the entire surface including the gate lines 22a, 22b, 22c, and 22d, the first interlayer insulating film is selectively patterned to form a subsequent positive cell node. A contact hole is formed for the contact NC and the subcell node contact / NC, wherein the contact hole is formed to expose a predetermined portion of the gate lines 22c and 22d and the active region 21a of the driving transistor. do. In addition, a portion in which the positive bit line pad and the sub bit line pad are to be formed in the active region 21a is also etched to form a contact hole.
이어서, 상기 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 상기 폴리실리콘을 선택적으로 패터닝하여, 상기 구동트랜지스터의 게이트라인(22c, 22d)과 활성영역(21a)을 교차접속시키는 정셀노드콘택(23a) 및 부셀노드콘택(23b)을 형성하고 동시에 상기 활성영역(21a)에 접속되는 정비트라인패드(23c), 부비트라인패드(23d)를 형성한다.Subsequently, after forming polysilicon on the entire surface including the contact hole, the polysilicon is selectively patterned to cross-connect the gate lines 22c and 22d of the driving transistor and the active region 21a. 23a) and the subcell node contact 23b are formed, and at the same time, the positive bit line pad 23c and the sub bit line pad 23d are connected to the active region 21a.
상기와 같은 정셀노드콘택(23a), 부셀노드콘택(23b), 정비트라인패드(23c) 및 부비트라인패드(23d)를 포함하여 제 2 배선층(200)이라 하며, 상기 제 2 배선층(200)은 후속 부하트랜지스터인 P형 TFT의 게이트로 이용되고 제 2 폴리실리콘 레벨(P2)이다.The second wiring layer 200 is referred to as the second wiring layer 200 including the positive cell node contact 23a, the subcell node contact 23b, the positive bit line pad 23c, and the sub bit line pad 23d. ) Is used as the gate of the P-type TFT which is a subsequent load transistor and is the second polysilicon level P2.
도 3c에 도시된 바와 같이, 상기 제 2 배선층(200)을 포함한 전면에 제 2 층간절연막을 형성한 후, 선택적으로 패터닝하여 하부의 구동트랜지스터의 게이트라인(22c, 22d)에 접속된 정셀노드콘택(23a)과 부셀노드콘택(23b)을 노출시키는 콘택홀을 형성하고, 상기 콘택홀을 포함한 전면에 폴리실리콘을 형성한 후, 선택적으로 패터닝하여 상기 콘택홀을 통해 상기 정셀노드콘택(23a)과 부셀노드콘택(23b)에 접속되는 제 3 배선층(300)을 형성한다. 여기서, 도면부호 24d는 제 2 배선층(200)과 제 3 배선층(300)을 연결시키는 콘택을 나타낸다.As shown in FIG. 3C, a second interlayer insulating film is formed on the entire surface including the second wiring layer 200, and then selectively patterned to form a positive cell node contact connected to gate lines 22c and 22d of a lower driving transistor. A contact hole exposing the contact hole 23a and the subcell node contact 23b is formed, polysilicon is formed on the entire surface including the contact hole, and then selectively patterned to form the contact hole 23a through the contact hole. A third wiring layer 300 connected to the subcell node contact 23b is formed. Here, reference numeral 24d denotes a contact connecting the second wiring layer 200 and the third wiring layer 300.
이 때, 상기 제 3 배선층(300)은 제 3 폴리실리콘 레벨(P3)로서, 상기 제 2 배선층(200)을 하부 게이트로 하는 TFT의 채널(24a) 및 소스/드레인(24b)을 포함하고, 상기 TFT에 전원을 공급하며 횡방향으로 인접셀과 접속되는 VCC라인(24c)을 포함한다.At this time, the third wiring layer 300 is a third polysilicon level P3, and includes a channel 24a and a source / drain 24b of a TFT having the second wiring layer 200 as a lower gate. And a VCC line 24c that supplies power to the TFT and is connected to an adjacent cell in the lateral direction.
상기와 같은 제 3 배선층(300)은 VCC라인(24c)에서 TFT의 채널(24a)을 거쳐 구동트랜지스터의 게이트라인(22c, 22d)에 접속된 정셀노드콘택(23a) 및 부셀노드콘택(23b) 즉, TFT의 게이트전극으로 연결되며, 또한 채널(24a)에서 90°꺽이면서LDO(Lightly Drain Offset) 영역 또는 소스/드레인영역(24b)으로 이어지므로 채널길이(Channel length)를 최대화시킬 수 있다. 즉, 소자의 스링크(Shrink)시 셀크기 감소와 TFT 크기 감소로 인해 발생할 수 있는 TFT의 특성 퇴화를 방지하기 위해 TFT의 채널(24a)과 소스/드레인영역(24b)을 연결하는 형태를 굴곡시키므로서 채널길이를 크게 한다.The third wiring layer 300 as described above is the positive cell node contact 23a and the subcell node contact 23b connected to the gate lines 22c and 22d of the driving transistor through the channel 24a of the TFT in the VCC line 24c. That is, it is connected to the gate electrode of the TFT and also extends 90 ° in the channel 24a to the LDO (Lightly Drain Offset) region or the source / drain region 24b, thereby maximizing the channel length. . In other words, in order to prevent the deterioration of the characteristics of the TFT which may occur due to the decrease in the cell size and the TFT size during the shrinking of the device, the channel 24a and the source / drain region 24b of the TFT are bent. Increase the channel length.
도 3d에 도시된 바와 같이, 상기 제 3 배선층(300)을 포함한 전면에 제 3 층간절연막을 형성한 후, 상기 제 1, 2, 3 층간절연막을 동시에 식각하여 활성영역 (21a)의 VSS콘택이 형성될 부분(21c)을 노출시키는 콘택홀을 형성한다. 이어서, 상기 콘택홀을 포함한 전면에 금속을 증착한 후, 선택적으로 패터닝하여 VSS콘택(25a) 및 VSS라인(25b)을 포함하는 제 4 배선층(400)을 형성한다. 이 때, 상기 제 4 배선층(400)은 제 1 메탈 레벨(Metal level; M1)이라 하며, VSS콘택(25a)에 오버랩되고 단위셀의 횡방향으로 배선되어 측방의 인접셀의 VSS콘택과 연결된다.As shown in FIG. 3D, after forming a third interlayer insulating film on the entire surface including the third wiring layer 300, the first, second and third interlayer insulating films are simultaneously etched to form VSS contacts in the active region 21a. A contact hole for exposing the portion 21c to be formed is formed. Subsequently, a metal is deposited on the entire surface including the contact hole, and then selectively patterned to form a fourth wiring layer 400 including the VSS contact 25a and the VSS line 25b. At this time, the fourth wiring 400, a first metal level (Metal level; M1) referred to, and, VSS contact overlap in (25a) are wired in the horizontal direction of the unit cells VSS contact of the side neighboring cell and Connected.
여기서, 제 4 배선층(400)의 배치공간은 충분하여 여분의 배선라인(25b,25c)을 추가할 수 있는데 이들 라인 중 하나(25b)는 제 1 배선층(100)의 워드라인 즉, 구동트랜지스터의 게이트라인(22c, 22d)을 스트랩핑(Stapping)하는 역할을 하고 나머지 하나(25c)는 글로발 워드라인(Global wordline)으로 사용할 수 있다.Here, the space for arranging the fourth wiring layer 400 is sufficient to add extra wiring lines 25b and 25c. One of these lines 25b is a word line of the first wiring layer 100, that is, a driving transistor. Strapping the gate lines 22c and 22d and the other one 25c may be used as a global wordline.
그리고, 상기 제 4 배선층(400)은 텅스텐 와이어링(W wiring) 공정 또는 텅스텐 플러깅(W pluging) 공정을 사용할 수 있는데 공정수를 감소시키기 위해서는 텅스텐 와이어링 공정을 사용함이 바람직하다.In addition, the fourth wiring layer 400 may use a tungsten wiring process or a tungsten plugging process, but it is preferable to use a tungsten wiring process to reduce the number of processes.
도 3e에 도시된 바와 같이, 상기 제 4 배선층(400)을 포함한 전면에 제 4 층간절연막을 형성한 후, 상기 제 2,3,4 층간절연막을 선택적으로 동시에 식각하여 활성영역(21a)에 접속된 제 2 배선층(200)의 정비트라인패드(23c) 및 부비트라인패드(23d)를 노출시키는 콘택홀을 형성한다.As shown in FIG. 3E, after forming a fourth interlayer insulating film on the entire surface including the fourth wiring layer 400, the second, third and fourth interlayer insulating films are selectively etched and connected to the active region 21a. A contact hole exposing the positive bit line pad 23c and the sub bit line pad 23d of the second wiring layer 200 is formed.
이어서, 상기 콘택홀을 포함한 전면에 금속을 형성한 후, 상기 금속을 선택적으로 패터닝하여 상기 정비트라인패드(23c) 및 부비트라인패드(23d)에 접속되며 소정간격 거리를 갖는 정비트라인(26a) 및 부비트라인(26b)을 포함하는 제 5 배선층(500)을 형성하는데, 이 때, 상기 제 5 배선층(500)은 상기 단위셀의 종방향으로 배선된다. 여기서, 상기 제 5 배선층(500)은 제 2 메탈레벨(M2)이라 한다.Subsequently, after the metal is formed on the front surface including the contact hole, the metal is selectively patterned to connect the positive bit line pad 23c and the sub bit line pad 23d to each other, and to form a positive bit line having a predetermined distance (see FIG. A fifth wiring layer 500 including 26a) and a sub bit line 26b is formed, wherein the fifth wiring layer 500 is wired in the longitudinal direction of the unit cell. In this case, the fifth wiring layer 500 is referred to as a second metal level M2.
도 3f에 도시된 바와 같이, 본 발명의 실시예에서는 5층의 배선구조 즉, 3 폴리실리콘(P3)-2 메탈(M2)의 배선층 구조를 이용하므로써 셀구성 요소를 포함하면서 최소의 배선층을 사용하여 셀 및 전체 다이를 구성하도록 한다. 즉, 5층의 배선구조 중 제 1,2,3 배선층(100, 200, 300)은 폴리실리콘레벨(P1, P2, P3)이고, 제 4, 5 배선층(400, 500)은 금속레벨(M1, M2)이며, VSS콘택(25a) 및 VSS라인(25b)을 포함하는 제 4 배선층(400)을 통상과 달리 금속레벨로 한다.As shown in FIG. 3F, an embodiment of the present invention uses a wiring layer structure of five layers, that is, a wiring layer structure of three polysilicon (P3) -2 metal (M2) to use a minimum wiring layer including cell components. To configure the cell and the entire die. That is, among the five-layer wiring structures, the first, second, third wiring layers 100, 200, and 300 are polysilicon levels P1, P2, and P3, and the fourth and fifth wiring layers 400 and 500 are metal levels M1. , M2), and the fourth wiring layer 400 including the VSS contact 25a and the VSS line 25b is at a metal level unlike usual.
도 4는 도 3f의 A-A'선에 따른 에스램셀의 단면도로서, 반도체기판(21)에 소자분리공정을 이용하여 필드영역(21b)이 형성되고, 필드영역상(21)상에 제 1 배선층(100)의 게이트라인(22d)이 형성되며, 게이트라인(22d)상에 제 2 배선층(200)으로서 셀노드콘택(23a)/부셀노드콘택(23b)이 형성된다. 그리고, 셀노드콘택(23a)/부셀노드콘택(23b)상에 제 3 배선층(300)으로서 TFT의 채널을 포함하는 소스/드레인영역(24d)이 형성되며, 반도체기판(21)의 소스/드레인(도시 생략)에 제 4 배선층(400)으로서 VSS콘택(25a) 및 VSS라인(25b)이 접속된다.FIG. 4 is a cross-sectional view of the SRAM cell taken along the line AA ′ of FIG. 3F, in which a field region 21b is formed on the semiconductor substrate 21 using an element isolation process, and a first region is formed on the field region 21. The gate line 22d of the wiring layer 100 is formed, and the cell node contact 23a / the subcell node contact 23b are formed on the gate line 22d as the second wiring layer 200. Then, a source / drain region 24d including a channel of the TFT as the third wiring layer 300 is formed on the cell node contact 23a / bus cell node contact 23b, and the source / drain of the semiconductor substrate 21 is formed. The VSS contact 25a and the VSS line 25b are connected to the fourth wiring layer 400 (not shown).
마지막으로, VSS라인(25b)상부에 소정간격을 두고 제 5 배선층(500)으로서 정비트라인(26a)/부비트라인(26b)이 형성된다.Finally, the bit line 26a / sub bit line 26b is formed as the fifth wiring layer 500 at predetermined intervals on the VSS line 25b.
여기서, 미설명 도면부호 27a 내지 27d는 층간절연막을 나타낸다.Here, reference numerals 27a to 27d denote the interlayer insulating films.
도 5는 도 3f의 B-B'선에 따른 에스램셀의 구조 단면도로서, 필드영역(21b)이 형성된 반도체기판(21)상에 제 1 배선층(100)으로서 구동트랜지스터 및 엑세스트랜지스터의 게이트라인(22a,22b,22c,22d)이 형성되며, 상기 제 1 배선층(100)상에 제 2 배선층(200)으로서 구동트랜지스터의 게이트라인(22b)과 활성영역(21a)을 교차접속시키는 부셀노드콘택(23b)이 형성된다. 그리고, 활성영역(21a)의 일측에 부비트라인패드(23c)이 접속되며, 부셀노드콘택(23b)상에 제 3 배선층(300)으로서 TFT의 소스/드레인(24a) 및 채널(24b), VCC라인(24c)이 형성된다.FIG. 5 is a structural cross-sectional view of the SRAM cell taken along the line BB ′ of FIG. 3F, and the gate line of the driving transistor and the exciter transistor as the first wiring layer 100 on the semiconductor substrate 21 on which the field region 21b is formed. 22a, 22b, 22c, and 22d are formed on the first wiring layer 100, and as a second wiring layer 200, a subcell node contact for cross-connecting the gate line 22b of the driving transistor and the active region 21a ( 23b) is formed. Then, the sub bit line pad 23c is connected to one side of the active region 21a, and the source / drain 24a and the channel 24b of the TFT as the third wiring layer 300 on the subcell node contact 23b, VCC line 24c is formed.
그리고, 제 3 배선층(300)상에 제 4 배선층(400)으로서 VSS라인(25b), 글로발 워드라인과 워드라인 스트랩핑으로 이용되는 여분의 라인(25c, 25d)이 형성되며 제 4 배선층(400)상에 제 5 배선층(500)으로서 부비트라인(26b)이 부비트라인패드 (23c)에 접속된다.Then, the VSS line 25b, the global word line and the extra lines 25c and 25d used for word line strapping are formed as the fourth wiring layer 400 on the third wiring layer 300, and the fourth wiring layer ( The sub bit line 26b is connected to the sub bit line pad 23c as the fifth wiring layer 500 on the 400.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 에스램셀의 제조 방법은 셀노드콘택 형성시 버팅콘택을 이용하지 않고 구동트랜지스터의 게이트라인을 패드로 이용하여 종횡비(Aspect ratio)가 작은 콘택을 형성하므로써, 셀노드콘택의 저항을 감소시킬 수 있는 효과가 있다.In the method of manufacturing the SRAM cell of the present invention as described above, by forming a contact having a small aspect ratio by using the gate line of the driving transistor as a pad without using a butting contact when forming the cell node contact, There is an effect that can reduce the resistance.
그리고, 금속을 이용하여 VSS콘택 및 VSS라인을 구성하므로써 VSS콘택의 저항을 감소시킬 수 있으며, 하부의 셀노드콘택을 포함하는 제 2 배선층을 TFT의 게이트전극으로 이용하므로써 공정에 소용되는 배선층의 수를 감소시켜 소자의 집적도를 향상시킬 수 있는 효과가 있다.In addition, the resistance of the VSS contact can be reduced by forming the VSS contact and the VSS line using a metal, and the second wiring layer including the lower cell node contact is used as a gate electrode of the TFT. The number of wiring layers can be reduced to improve the degree of integration of the device.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000064437AKR20020034313A (en) | 2000-10-31 | 2000-10-31 | Method of manufacturing sram cell |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000064437AKR20020034313A (en) | 2000-10-31 | 2000-10-31 | Method of manufacturing sram cell |
| Publication Number | Publication Date |
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| KR20020034313Atrue KR20020034313A (en) | 2002-05-09 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000064437AWithdrawnKR20020034313A (en) | 2000-10-31 | 2000-10-31 | Method of manufacturing sram cell |
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| KR (1) | KR20020034313A (en) |
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