KR100547248B1 - 알루미나를 사용한 반도체 소자의 게이트 절연막 형성방법 - Google Patents
알루미나를 사용한 반도체 소자의 게이트 절연막 형성방법Download PDFInfo
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- KR100547248B1 KR100547248B1KR1019990050067AKR19990050067AKR100547248B1KR 100547248 B1KR100547248 B1KR 100547248B1KR 1019990050067 AKR1019990050067 AKR 1019990050067AKR 19990050067 AKR19990050067 AKR 19990050067AKR 100547248 B1KR100547248 B1KR 100547248B1
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- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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Abstract
Description
도 1 및 도 2는 본 발명의 일 실시예에 따른 게이트 절연막 형성 공정도.
* 도면의 주요 부분에 대한 부호의 설명
1 : 실리콘 기판
2 : 소자분리막
3 : 인터페이스 알루미나막
4 : 알루미나막
본 발명은 반도체 제조 기술에 관한 것으로, 반도체 소자 제조 공정 중 게이트 절연막 형성 공정에 관한 것이며, 더 자세히는 알루미나(Al2O3)를 사용한 게이트 절연막 형성 공정에 관한 것이다.
반도체 소자에서 현재 양산중인 DRAM 및 로직(Logic)의 게이트 절연막으로 열산화 방식의 실리콘산화막(SiO2)을 사용하고 있다. 한편, 반도체 소자의 고속화와 디자인 룰(Design rule)의 축소가 계속하여 진행됨에 따라 얇은 두께이 게이트 산화막이 요구되고 있으며, 향후 0.10㎛ 공정에서는 25∼30Å 정도의 두께가 요구되고 있다.
그러나, 이러한 25∼30Å의 두께는 실리콘산화막의 터널링(tunneling) 한계에 해당하며, 이 경우 직접 터널링(direct tunneling)에 의한 오프-전류(off-current)의 증가로 말미암아 소자의 성능이 악화될 우려가 있다.
특히 메모리(memory) 소자의 경우 누설전류(leakage current)의 감소 방안이 중요한 이슈(issue)가 되고 있는데, 이러한 누설전류 문제를 개선하기 위한 노력의 일환으로 높은 유전상수를 가지는 고유전체 물질(high-k dielectric material)을 게이트 절연막으로 채용하고자 하는 연구가 진행되고 있다.
최근에는 실리콘산화막에 비해서 2배 이상의 유전상수를 가지는 알루미나(Al2O3)를 게이트 절연막 재료로 사용하려는 시도가 진행되고 있다. 알루미나는 캐패시터의 유전체로 적용될 경우 탄탈륨산화막(Ta2O5)과 유사하거나 우수한 특성을 가지는 것이 보고 되고 있다.
한편, 이와 같이 캐패시터에 적용되는 알루미나를 그대로 게이트 절연막에 적용할 경우, MOS 트랜지스터 측면에서는 알루미나/실리콘의 우수한 계면 특성이 가장 중요한 인자(factor)로 요구된다.
그런데, 캐패시터에의 적용에서와 같이 유기금속 소오스(metal organic source)를 사용하여 게이트 산화막/실리콘 계면을 형성하게 되면 그 계면에서의 탄소와 수소의 증가가 계면 특성의 열화와 누설전류의 근원이 될 뿐만 아니라, 유효전하(effective charge) 측면에서도 네가티브 전하(negative charge)를 유입하기 때문에 문턱전압(threshold voltage)의 전이(shift)를 야기하는 문제점이 있다.
기 발표된 TMA(TriMethyl Aluminium, Al(CH3)3)와 수증기(H2O)를 이용한 원자층 증착(atomic layer deposition, ALD) 방식의 알루미나의 경우 6×1011#/㎠의 네가티브 인터페이스 전하(negative interfacial charge)에 의하여 플랫밴드 전압(flat band voltage)의 전이가 일어나고 있으며, 현재 진행되고 있는 연구에서도 -5×1012 #/㎠ 수준의 높은 유효 전하가 박막내에 함유되어 문턱전압의 전이를 야기하고 있다. 또한, ALD 방식의 알루미나 박막내에 포함된 탄소 및 수소는 산화막 벌크 트랩(oxide bulk trap)의 근원으로 누설전류 뿐만 아니라, 게이트 산화막 특성(gate oxide integrity, GOI)과 같이 신뢰도와 관련된 심각한 문제를 야기하고 있다.
본 발명은 알루미나를 게이트 절연막으로 사용하고자 하는 경우 반도체 기판과의 계면 특성을 개선하고 문턱전압 전이를 개선할 수 있는 반도체 소자의 게이트 절연막 형성방법을 제공하는데 그 목적이 있다.
상기의 기술적 과제를 달성하기 위하여 본 발명은, 알루미나를 사용한 반도체 소자의 게이트 절연막 형성방법에 있어서, 반도체 기판 상에 상기 알루미나를 증착하는 제1 단계와, 상기 알루미나에 UV 오존 처리를 수행하는 제2 단계를 포함하여 이루어진다.
또한, 본 발명은 알루미나를 사용한 반도체 소자의 게이트 절연막 형성방법에 있어서, 알루미늄 소오스 가스를 0.1∼1.0초 동안 투입(dosing)하고, 1×10-4∼1×10-7Torr의 고진공 상태에서 2∼20초 정도 유지시키고, 산소 소오스 가스를 0.1∼1.0초 동안 투입하고, 1×10-4∼1×10-7Torr의 고진공 상태에서 2∼20초 정도 유지시키는 것을 순환적으로 다수 번 실시하여 반도체 기판 상에 초기 계면층인 제1 알루미나막을 증착하는 제1 단계; 상기 제1 알루미나막에 UV 오존 처리를 수행하는 제2 단계; 및 알루미늄 소오스 가스를 0.1∼1.0초 동안 투입하고, 0.1∼3.0초 동안 배기(purge)를 실시하고, 산소 소오스 가스를 0.1∼1.0초 동안 투입하고, 0.1∼3.0초 동안 배기(purge)를 실시하는 것을 순환적으로 다수 번 실시하여 상기 제1 알루미나막 상에 예정된 두께의 제2 알루미나막을 증착하는 제3 단계를 포함하여 이루어진다.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기 로 한다.
첨부된 도면 도 1 및 도 2는 본 발명의 일 실시예에 따른 게이트 절연막 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.
실리콘 기판(1) 상에 소자분리막(2)을 형성하고, 인터페이스 알루미나막(3)을 증착한다. 이때, 인터페이스 알루미나막(3)은 ALD 방법을 사용하여 증착하는데, 알루미늄(Al)의 소오스 가스로 Al(CH3)3(TMA)를 사용(Al(CH3)2Cl, AlC13 등도 사용 가능)하며, 산소(O)의 소오스 가스로 H2O를 사용한다. 증착온도는 200∼550℃ 정도가 적당하며, 챔버 압력은 0.2∼1.0Torr 정도가 적당하다. 또한, 인터페이스 알루미나막(3)은 5∼10 모노레이어(monolayer, 원자층의 적층 수를 나타내는 단위) 정도 형성하는데, Al 소오스와 H2O를 순환적(cyclic)으로 투입(dosing)하되, 그 사이에 1×10-4∼1×10-7Torr의 고진공(high vacuum) 상태에서 2∼20초 정도의 충분한 유지시간(dwelling time)을 주어 반응하지 못하고 박막내에 잔존할 수 있는 탄화수소계 레지듀(hydrocarbon residue)를 제거한다. 즉, Al 소오스를 0.1∼1초 동안 투입 후 2∼20초간 고진공에서 유지시켜 Al 소오스에 포함된 CH3 또는 CH4가 기판에 흡착되는 것을 어느 정도 방지하고 난 후 H2O를 투입한다. H2O에 대해서도 동일한 투입시간과 유지시간을 적용한다.
계속하여, 상기와 같은 인터페이스 알루미나막(3)의 증착 후에는 UV 오존(ozone) 처리를 통하여 계면에서의 탄소의 존재를 최소화 시켜준다. UV 오존 처리시 웨이퍼 온도는 300∼450℃, 처리 시간은 2∼15분이 바람직하다.
다음으로, 도 2에 도시된 바와 같이 통상적인 TMA/배기(purge)/H2O/배기의 빠른 단계를 반복하여 알루미나막(4)을 증착한다. 이때, 게이트 절연막을 이루는 전체 알루미나의 두께가 10∼150Å 정도가 되도록 한다. 이처럼 기판과의 계면 특성이 우수한 인터페이스 알루미나막(3)을 계속하여 형성하지 않는 이유는 생산성을 극대화하기 위함이다. 이때, TMA와 H2O의 투입시간은 각각 0.1∼1초로 하고 배기시간은 각각 0.1∼3초로 하며, 유전체 특성 개선을 위한 어닐링과 UV 오존 처리를 실시하여 알루미나의 막질을 개선하고 박막내의 탄소 및 수소에 의한 오염(contamination)을 최소화한다. 한편, UV 오존 처리는 알루미나막(4) 증착 중에도 한 번 이상 실시할 수 있으며, 어닐링은 퍼니스 어닐링 방식으로 진행하는 경우, 산소, 질소, N2O 등의 분위기에서 650∼850℃에서 10∼60분 동안 실시하며, 급속열처리 방식으로 진행하는 경우에는 20∼80℃/초의 램프-업 속도를 적용하여 600∼900℃에서 10∼120초간 실시한다.
한편, 알루미나 증착을 위해서 전술한 ALD 방법이 아닌, CVD 방법이나 ECR 원격 플라즈마(electron cyclotron resonance remote plasma) 증착법을 사용할 수 있는데, CVD 방법을 사용하는 경우, 알루미늄(Al)의 소오스 가스로 Al(CH3)3, Al(CH3)2Cl, AlC13 등을 사용하며, 산소(O)의 소오스 가스로 H2/O2, N2O, NO, O2 등을 사용한다. 또한, 증착온도는 300∼750℃, 챔버 압력은 0.1∼0.8Torr 정도의 저압이 적당하다. 그리고, ECR 원격 플라즈마 증착법을 사용하는 경우, 2.45∼8.5GHz의 초 고주파를 이용하여 O2/He를 여기시키고 Al 소오스 가스를 기판 근처에서 분사하여 증착한다.
상기의 일 실시예와 같은 공정을 진행하는 경우, 실제 실험 결과 초기 계면층(인터페이스 알루미나) 증착시 충분한 유지시간(5∼20초)을 준 경우 그렇지 않은 경우에 비하여 유효전하 밀도가 약 30% 정도 줄었고, 여기에 UV 오존 처리를 더 실시하는 경우 기존의 -5×1012 #/㎠ 수준에서 -3×1012 #/㎠ 수준으로 개선되었으며, 이로 인하여 문턱전압 전이는 기존의 1.5∼1.8V에서 1.0∼1.3V로 개선됨을 확인할 수 있었다.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
본 발명은 알루미나 박막 내의 탄소와 같은 불순물을 제거하여 기판과의 계면 특성을 향상시킬 수 있으며, 유효전하 밀도를 줄여 문턱전압 전이를 개선할 수 있는 효과가 있다. 상기의 효과로 인하여 본 발명은 고집적, 고속 소자의 개발을 조기에 달성할 수 있도록 한다.
Claims (16)
- 알루미나를 사용한 반도체 소자의 게이트 절연막 형성방법에 있어서,반도체 기판 상에 상기 알루미나를 증착하는 제1 단계와,상기 알루미나에 UV 오존 처리를 수행하는 제2 단계를 포함하여 이루어진 반도체 소자의 게이트 절연막 형성방법.
- 제1항에 있어서,상기 제1 단계에서,알루미늄 소오스 가스를 투입(dosing)하는 제3 단계;상기 제3 단계 수행 후, 1×10-4∼1×10-7Torr의 고진공 상태에서 2∼20초 정도 유지시키는 제4 단계;산소 소오스 가스를 투입하는 제5 단계; 및상기 제5 단계 수행 후, 1×10-4∼1×10-7Torr의 고진공 상태에서 2∼20초 정도 유지시키는 제6 단계를 다수 번 반복하여 실시하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제1항 또는 제2항에 있어서,상기 UV 오존 처리시 웨이퍼 온도는 300∼450℃, 처리 시간은 2∼15분인 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제2항에 있어서,상기 알루미나는 원자층 증착(ALD)법을 사용하여 증착하되,Al(CH3)3, Al(CH3)2Cl, AlC13 중 어느 하나의 상기 알루미늄 소오스 가스를 사용하고, 상기 산소 소오스 가스로 H2O를 사용하며, 200∼550℃의 증착온도, 0.2∼1.0Torr의 챔버 압력하에서 증착하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제2항에 있어서,상기 제3 단계 및 상기 제5 단계가,각각 0.1∼1.0초 동안 수행되는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 알루미나를 사용한 반도체 소자의 게이트 절연막 형성방법에 있어서,알루미늄 소오스 가스를 0.1∼1.0초 동안 투입(dosing)하고, 1×10-4∼1×10-7Torr의 고진공 상태에서 2∼20초 정도 유지시키고, 산소 소오스 가스를 0.1∼1.0초 동안 투입하고, 1×10-4∼1×10-7Torr의 고진공 상태에서 2∼20초 정도 유지시키는 것을 순환적으로 다수 번 실시하여 반도체 기판 상에 초기 계면층인 제1 알루미나막을 증착하는 제1 단계;상기 제1 알루미나막에 UV 오존 처리를 수행하는 제2 단계; 및알루미늄 소오스 가스를 0.1∼1.0초 동안 투입하고, 0.1∼3.0초 동안 배기(purge)를 실시하고, 산소 소오스 가스를 0.1∼1.0초 동안 투입하고, 0.1∼3.0초 동안 배기(purge)를 실시하는 것을 순환적으로 다수 번 실시하여 상기 제1 알루미나막 상에 예정된 두께의 제2 알루미나막을 증착하는 제3 단계를 포함하여 이루어진 반도체 소자의 게이트 절연막 형성방법.
- 제6항에 있어서,상기 제3 단계 수행 후,상기 제2 알루미나막에 UV 오존 처리를 수행하는 제4 단계와,유전체 막질 개선을 위한 어닐링을 실시하는 제5 단계를 더 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제7항에 있어서,상기 제2 알루미나막 증착 도중에 UV 오존 처리를 적어도 한 번 이상 실시하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제6항에 있어서,상기 제1 및 제2 알루미나막은 원자층 증착(ALD)법을 사용하여 증착하되,Al(CH3)3, Al(CH3)2Cl, AlC13 중 어느 하나의 상기 알루미늄 소오스 가스를 사용하고, 상기 산소 소오스 가스로 H2O를 사용하며, 200∼550℃의 증착온도, 0.2∼1.0Torr의 챔버 압력하에서 증착하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제6항에 있어서,상기 제2 알루미나막은 화학기상증착(CVD)법을 사용하여 증착하되,Al(CH3)3, Al(CH3)2Cl, AlC13 중 어느 하나의 상기 알루미늄 소오스 가스를 사용하고, H2/O2, N2O, NO, O2 중 어느 하나의 상기 산소 소오스 가스를 사용하며, 300∼750℃의 증착온도, 0.1∼0.8Torr의 챔버 압력하에서 증착하는 것을 특징으로 하 는 반도체 소자의 게이트 절연막 형성방법.
- 제6항에 있어서,상기 제2 알루미나막은 ECR 원격 플라즈마(electron cyclotron resonance remote plasma) 증착법을 사용하여 증착하되, 2.45∼8.5GHz의 초고주파를 이용하여 O2/He를 여기시키고 알루미늄 소오스 가스를 기판 근처에서 분사하여 증착하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제6항에 있어서,상기 제1 알루미나막은 5∼10 모노레이어(monolayer) 만큼 증착하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제6항 또는 제12항에 있어서,상기 제1 및 제2 알루미나막의 총 두께가 10∼150Å인 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제6항 내지 제8항 중 어느 한 항에 있어서,상기 UV 오존 처리 각각은 300∼450℃의 웨이퍼 온도, 2∼15분의 처리 시간 조건으로 수행하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제7항에 있어서,상기 어닐링은 산소, 질소, N2O 중 어느 하나를 분위기 가스로 사용하여 650∼850℃에서 10∼60분 동안 퍼니스 어닐링 방식으로 진행하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
- 제7항에 있어서,상기 어닐링은 산소, 질소, N2O 중 어느 하나를 분위기 가스로 사용하며 20∼80℃/초의 램프-업 속도를 적용하여 600∼900℃에서 10∼120초간 급속열처리 방식으로 진행하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.
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