본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 하부전극을 폴리실리콘/전도성 금속질화막의 복층전극으로 형성하므로서 폴리실리콘층의 산화로 인한 충전용량 감소를 최소화하고, 누설전류 및 절연파괴전압을 개선시킬 수 있는 캐패시터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by forming a lower electrode as a multilayer electrode of a polysilicon / conductive metal nitride film, minimizing a reduction in charge capacity due to oxidation of a polysilicon layer, and improving leakage current and dielectric breakdown voltage. It is about a capacitor which can be made.
메모리 반도체 소자의 집적도 증가에 따른 셀의 크기 감소로 캐패시터의 크기 또한 감소하게 되어 충분한 충전용량 확보가 더욱 어려워지고 있다. 따라서 Si3N4/SiO2(NO)보다 유전율이 큰 Ta2O5 고유전율 물질개발이 진행중이나, 폴리실리콘을 하부전극으로 사용하면 Ta2O5 증착 공정이나 후속 열처리 공정에서 폴리실리콘이 산화되어 충전용량이 감소되고, 캐패시터의 전기적 특성이 심각하게 열화된다. 이를 해결하기 위해, 하부전극을 RTN(Rapid Thermal Nitridation) 처리하여 하부전극 표면에 20 내지 30Å 정도의 얇은 질화막(Si3N4, SiOxNy)을 형성한다. 그러나 이 방법 또한 질화막이 너무 얇아서 산화방지막으로서 우수한 특성을 보이지 못하고, 상부전극과의 일함수 차이에 의하여 전기적 특성이 인가되는 바이어스(bias)에 따라 폴라리티(polarity)를 보이는 단점이 있다.As the size of the cell decreases due to the increase in the density of memory semiconductor devices, the size of the capacitor is also reduced, making it difficult to secure sufficient charge capacity. Therefore, development of Ta2 O5 high dielectric constant material, which has a higher dielectric constant than Si3 N4 / SiO2 (NO), is under development, but if polysilicon is used as a lower electrode, polysilicon is oxidized during Ta2 O5 deposition or subsequent heat treatment. This reduces the charge capacity and seriously degrades the electrical characteristics of the capacitor. In order to solve this problem, the lower electrode is subjected to Rapid Thermal Nitridation (RTN) to form a thin nitride film (Si3 N4 , SiOx Ny ) having a thickness of about 20 to about 30 kW on the lower electrode surface. However, this method also has a disadvantage in that the nitride film is too thin to show excellent properties as an anti-oxidation film and to show polarity depending on bias applied to electrical properties due to a difference in work function from the upper electrode.
따라서, 본 발명은 상기 문제점을 해결하기 위해, 캐패시터의 하부전극을 구성하는데 있어서, 폴리실리콘층상에 전도성 금속질화막을 증착한다. 즉, 하부전극을 탄타늄나이트라이드/폴리실리콘, 티타늄나이트라이드/폴리실리콘 및 텅스텐나이트라이드/폴리실리콘 등의 복층전극 구조로 형성한다. 이에 따라, 저유전율 산화막의 형성을 최소화하고, 또한 전도성 금속질화막의 높은 일함수로 인해 낮은 누설전류 및 높은 절연파괴전압을 획득하는데 그 목적이 있다.Accordingly, the present invention, in order to solve the above problems, in forming the lower electrode of the capacitor, depositing a conductive metal nitride film on the polysilicon layer. That is, the lower electrode is formed of a multilayer electrode structure such as titanium nitride / polysilicon, titanium nitride / polysilicon and tungsten nitride / polysilicon. Accordingly, the purpose is to minimize the formation of a low dielectric constant oxide film and to obtain a low leakage current and a high dielectric breakdown voltage due to the high work function of the conductive metal nitride film.
상기한 목적을 달성하기 위한 본 발명은 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판상에 제 1 도프트 폴리실리콘층을 형성한 후 상기 제 1 도프트 폴리실리콘층상에 제 1 전도성 금속질화막을 형성하고, 이로 인하여 상기 기판상에 복층전극 구조의 하부전극이 형성되는 단계; 상기 하부전극상에 Ta2O5 유전체막을 형성한 후 열처리를 실시하는 단계; 및 상기 Ta2O5 유전체막상에 제 2 전도성 금속질화막을 형성한 후 제 2 도프트 폴리실리콘층을 형성하고, 이로 인하여 복층전극 구조의 상부전극이 형성되는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is to form a first conductive polysilicon layer on the first doped polysilicon layer after forming a first doped polysilicon layer on a substrate having a number of elements for forming a semiconductor device And thereby forming a lower electrode of the multilayer electrode structure on the substrate; Forming a Ta2 O5 dielectric film on the lower electrode and then performing heat treatment; And forming a second doped polysilicon layer after forming the second conductive metal nitride layer on the Ta2 O5 dielectric layer, thereby forming an upper electrode of the multilayer electrode structure.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1은 본 발명에 따른 캐패시터의 제조 방법을 설명하기 위한 구성도로서, 기판(10)상에 하부전극(20), 유전체막(19) 및 상부전극(30)이 순차적으로 형성된 나타낸다.FIG. 1 is a block diagram illustrating a method of manufacturing a capacitor according to the present invention, in which a lower electrode 20, a dielectric film 19, and an upper electrode 30 are sequentially formed on a substrate 10.
도 1을 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(10)상에 도프트 폴리실리콘층(13)을 형성한 후 상기 도프트 폴리실리콘층(13)상에 전도성 금속질화막을 형성하고, 이로 인하여 기판(10)상에 복층전극 구조의 하부전극(20)이 형성된다. 상기 하부전극(10)상에 Ta2O5 유전체막(19)을 형성하고, Ta2O5 유전체막(19)의 불순물 제거 및 산소 공공(Oxigen Vacancy)의 감소, 결정화 및 치밀화를 위하여 열처리를 실시한다. Ta2O5 유전체막(19)상에 전도성 금속질화막(22)을 형성한 후 도프트 폴리실리콘층(25)을 형성하고, 이로 인하여 복층전극 구조의 상부전극(30)이 형성된다.Referring to FIG. 1, a doped polysilicon layer 13 is formed on a substrate 10 on which various elements for forming a semiconductor device are formed, and then a conductive metal nitride film is formed on the doped polysilicon layer 13. As a result, the lower electrode 20 of the multilayer electrode structure is formed on the substrate 10. A Ta2 O5 dielectric film 19 is formed on the lower electrode 10, and heat treatment is performed to remove impurities from the Ta2 O5 dielectric film 19 and to reduce, crystallize, and densify oxygen vacancies. Conduct. After the conductive metal nitride layer 22 is formed on the Ta2 O5 dielectric layer 19, the doped polysilicon layer 25 is formed, thereby forming the upper electrode 30 having the multilayer electrode structure.
상기에서, 하부 및 상부전극으로 이용되는 전도성 금속질화막(16 및 22)은 전도성이 우수하고, 내산화성이 큰 TaN, TiN 또는 WN이 사용되며, LPCVD, PECVD, 스퍼터링(sputtering) 및 이온-빔 스퍼터링법(Ion-Beam Sputtering) 등에 의해 증착된다. 상기 전도성 금속질화막(16 및 22)은 종래의 캐패시터에서 발생되는 저유전층인 SiO2 형성을 억제시키고, 또한 누설전류를 감소시켜 전극의 전기적 특성을 향상시킨다.In the above, the conductive metal nitride films 16 and 22 used as the lower and upper electrodes are made of TaN, TiN or WN having excellent conductivity and high oxidation resistance, and include LPCVD, PECVD, sputtering and ion-beam sputtering. Vapor deposition by ion-beam sputtering or the like. The conductive metal nitride films 16 and 22 suppress the formation of SiO2, which is a low dielectric layer generated in a conventional capacitor, and also improve the electrical characteristics of the electrode by reducing the leakage current.
상기 Ta2O5 유전체막(19)은 스텝 커버리지가 좋은 LPCVD 또는 PECVD 등에 의해 비정질(amorphous)상으로 50 내지 150Å의 두께로 증착된다. 이때, 상기 유전체막(19)은 300 내지 600℃의 온도범위, 0.01 내지 1 Torr의 압력범위에서 Ta(OC2H5)5(액체), TaCl5(고체) 또는 TaI5등의 탄타늄 원료물질과 O2, O3, N2O, NO 또는 NO2 등의 산소 원료물질이 사용되어 형성된다.The Ta2 O5 dielectric film 19 is deposited to a thickness of 50 to 150 GPa in an amorphous phase by LPCVD or PECVD with good step coverage. At this time, the dielectric film 19 is a raw material of titanium such as Ta (OC2 H5 )5 (liquid), TaCl5 (solid) or TaI5 in the temperature range of 300 to 600 ℃, pressure range of 0.01 to 1 Torr The material is formed by using oxygen raw materials such as O2 , O3 , N2 O, NO or NO2 .
상기 열처리는 단일 열처리 또는 두 단계 열처리로 실시되는데, 두 단계 열처리는 저압 및 저온의 제 1 열처리와 고온의 제 2 열처리로 실시된다. 상기 제 1 열처리는 O2, O3, N2O, NO 또는 NO2 등의 가스 분위기에서 300 내지 600 ℃의 온도범위, 0.1 내지 1 Torr의 압력범위로 실시되고, 제 2 열처리는 O2, O3, N2O, NO 또는 NO2 등의 가스 분위기, 저압 또는 상압에서 700 내지 900℃ 온도범위로 실시된다. 또한, 상기 열처리는 플라즈마 및 자외선 등의 보조에너지원을 이용하여 O2, O3, N2O, NO 또는 NO2 등의 가스를 활성화시킨다.The heat treatment is carried out in a single heat treatment or a two-stage heat treatment, wherein the two-stage heat treatment is performed by the first heat treatment at low pressure and low temperature and the second heat treatment at high temperature. The first heat treatment is carried out in a temperature range of 300 to 600 ℃, a pressure range of 0.1 to 1 Torr in a gas atmosphere such as O2 , O3 , N2 O, NO or NO2 , the second heat treatment is O2 , It is carried out at a temperature range of 700 to 900 ° C. in a gas atmosphere, low pressure or normal pressure, such as O3 , N2 O, NO, or NO2 . In addition, the heat treatment activates gases such as O2 , O3 , N2 O, NO, or NO2 using auxiliary energy sources such as plasma and ultraviolet light.
본 발명에서 사용된 TaN, TiN, WN 등의 전도성 금속질화막(16 및 22)은 폴리실리콘에 비해 산화저항성이 월등히 크므로 쉽게 산화가 되지 않고, 산화가 발생해도 Ta2O5및 TiO2 등의 고유전체막이 생성되므로 충전용량의 감소가 작다. 또한 TaN, TiN, WN 등의 전도성 금속질화막(16 및 22)은 산소 원자와 실리콘 원자의 확산 장벽으로 작용하므로 열처리시 SiO2의 생성을 억제하는 특성이 있다. 그리고 일함수가 폴리실리콘에 비해 크므로 누설전류 및 전연파괴전압 특성이 개선되는 특징이 있다.The conductive metal nitride films 16 and 22 used in the present invention, such as TaN, TiN, and WN, have much greater oxidation resistance than polysilicon, and thus are not easily oxidized, and even when oxidation occurs, such as Ta2 O5 and TiO2 . Since the high-k dielectric film is produced, the reduction of the charge capacity is small. In addition, since the conductive metal nitride films 16 and 22 such as TaN, TiN, and WN act as diffusion barriers of oxygen atoms and silicon atoms, there is a property of suppressing generation of SiO2 during heat treatment. In addition, since the work function is larger than that of polysilicon, the leakage current and the breakdown voltage characteristics are improved.
한편, Ta2O5 유전체막(19) 대신에 사용할 수 있는 BST [(Ba,Sr)TiO3], STO [SrTiO3], BTO [BaTiO3], PZT [Pb(Zr,Ti)O3], PLZT [(Pb,La)(Zr,Ti)O3] 등의 고유전 물질에도 상기 본 발명의 적응이 가능한다.On the other hand, BST [(Ba, Sr) TiO3], STO [SrTiO3], BTO [BaTiO3], PZT [Pb (Zr, Ti) O3], PLZT [(which can be used in place of Ta2 O5 dielectric film 19) Pb, La) (Zr, Ti) O 3] and the like can be adapted to the present invention.
캐패시터의 Ta2O5 유전체막 증착공정은 고온의 산화분위기에서 이루어지므로 하부전극으로 사용된 폴리실리콘층상에 저유전층인 SiO2가 생성되고, Ta2O5 증착후의열처리 공정에서 Ta2O5유전체막과 하부전극인 폴리실리콘층의 계면에 SiO2의 저유전층이 생성된다. 그러나 TaN, TiN, WN 등은 폴리실리콘에 비해 산화저항성이 월등히 크므로 쉽게 산화가 되지 않고, 산화가 발생해도 Ta2O5또는 TiO2등의 고유전율층이 생성되므로 충전용량의 감소가 작다. 또한, TaN, TiN, WN 등은 산소 원자와 실리콘 원자의 확산 장벽으로 작용하므로, 열처리시 SiO2의 생성을 억제한다. 그리고, TaN, TiN , WN 등은 일함수가 폴리실리콘에 비해 크므로 누설전류 및 절연파괴전압 특성이 개선되고, 상하부 전극을 같은 물질로 사용하면 전극의 일함수 차이에 의한 전기적 특성의 폴라리티가 발생되지 않는다.Since the Ta2 O5 dielectric film deposition process of the capacitor is performed in a high temperature oxidizing atmosphere, a low dielectric layer SiO2 is formed on the polysilicon layer used as the lower electrode, and the Ta2 O5 dielectric material is used in the heat treatment process after Ta2 O5 deposition. A low dielectric layer of SiO2 is formed at the interface between the film and the polysilicon layer as the lower electrode. However, since TaN, TiN, WN, etc. are much higher in oxidation resistance than polysilicon, they are not easily oxidized, and even when oxidation occurs, a high dielectric constant layer such as Ta2 O5 or TiO2 is generated, so that the reduction in charge capacity is small. Further, TaN, TiN, WN and the like act as diffusion barriers of oxygen atoms and silicon atoms, thus suppressing the generation of SiO2 during heat treatment. In addition, since TaN, TiN, and WN have a larger work function than polysilicon, leakage current and breakdown voltage characteristics are improved, and when the upper and lower electrodes are used as the same material, the polarity of the electrical characteristics due to the difference in the work function of the electrodes is increased. It does not occur.
따라서, 본 발명에 따르면, 하부전극으로 폴리실리콘상에 전도성 금속질화막을 증착하므로서 산화문제를 해결할 수 있고, 전도성 금속질화막의 높은 일함수로 인해 낮은 누설전류와 높은 절연파괴전압을 얻을 수 있다. 또한, 유효 산화막 두께 40Å 이하의 유전율을 얻을 수 있어 차세대 소자의 개발을 앞당길 수 있으며, 하부 전극을 종래에 사용하던 폴리실리콘을 사용하므로 공정개발 및 장비투자 등의 비용을 절감할 수 있다.Therefore, according to the present invention, the oxidation problem can be solved by depositing a conductive metal nitride film on polysilicon as a lower electrode, and a low leakage current and a high dielectric breakdown voltage can be obtained due to the high work function of the conductive metal nitride film. In addition, the dielectric constant of 40 유효 or less effective oxide film thickness can be obtained to accelerate the development of next-generation devices, and polysilicon used as the lower electrode is conventionally used, thereby reducing costs such as process development and equipment investment.
도 1은 본 발명에 따른 캐패시터의 제조 방법을 설명하기 위한 구성도.1 is a configuration diagram for explaining a method for manufacturing a capacitor according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
10 : 반도체 기판 13 및 25 : 도프트 폴리실리콘층10 semiconductor substrate 13 and 25 doped polysilicon layer
16 및 22 : 전도성 금속질화막 19 : 유전체막16 and 22: conductive metal nitride film 19: dielectric film
20 : 하부전극 30 : 상부전극20: lower electrode 30: upper electrode
| Application Number | Priority Date | Filing Date | Title |
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| KR1019980025645AKR100538074B1 (en) | 1998-06-30 | 1998-06-30 | Capacitor Manufacturing Method of Semiconductor Device |
| Application Number | Priority Date | Filing Date | Title |
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| KR1019980025645AKR100538074B1 (en) | 1998-06-30 | 1998-06-30 | Capacitor Manufacturing Method of Semiconductor Device |
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| KR20000004215A KR20000004215A (en) | 2000-01-25 |
| KR100538074B1true KR100538074B1 (en) | 2006-04-28 |
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| KR1019980025645AExpired - Fee RelatedKR100538074B1 (en) | 1998-06-30 | 1998-06-30 | Capacitor Manufacturing Method of Semiconductor Device |
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| KR20040008527A (en)* | 2002-07-18 | 2004-01-31 | 주식회사 하이닉스반도체 | Method of semiconductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR970018493A (en)* | 1995-09-01 | 1997-04-30 | 김광호 | Capacitor Fabrication Method for Semiconductor Devices |
| JPH1022455A (en)* | 1996-06-28 | 1998-01-23 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| KR980012537A (en)* | 1996-07-30 | 1998-04-30 | 김광호 | Capacitor of semiconductor device and manufacturing method thereof |
| KR19980021205U (en)* | 1996-10-19 | 1998-07-15 | 박병재 | Door sealing structure of automobile |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970018493A (en)* | 1995-09-01 | 1997-04-30 | 김광호 | Capacitor Fabrication Method for Semiconductor Devices |
| JPH1022455A (en)* | 1996-06-28 | 1998-01-23 | Oki Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| KR980012537A (en)* | 1996-07-30 | 1998-04-30 | 김광호 | Capacitor of semiconductor device and manufacturing method thereof |
| KR19980021205U (en)* | 1996-10-19 | 1998-07-15 | 박병재 | Door sealing structure of automobile |
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| KR20000004215A (en) | 2000-01-25 |
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