본 발명은 반도체 장치의 저유전상수 절연막 형성방법에 관한 것으로서, 상세하게는 페닐트리에톡시실란(PhenylTriEthoxySilane, 이하 "PTES"라 약하기로 한다)을 증착 소오스로 이용하여 유기그룹(organic group)을 포함하는 실리콘 산화막을 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a low dielectric constant insulating film of a semiconductor device, and more particularly, includes an organic group using phenyltriethoxysilane (hereinafter referred to as "PTES") as a deposition source. A method for forming a silicon oxide film.
반도체 장치의 고밀도 고집적화는 보다 미세한 회로 구조가 요구되며, 따라서 동일 평면상에 형성되는 금속 배선간의 수평 간격이 감소되어야 한다. 그런데, 금속 배선간의 간격이 좁아지게 되면 금속 배선 상호 간의 교란(cross talk)이 일어날 수 있으며, 절연막에 의하여 전기적으로 분리된 인접한 금속 배선 사이의 기생 커패시턴스가 증가된다. 따라서, 금속 배선을 통한 반도체 장치의 전기적 신호가 불완전하게 전달되거나. 그 전달 속도가 감소하는 문제가 발생된다.High density and high integration of semiconductor devices require finer circuit structures, and therefore horizontal spacing between metal lines formed on the same plane must be reduced. However, when the spacing between the metal wires is narrowed, cross talk between the metal wires may occur, and parasitic capacitance between adjacent metal wires electrically separated by the insulating film is increased. Therefore, the electrical signal of the semiconductor device through the metal wiring is incompletely transmitted. The problem arises in that the transmission speed is reduced.
금속 배선을 통하여 전달되는 신호 전달 속도는 반비례의 관계에 있는 지연 상수(RC, delay constant)에 의존한다. 지연 상수(RC)는 하기 수학식 1로 표현된다.The rate of signal transmission through the metal wire depends on the delay constant (RC), which is inversely related. The delay constant RC is represented by the following equation.
이때, 상기 수학식 1에서 ρIn this case, p in Equation 1
m는 금속 배선의 비저항, εox는 층간 절연막의 유전 상수, Lm2은 금속 배선의 길이, Tm은 금속 배선의 두께 및 Tox는 층간 절연막의 두께를 각각 나타낸다.m is the resistivity of the metal wiring, εox is the dielectric constant of the interlayer insulating film, Lm2 is the length of the metal wiring, Tm is the thickness of the metal wiring, and Tox is the thickness of the interlayer insulating film, respectively.
한편, 상기 수학식 1에서 알 수 있듯이, 지연상수(RC)를 결정하는 요소, 구체적으로 금속 배선의 비저항(ρm), 층간 절연막의 유전 상수(εox), 금속 배선의 길이(Lm2), 금속 배선의 두께(Tm) 및 층간 절연막의 두께(Tox) 들 각각은 금속 배선을 통한 전기적 신호 전달에 있어서 지연 상수(RC)를 결정하는 중요한 인자이다. 특히 본 발명과 관련하여 금속 배선 사이의 전기적 소자분리를 위한 층간 절연막의 유전 상수(εox)에 관심을 집중하기로 한다.On the other hand, as can be seen in Equation 1, the element that determines the delay constant (RC), specifically the specific resistance (ρm ) of the metal wiring, the dielectric constant (εox ) of the interlayer insulating film, the length of the metal wiring (Lm2 ), The thickness of the metal wiring (Tm ) and the thickness of the interlayer insulating film (Tox ) are each important factors for determining the delay constant (RC) in the electrical signal transmission through the metal wiring. In particular, attention will be paid to the dielectric constant εox of the interlayer insulating film for the isolation of electrical devices between metal wires.
상기 수학식 1로부터 층간 절연막의 유전 상수(εox)가 작으면 작을수록 지연 상수(RC)는 더욱 작은 값을 갖게 됨을 알 수 있으며, 따라서 층간 절연막의 유전 상수(εox)가 작을수록 금속 배선을 통한 신호 전달 속도가 증가됨을 알 수 있다. 결론적으로, 금속 배선을 통한 신호 전달 속도를 증가시키기 위해서는 유전상수(또는 유전율)가 작은 절연막을 이용하는 것이 필연적임을 알 수 있다.It can be seen from Equation 1 that the smaller the dielectric constant εox of the interlayer insulating film is, the smaller the delay constant RC is. Therefore, the smaller the dielectric constant εox of the interlayer insulating film is, the metal wiring isreduced . It can be seen that the signal transmission rate is increased through. In conclusion, it is necessary to use an insulating film having a small dielectric constant (or dielectric constant) in order to increase the signal transmission rate through the metal wiring.
종래의 화학기상증착(CVD) 방법으로 형성되는 저유전상수 절연막으로 산화실리콘플로라이드(FxSiOy)계 절연막과, 비결정질의(amorphous) 탄화수소물질(α-C:H) 또는 동계의 탄화불소물질(α-C:F)로 이루어진 절연막을 들 수 있다.A low dielectric constant insulating film formed by a conventional chemical vapor deposition (CVD) method is a silicon oxide fluoride (Fx SiOy ) -based insulating film, amorphous hydrocarbon material (α-C: H) or copper fluorocarbon material and an insulating film made of (? -C: F).
산화실리콘플로라이드(FxSiOy)계 절연막은 기존의 실리콘 산화막과 유사한 공정으로 형성한다. 따라서, 산화실리콘플로라이드(FxSiOy)계 절연막을 증착하는 공정은 그 공정을 진행하는 공정 조건은 쉽게 찾을 수 있는 장점이 있다. 반면, 산화실리콘플로라이드(FxSiOy)계 절연막 내의 불소(F)의 농도가 증가함에 따라 증착된 절연막의 안정성이 감소하는 단점이 있다.Silicon oxide-based (Fx SiOy ) -based insulating film is formed by a process similar to the conventional silicon oxide film. Therefore, the process of depositing a silicon oxide (Fx SiOy ) -based insulating film has an advantage that the process conditions for proceeding the process can be easily found. On the other hand, as the concentration of fluorine (F) in the silicon oxide fluoride (Fx SiOy ) -based insulating film increases, the stability of the deposited insulating film is reduced.
한편, 비결정질의 탄화수소물질(α-C:H) 또는 비결정질의 탄화불소물질(α-C:F)로 이루어진 절연막은 매우 낮은 유전상수, 예컨대 2.2 내지 2.8의 값을 갖는 장점이 있다. 그러나, 비결정질의 탄화수소물질(α-C:H) 또는 비결정질의 탄화불소물질(α-C:F)로 이루어진 절연막은 저유전상수를 확보할 수 있음에도 불구하고, 절연막의 열적 안정성(thermal stability)이 낮으며, 산소 플라즈마에 대한 내성이 떨어지며, 상이한 다른 물질층에 응착(adhesion)이 어려운 여러 단점이 있다. 이러한 단점 때문에 DLC(Diamond-Like Carbon)막 등을 추가로 형성하는 공정이 필요하며, 이는 반도체 제조 공정의 단순화와는 배치되는 문제점이 있다.On the other hand, an insulating film made of amorphous hydrocarbon material (α-C: H) or amorphous fluorocarbon material (α-C: F) has an advantage of having a very low dielectric constant, for example, a value of 2.2 to 2.8. However, an insulating film made of an amorphous hydrocarbon material (α-C: H) or an amorphous fluorocarbon material (α-C: F) has a low thermal stability even though a low dielectric constant can be secured. In addition, there are a number of disadvantages in that the resistance to oxygen plasma is poor and it is difficult to adhere to different material layers. Because of these drawbacks, a process of additionally forming a diamond-like carbon (DLC) film is required, which has a problem of being disposed with the simplification of the semiconductor manufacturing process.
따라서, 본 발명이 이루고자 하는 기술적 과제는 상술한 문제점을 해소하기 위한 것으로서, 산소에 대한 내성이 있는 저유전상수의 절연막을 층간절연막으로 이용하여 금속막간의 기생 커패시터의 정전용량을 줄일 수 있는 반도체 장치의 금속막 형성방법을 제공함에 있다.Accordingly, a technical problem to be solved by the present invention is to solve the above-described problems. The semiconductor device can reduce the capacitance of parasitic capacitors between metal films by using an insulating film having a low dielectric constant that is resistant to oxygen as an interlayer insulating film. A metal film forming method is provided.
도 1 내지 도 5는 본 발명의 실시예에 의한 저유전상수 절연막을 층간절연막으로 사용하는 반도체 장치의 금속막 형성방법을 단계별로 나타낸 도면들이다.1 to 5 are diagrams showing step by step methods of forming a metal film of a semiconductor device using a low dielectric constant insulating film as an interlayer insulating film according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호설명><Code Description of Main Parts of Drawing>
40:반도체 기판. 42, 56:제1 및 제2 금속층 패턴.40: semiconductor substrate. 42, 56: First and second metal layer patterns.
44, 46:제1 및 제2 절연막.44, 46: First and second insulating films.
48:자외선 조사.48: UV irradiation.
상기 기술적 과제를 달성하기 위해, 본 발명은 반도체 기판 상에 제1 금속막 패턴을 형성하는 단계와 상기 반도체 기판 상에 상기 제1 금속막 패턴의 전면을 덮는 층간 절연막을 형성하는 단계와 상기 층간 절연막에 상기 제1 금속막 패턴을 노출시키는 비어홀을 형성하는 단계 및 상기 층간절연막 상에 상기 비어홀을 채우는 제2 금속막 패턴을 형성하는 단계를 포함하는 금속막 형성 방법에 있어서, 상기 비어홀 형성 이후의 공정에서 상기 층간 절연막의 유전율이 증가되는 것을 방지하기 위해 상기 비어홀 형성에 앞서 상기 층간 절연막 전면에 자외선을 조사(UV-curing)하여 상기 층간 절연막의 산소 플라즈마에 대한 내성을 높이는 것을 특징으로 하는 반도체 장치의 금속막 형성 방법을 제공한다.In order to achieve the above technical problem, the present invention is a step of forming a first metal film pattern on a semiconductor substrate and forming an interlayer insulating film covering the entire surface of the first metal film pattern on the semiconductor substrate and the interlayer insulating film Forming a via hole exposing the first metal film pattern in the second layer; and forming a second metal film pattern filling the via hole on the interlayer insulating layer, wherein the process is performed after the via hole is formed. In order to prevent the dielectric constant of the interlayer insulating layer from increasing, UV-curing is applied to the entire surface of the interlayer insulating layer prior to forming the via hole, thereby increasing the resistance of the interlayer insulating layer to oxygen plasma. A metal film forming method is provided.
이 과정에서, 상기 층간절연막을 형성하기 위해, 상기 제1 금속막 패턴이 형성된 반도체 기판 상에 스핀 온 글래스(Spin On Glass:이하, SOG라 한다)막과 저유전 상수의 실리콘 산화막, 예컨대 SiOC막을 순차적으로 형성한다. 이때, 상기 SiOC막은 페닐트리에톡시실렌(Phenyltriethoxysilane, 이하 PTES라 한다)을 이용하여형성한다.In this process, in order to form the interlayer insulating film, a spin on glass (hereinafter referred to as SOG) film and a silicon oxide film having a low dielectric constant, such as a SiOC film, are formed on a semiconductor substrate on which the first metal film pattern is formed. Form sequentially. In this case, the SiOC film is formed using phenyltriethoxysilane (hereinafter referred to as PTES).
상기 SOG막을 형성하기 전에 캡핑 산화막(capping oxide)을 먼저 형성할 수 있다.Before forming the SOG film, a capping oxide may be formed first.
상기 층간절연막의 산소 플라즈마에 대한 내성을 높이기 위해 본 발명은 자외선을 상기 층간절연막의 전면에 조사하는 방법을 제시한다. 일명, 자외선 치료 방법(UV curing)을 제시한다.The present invention provides a method for irradiating the entire surface of the interlayer insulating film to increase the resistance to the oxygen plasma of the interlayer insulating film. Also known as, UV curing (UV curing).
이렇게 함으로써 상기 비어홀을 형성한 다음 감광막 패턴을 제거하기 위해 실시되는 산소 플라즈마를 이용한 에싱과정에서 상기 층간절연막, 특히 상기 저 유전 상수의 절연막의 유전율이 증가되는 것을 방지하여 인접한 상기 금속막 간의 기생 커패시터의 정전용량이 증가되는 것을 방지할 수 있다. 이 결과, 상기 금속막을 통한 신호전달이 원활하게 이루어지고 기생 커패시터에 의해 전달속도가 저하되는 것을 방지할 수 있다.By doing so, the dielectric constant of the interlayer insulating film, in particular the low dielectric constant insulating film, is prevented from increasing during the ashing process using the oxygen plasma formed to form the via hole and then remove the photoresist pattern. The capacitance can be prevented from increasing. As a result, it is possible to smoothly transmit the signal through the metal film and to prevent the transfer speed from being lowered by the parasitic capacitor.
이하, 본 발명의 실시예에 의한 저유전상수 절연막을 층간절연막으로 사용하는 반도체 장치의 금속막 형성방법을 첨부된 도면들을 참조하여 상세하게 설명한다.Hereinafter, a method of forming a metal film of a semiconductor device using a low dielectric constant insulating film according to an embodiment of the present invention as an interlayer insulating film will be described in detail with reference to the accompanying drawings.
그러나 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들에 한정되는 것으로 해석되어져서는 안된다. 본 발명의 실시예는 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되어지는 것이다. 도면에서 층이나 영역들의 두께는 명세서의 명확성을 위해 과장되어진 것이다. 도면상에서 동일한 부호는 동일한 요소를 지칭한다. 또한, 어떤 층이 다른 층 또는 기판의 "상부"에 있다라고 기재된 경우, 상기 어떤 층이 상기 다른 층 또는 기판의 상부에 직접 존재할 수도 있고 그 사이에 제 3의 층이 개재되어 질 수도 있다.However, embodiments of the present invention can be modified in many different forms, the scope of the invention should not be construed as limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements. In addition, where a layer is described as being "top" of another layer or substrate, the layer may be directly on top of the other layer or substrate, with a third layer intervening therebetween.
도 1 및 도 2는 층간 절연막을 형성하는 방법을 단계별로 나타낸 도면들이다.1 and 2 are steps illustrating a method of forming an interlayer insulating film.
구체적으로, 도 1을 참조하면, 반도체 기판(40) 상에 제1 금속막 패턴(42)을 형성한다. 상기 반도체 기판(40) 상에 상기 제1 금속막 패턴(42)을 덮는 제1 절연막(44)을 형성한다. 상기 제1 절연막(44)은 SOG막으로 형성한다. 상기 제1 절연막(44)을 형성하기 전에 캡핑 산화막(capping oxide)을 형성할 수도 있다.Specifically, referring to FIG. 1, the first metal film pattern 42 is formed on the semiconductor substrate 40. A first insulating film 44 covering the first metal film pattern 42 is formed on the semiconductor substrate 40. The first insulating film 44 is formed of an SOG film. Before forming the first insulating layer 44, a capping oxide may be formed.
도 2를 참조하면, 상기 제1 절연막(44) 상에 제2 절연막(46)을 형성한다. 상기 제2 절연막(46)은 저유전 상수를 갖는 실리콘 산화막, 예컨대 SiOC막으로 형성한다.Referring to FIG. 2, a second insulating layer 46 is formed on the first insulating layer 44. The second insulating film 46 is formed of a silicon oxide film having a low dielectric constant, for example, an SiOC film.
이때, 상기 SiOC막은 실리콘과 산소간 결합(Si-O bond)과 실리콘과 탄소간 결합(Si-C bond)을 가지고 있는 케미컬(Chemical)을 전구체(precursor)로 사용하여 얻을 수 있다. 본 발명은 이러한 전구체중의 하나로 테트라에톡시오소실리케이트(tetraethoxyorthosilicate:TEOS)분자에서 에톡시(ethoxy)기 하나를 벤젠 링(benzene ring)으로 치환시킨 PTES를 사용한다.In this case, the SiOC film may be obtained by using a chemical having a silicon-to-oxygen bond (Si-O bond) and a silicon-to-carbon bond (Si-C bond) as a precursor. The present invention uses PTES in which one ethoxy group is substituted with a benzene ring in tetraethoxyorthosilicate (TEOS) molecule as one of such precursors.
상기 PTES를 이용한 SiOC막 형성 방법은 본 출원인에 의해 "반도체 장치의 저유전상수 절연막 형성방법"이라는 제목으로 특허 출원(97-65542)중에 있으므로 자세한 설명은 생략한다.Since the method for forming a SiOC film using the PTES is in the patent application (97-65542) entitled "Method of forming a low dielectric constant insulating film of a semiconductor device" by the applicant, detailed description thereof will be omitted.
계속해서 상기 제2 절연막(46)의 산소 플라즈마에 대한 내성을 높인다. 이를 위한 한 방법으로 도 3에 도시한 바와 같이, 상기 제2 절연막(46)의 전면에 대해 자외선을 조사(48)한다. 즉, 상기 제2 절연막(46)에 대해 자외선 치료(UV curing)를 실시한다. 상기 자외선 조사(48)를 위해 자외선 원으로 수은(Hg) 램프를 사용한다. 상기 자외선 조사(48)의 평균 파워는 약 375 mW/㎠이나 필요에 따라 파워 값의 상, 하 조절이 가능하다. 이와 같은 평균 파워에서 상기 자외선 조사(48)는 약 9분정도 실시한다. 상기 자외선 조사(48)의 평균 파워가 조절되는 경우, 상기 조사 시간도 그에 따라 조절될 수 있다.Subsequently, the resistance to the oxygen plasma of the second insulating film 46 is increased. As a method for this purpose, as shown in FIG. 3, ultraviolet rays 48 are irradiated onto the entire surface of the second insulating layer 46. That is, UV curing is performed on the second insulating layer 46. A mercury (Hg) lamp is used as the ultraviolet source for the ultraviolet irradiation 48. The average power of the ultraviolet irradiation 48 is about 375 mW / ㎠, but if necessary, the power value can be adjusted up and down. At this average power, the ultraviolet irradiation 48 is carried out for about 9 minutes. When the average power of the ultraviolet irradiation 48 is adjusted, the irradiation time can also be adjusted accordingly.
여기서, 상기 제2 절연막(46)에 대해 상기 자외선 조사(48)를 실시했을 때와 실시하지 않았을 때, 상기 제2 절연막(46)이 어떻게 변하였는가를 실험예를 바탕으로 설명한다.Here, how the second insulating film 46 changes when the ultraviolet ray irradiation 48 is applied to the second insulating film 46 and when not is described will be described based on the experimental example.
상기 자외선 조사(48)는 상기 제2 절연막(46)의 후속공정에서 산소 플라즈마에 대한 내성을 높이기 위한 것이다. 따라서, 상기 자외선 조사(48)가 되지 않은 상기 제2 절연막(46)의 산소 플라즈마에 의한 특성 변화를 알아보는 것이 바람직할 것이다.The ultraviolet irradiation 48 is to increase the resistance to oxygen plasma in the subsequent step of the second insulating film 46. Therefore, it may be desirable to find out the characteristic change by the oxygen plasma of the second insulating film 46 that is not the ultraviolet irradiation 48.
상기 제2 절연막(46)의 상기 산소 플라즈마에 의한 특성 변화를 알아보기 위해 본 출원인은 상기 제2 절연막(46)으로서 PTES를 이용한 SiOC막을 사용하였다. 이때, 상기 SiOC막은 150℃정도에서 형성하였다. 그리고 반응챔버의 압력은 2토르(Torr)정도로 유지하였으며, 산소 플라즈마 형성을 위한 고주파 전력(RF power)은 300왓트(W)정도를 인가하였고, 상기 산소 플라즈마 형성을 위해 상기 반응챔버에 300 sccm(standard cubic cm)정도의 플로우 율로 산소가스를 공급하였다. 이와 같은 조건하에서 상기 SiOC막을 30분 동안 상기 산소 플라즈마에 노출시켰다. 이후, 상기 SiOC막의 특성들, 예컨대 두께와 굴절율(Refractive Index, 이하,RI라 한다) 및 유전율을 측정하였다. 측정된 결과는 아래의 표 1과 같다.Applicant used the SiOC film using PTES as the second insulating film 46 in order to determine the characteristic change of the second insulating film 46 by the oxygen plasma. At this time, the SiOC film was formed at about 150 ℃. In addition, the pressure of the reaction chamber was maintained at about 2 Torr, and the RF power for forming the oxygen plasma was about 300 Watts (W), and 300 sccm ( Oxygen gas was supplied at a flow rate of about standard cubic cm). Under these conditions, the SiOC film was exposed to the oxygen plasma for 30 minutes. Thereafter, properties of the SiOC film, such as thickness, refractive index (hereinafter referred to as RI), and dielectric constant, were measured. The measured results are shown in Table 1 below.
표 1 산소 플라즈마 처리 전, 후의 SiOC막의 특성변화Table 1 Characteristics of SiOC film before and after oxygen plasma treatment
상기 표 1을 참조하면, 산소 플라즈마 처리에 의해 상기 SiCO막 두께는 약 61%정도 감소되었다. 그리고 굴절율은 1.51에서 1.38로 감소되었다. 반면, 유전율은 2.7에서 3.9로 1.2정도 증가되었다. 이와 같이, 산소 플라즈마 처리에 의해 상기 SiOC막의 유전율이 크게 증가되므로 이를 층간절연막으로 사용한다는 것은 정전용량이 큰 기생 커패시터의 형성을 초래하여 바람직하지 못하다.Referring to Table 1, the thickness of the SiCO film was reduced by about 61% by oxygen plasma treatment. The refractive index was reduced from 1.51 to 1.38. On the other hand, the dielectric constant increased by 1.2 from 2.7 to 3.9. As described above, since the dielectric constant of the SiOC film is greatly increased by the oxygen plasma treatment, use of the SiOC film as an interlayer insulating film leads to the formation of a parasitic capacitor having a large capacitance, which is not preferable.
다음에는 자외선이 조사된 상기 SiOC막을 상기 산소 플라즈마에 노출시킨 실험예를 설명한다. 이과정에서 상기 반응챔버내의 조건은 상기 자외선이 조사되지 않은 상기 SiOC막을 상기 산소 플라즈마에 노출시킬 때와 동일한 조건이다.Next, an experimental example in which the SiOC film irradiated with ultraviolet rays is exposed to the oxygen plasma will be described. In this process, the conditions in the reaction chamber are the same as those when the SiOC film not irradiated with the ultraviolet rays is exposed to the oxygen plasma.
이 실험에 대한 결과는 표 2에 도시하였다.The results for this experiment are shown in Table 2.
*표 2, 자외선 조사된 SiOC막의 산소 플라즈마 처리 전, 후의 특성 변화* Table 2, Characteristics change before and after oxygen plasma treatment of UVC-irradiated SiOC film
상기 표 2를 참조하면, 상기 자외선 조사된 SiOC막을 산소 플라즈마에 노출시킨 경우, 상기 자외선 조사된 SiOC막의 두께는 약 4%정도 감소되었으나, 굴절율과 유전율은 변화가 없었다.Referring to Table 2, when the ultraviolet-rayed SiOC film was exposed to oxygen plasma, the thickness of the ultraviolet-rayed SiOC film was reduced by about 4%, but the refractive index and the dielectric constant did not change.
상기 표 1 및 표 2를 참조하면, 상기 SiOC막을 자외선으로 조사한 후, 상기 산소 플라즈마에 노출시키는 것이 자외선 조사 없이 산소 플라즈마에 노출시키는 것 보다 두께 감소는 작았으나, 굴절율이나 유전율은 상기 산소 플라즈마 처리 전, 후에 일정하게 유지됨을 알 수 있다. 결론적으로, 상기 SiOC막을 저유전 층간절연막으로서 사용하기 위해선 상기 SiOC막을 산소 플라즈마에 노출시키기 전에 상기 SiOC막을 자외선으로 조사하는 것이 바람직하다.Referring to Tables 1 and 2, after the SiOC film was irradiated with ultraviolet rays, the exposure to the oxygen plasma was smaller than the exposure to the oxygen plasma without ultraviolet irradiation, but the refractive index and the dielectric constant were before the oxygen plasma treatment. It can be seen that it is kept constant afterwards. In conclusion, in order to use the SiOC film as a low dielectric interlayer insulating film, it is preferable to irradiate the SiOC film with ultraviolet rays before exposing the SiOC film to oxygen plasma.
이와 같이, 상기 제2 절연막(46)에 대해 상기 자외선 조사(48)를 실시하면, 상기 제2 절연막(46)의 막질은 상기 자외선 조사(48)를 실시하지 않았을 때 보다 산소 플라즈마에 대한 내성이 높아져서 산소 플라즈마에 의해 상기 제2 절연막(46)의 굴절율이나 유전율이 변화되지 않는다. 즉, 산소 플라즈마 처리후에도 상기 제2 절연막(46)의 유전상수는 낮은 값으로 유지된다.As such, when the ultraviolet irradiation 48 is applied to the second insulating film 46, the film quality of the second insulating film 46 is more resistant to oxygen plasma than when the ultraviolet irradiation 48 is not performed. As a result, the refractive index and the dielectric constant of the second insulating film 46 are not changed by the oxygen plasma. That is, even after the oxygen plasma treatment, the dielectric constant of the second insulating film 46 is maintained at a low value.
도 4는 상기 제1 금속막 패턴(42)을 노출시키는 비어홀(52)을 형성하는 단계를 나타낸다.4 illustrates forming a via hole 52 exposing the first metal layer pattern 42.
도 4를 참조하면, 상기 자외선 조사(48)후, 상기 제2 절연막(46)의 전면에 포토레지스트막(도시않음)을 도포한다. 이어서, 상기 포토레지스트막을 패터닝하여 상기 제2 절연막(46)의 상기 제1 금속막 패턴(42)에 대응하는 부분을 커버링하는 포토레지스트막 패턴(50)을 형성한다. 상기 포토레지스트막 패턴(50)을 식각마스크로 사용하여 상기 제2 절연막(46)과 상기 제1 절연막(44)을 순차적으로 이방성식각한다. 상기 이방성식각은 상기 제1 금속막 패턴(42)이 노출될 때 까지 실시한다.상기 이방성식각에 의해 상기 제1 및 제2 절연막(44, 46)에 상기 제1 금속막 패턴(42)의 표면을 노출시키는 비어홀(52)이 형성된다. 상기 포토레지스트막 패턴(50)을 에싱하여 제거하기 위해 상기 포토레지스트막 패턴(50)이 형성되어 있는 결과물의 전면을 산소 플라즈마로 처리한다. 상기 제2 절연막(46)은 상기 자외선 조사(48)에 의해 산소 플라즈마에 대한 내성이 있으므로 상기 포토레지스트막 패턴(50)을 제거하는 과정에서 두께가 감소하는 것외에 어떤 특성 변화를 일으키지 않는다.Referring to FIG. 4, after the ultraviolet irradiation 48, a photoresist film (not shown) is coated on the entire surface of the second insulating film 46. Subsequently, the photoresist film is patterned to form a photoresist film pattern 50 covering a portion corresponding to the first metal film pattern 42 of the second insulating film 46. The second insulating layer 46 and the first insulating layer 44 are sequentially anisotropically etched using the photoresist layer pattern 50 as an etching mask. The anisotropic etching is performed until the first metal film pattern 42 is exposed. The surface of the first metal film pattern 42 is formed on the first and second insulating layers 44 and 46 by the anisotropic etching. A via hole 52 is formed to expose the via. The entire surface of the resultant on which the photoresist film pattern 50 is formed is treated with oxygen plasma to ashed and remove the photoresist film pattern 50. Since the second insulating layer 46 is resistant to the oxygen plasma by the ultraviolet irradiation 48, the second insulating layer 46 does not cause any characteristic change except that the thickness is reduced in the process of removing the photoresist layer pattern 50.
계속해서, 도 5에 도시한 바와 같이, 상기 제2 절연막(46) 상에 상기 비어홀(52)을 통해 상기 제1 금속막 패턴(42)과 접촉되는 제2 금속막 패턴(56)을 형성한다.Subsequently, as shown in FIG. 5, a second metal film pattern 56 is formed on the second insulating film 46 and in contact with the first metal film pattern 42 through the via hole 52. .
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당분야에서의 통상의 지식을 가진 자에 의하여 실시 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.
상기한 바와 같이, 본 발명에 의한 반도체 장치의 금속막 형성방법은 상, 하 금속막 패턴 사이에 형성되는 층간절연막에 상기 상, 하 금속막 패턴을 연결하기 위한 비어홀을 형성하기 전에 상기 층간절연막에 대해 자외선 조사를 실시한다. 이렇게 함으로써 후속 비어홀 형성용 감광막 패턴을 제거하기 위한 산소 플라즈마 처리공정에 의해, 상기 층간절연막, 특히 상기 저 유전 상수의 절연막의 유전율이 증가되는 것을 방지하여 인접한 금속막 패턴 사이에 형성되는 기생 커패시터의 정전용량이 증가되는 것을 방지할 수 있다. 이 결과, 전기적으로 분리되어 있는 금속막 패턴을 통해서 흐르는 전기적 신호가 교란되는 것과 상기 금속막 패턴 사이에 형성되는 기생 커패시터에 의해 상기 신호의 전달이 지연되는 것을 방지할 수 있다.As described above, in the method of forming a metal film of the semiconductor device according to the present invention, before the via hole for connecting the upper and lower metal film patterns is formed in the interlayer insulating film formed between the upper and lower metal film patterns. Ultraviolet irradiation is performed. This prevents an increase in the dielectric constant of the interlayer insulating film, particularly the low dielectric constant insulating film by an oxygen plasma treatment process for removing a subsequent via hole forming photoresist pattern, thereby preventing electrostatic capacitance of parasitic capacitors formed between adjacent metal film patterns. Dose increase can be prevented. As a result, it is possible to prevent the electrical signal flowing through the electrically separated metal film patterns from being disturbed and delayed transmission of the signal by parasitic capacitors formed between the metal film patterns.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR19970065542 | 1997-12-03 | ||
| KR1019970065542 | 1997-12-03 |
| Publication Number | Publication Date |
|---|---|
| KR100295043B1true KR100295043B1 (en) | 2001-10-19 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980020027AExpired - Fee RelatedKR100295043B1 (en) | 1997-12-03 | 1998-05-30 | Method for forming a metal film of a semiconductor device using an insulating film having a low dielectric constant as an interdielectric layer |
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| KR (1) | KR100295043B1 (en) |
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