본 발명은 이동 통신 시스템에서 셀 탐색 방법에 관한 것으로서, 특히 비동기식 광대역(Wide Band) 코드 분할 다중 접속(Code Division Multiple Access : CDMA)방식의 이동 통신 시스템에서 단말기에 전원을 인가한 후 기지국에서 제공되는 신호로부터 셀을 탐색하는 방식을 개선하여 빠른 시간 내에 셀을 탐색하기에 적당하도록 한 이동 통신 시스템에서 셀 탐색 장치 및 방법에 관한 것이다.The present invention relates to a cell discovery method in a mobile communication system. In particular, the present invention relates to a cell discovery method, which is provided by a base station after power is applied to a terminal in a mobile communication system using an asynchronous wideband code division multiple access (CDMA) scheme. An apparatus and method for searching for a cell in a mobile communication system that improves the way of searching for a cell from a signal and is suitable for searching for a cell in a short time.
비동기식 광대역 코드 분할 다중 접속 방식의 이동 통신 시스템에서, 기지국에서 제공되는 신호로부터셀 탐색 방법은 크게 3단계로 이루어진다.In the mobile communication system of the asynchronous wideband code division multiple access method, the cell searching method from the signal provided from the base station is largely composed of three steps.
첫째 단계(ST1)는 도1에 도시된 바와 같이 기지국에서 제공되는 동기 채널신호(SCH1)를 검출하여 1 프레임(frame) 당 16개의 슬롯(slot) 중 임의의 한 슬롯의 시작점을 알아내는 단계이다.The first step ST1 is a step of detecting the start point of any one of 16 slots per frame by detecting the synchronization channel signal SCH1 provided from the base station as shown in FIG. .
둘째 단계(ST2)는 첫째 단계에서 알아낸 슬롯의 시작점을 기준으로 하여 기지국에서 제공되는 동기 채널신호(SCH2)를 검출하여 보내어진 동기 채널신호(SCH2)가 어느 기지국 그룹에 속하고 프레임의 시작 부분은 어디인지를 알아내는 단계이다.In the second step ST2, the synchronization channel signal SCH2 transmitted by detecting the synchronization channel signal SCH2 provided from the base station based on the starting point of the slot found in the first step belongs to which base station group and the beginning of the frame. Is the step of figuring out where.
셋째 단계(ST3)는 둘째 단계에서 알려진 기지국 그룹과 프레임 시작 부분에 관한 정보를 이용하여 공통 제어 물리채널(Common Control Physical Channel : CCPCH1) 신호를 검출하여 둘째 단계에서 밝혀진 기지국 그룹 속에 있는 총 16개의 기지국 중에서 어느 기지국인지를 알아내는 단계이다. 이때, 만일 셋째 단계에서 기지국에서 제공된 셀을 못 찾았을 때는 첫째 단계로 돌아가 앞에서 설명한 모든 단계를 반복하여 실행한다.The third step (ST3) detects the common control physical channel (CCPCH1) signal by using the base station group and the frame start information known in the second step, so that a total of 16 base stations in the base station group identified in the second step are detected. This step is to find out which base station. In this case, if the cell provided by the base station is not found in the third step, the process returns to the first step and repeats all the steps described above.
도 2는 위에서 설명한 셀 탐색을 실행하는 단말기의 수신단의 블록 구성도이다.2 is a block diagram illustrating a receiver of a terminal for performing cell search described above.
도 2를 참조하여 첫째 단계를 설명하면, 기지국에서 송신된 채널 동기신호(SCH1)는 곱셈기(10,14)에 각각 입력되어 싸인 및 코사인 반송파가 곱해진다. 각 곱셈기(10,14)에서 출력되는 I 및 Q 채널신호는 펄스 성형 필터(11,15)를 각각 통과한 후 직교골드코드 Cp에 매치된 정합 여파기(Matched Filter)(12,16)를 통과하여 필터링된다. 이어, 각 정합 여파기(Matched Filter)(12,16)에서 출력되는 I, Q 채널신호는 제곱기(13,17)에 각각 입력되어 각각의 결과를 제곱한 후 덧셈기(18)를 통하여 더해진다. 즉, 미리 지정된 수의 슬롯에 걸쳐 이상에서 설명한 과정을 반복하고 그 결과를 덧셈기(18)에 저장된 값에 더한다.Referring to FIG. 2, the first step is described. The channel synchronization signal SCH1 transmitted from the base station is input to the multipliers 10 and 14, respectively, to multiply the sine and cosine carriers. The I and Q channel signals output from the multipliers 10 and 14 pass through the pulse shaping filters 11 and 15, respectively, and then through matched filters 12 and 16 matched to the orthogonal gold code Cp. Is filtered. Subsequently, the I and Q channel signals output from the matched filters 12 and 16 are input to the squarers 13 and 17, respectively, to square the respective results and then added through the adder 18. That is, the above-described process is repeated over a predetermined number of slots and the result is added to the value stored in the adder 18.
이어, 덧셈기(18)에서 출력되는 동기신호에 대한 상관값은 누산기(19)를 통해 미리 정해진 기준 슬롯동안 그 결과를 각각의 칩지연 별로 따로 누적시킨다. 즉, 누산기(19)는 입력신호의 칩지연별로 각각 계산된 각 슬롯마다의 결과를 한 슬롯 간격으로 더해서 저장해 주는 역할을 한다.Subsequently, the correlation value for the synchronization signal output from the adder 18 accumulates the result separately for each chip delay through the accumulator 19 during a predetermined reference slot. That is, the accumulator 19 adds and stores the result of each slot calculated for each chip delay of the input signal at one slot interval.
이어, 누산기(19)의 출력신호는 비교기(20)로 입력되어 칩지연별로 각각 계산된 상관값을 차례대로 비교하여 가장 큰 상관값을 나타내는 위치 정보(기준시점으로부터의 칩지연)를 알아낸다. 즉, 비교기(20)는 누산기(19)의 출력값들 중에서 특정 임계값을 넘는 것들을 찾아 그 중에서 최대값을 갖는 수신 신호의 지연을 찾아내어, 이 지연값을 바로 슬롯의 시작점으로 판단한다. 이때, 특정 임계값을 넘는 칩 지연이 없으면 마이크로 프로세서(미도시)는 다시 100으로 표시되는 첫째 단계를 반복시키도록 제어한다.Subsequently, the output signal of the accumulator 19 is input to the comparator 20 to compare the calculated correlation values for each chip delay in order to find out the position information (chip delay from the reference point) indicating the largest correlation value. That is, the comparator 20 finds the ones exceeding a specific threshold value among the output values of the accumulator 19, finds the delay of the received signal having the maximum value, and determines this delay value as the starting point of the slot. At this time, if there is no chip delay exceeding a certain threshold, the microprocessor (not shown) controls to repeat the first step indicated by 100 again.
200으로 표시되는 둘째 단계에서는 첫째 단계에서 비교기(20)가 특정 임계값을 넘는 칩 지연이 발생한 경우, 슬롯의 시작점에 관한 위치 정보를 상관부(21)에 알려주게 된다. 그러면 첫째 단계에서 수신되어 펄스 성형 필터(11,15)를 통과한 신호에 각 슬롯마다 17개의 상관기(각각 C1에서 C17까지의 직교골드코드)를 첫째 단계에서 알려준 슬롯의 시작점에서부터 적용시킨 다음 I와 Q 채널을 제곱기(22,23)를 통하여 각각 제곱하여 더한 값을 기억장치인 메모리(25)에 저장한다. 그리고 이러한 과정을 16개의 슬롯, 즉 한 프레임에 걸쳐 반복한다.In the second stage, indicated by 200, when the comparator 20 generates a chip delay exceeding a specific threshold in the first stage, the comparator 20 informs the correlator 21 of the position information regarding the starting point of the slot. 17 correlators (orthogonal gold codes from C1 to C17, respectively) for each slot are applied to the signal received in the first stage and passed through the pulse shaping filters 11 and 15 from the beginning of the slot indicated in the first stage, and then I and The Q channels are squared through the squarers 22 and 23, respectively, and stored in the memory 25, which is a storage device. This process is repeated over 16 slots, i.e., one frame.
이어, 비교기(26)는 메모리(25)에 저장된 값들 중에서 코드 그룹 테이블과 비교하여 수신 신호의 코드 그룹과 프레임의 시작점을 알아낸다. 그리고 이러한 정보를 셋째 단계의 채널 코드 저장부(31)와 상관부(34)로 알려준다. 이때, 만일, 비교기(26)가 특정 임계값을 넘는 코드 그룹을 알아내지 못하면, 마이크로 프로세서는 기지국에서 제공되는 동기 채널신호로부터 첫째 단계를 반복하도록 제어한다.The comparator 26 then compares the code group table among the values stored in the memory 25 to find the code group of the received signal and the start point of the frame. This information is informed to the channel code storage unit 31 and the correlator 34 of the third step. At this time, if the comparator 26 does not find a code group exceeding a certain threshold value, the microprocessor controls to repeat the first step from the synchronization channel signal provided from the base station.
300으로 표시되는 셋째 단계는 기지국에서 수신되어 펄스 성형 필터(11,15)를 통과한 신호에 둘째 단계에서 알려준 프레임의 시작점에 채널 코드 저장부(31)에서 제공되는 채널 구분 코드를 I와 Q 채널에 곱셈기(32,33)를 통하여 각각 곱한다. 이어, 둘째 단계에서 알아낸 코드 그룹에 속하는 16개의 상관기(각각의 상관기는 초기값이 서로 다른 골드코드를 사용한다)로 이루어진 상관부(34)를 심볼단위로 적용시켜 상관한다. 이어, 상관부(24)에서 출력되는 신호를 제곱기(35,36)를 통하여 각각 제곱하고, 제곱기(35,36)에서 각각 출력되는 I와 Q 채널을 덧셈기(37)를 이용하여 더한 후 저장한다.The third step, denoted by 300, is a channel identification code provided from the channel code storage unit 31 at the start of the frame indicated in the second step to the signal received from the base station and passed through the pulse shaping filters 11 and 15, and the I and Q channels. Multiply by the multipliers 32 and 33, respectively. Subsequently, the correlation unit 34, which consists of 16 correlators belonging to the code group found in the second step (each correlator uses a gold code having a different initial value), is applied by symbol unit. Subsequently, the signals output from the correlator 24 are squared through the squarers 35 and 36, and the I and Q channels respectively output from the squarers 35 and 36 are added using the adder 37. Save it.
이러한 과정을 미리 정해진 수의 심볼 동안 반복한 다음 그 결과를 누산기(38)에 더한 후 비교기(39)를 이용하여 더해진 값들 중에서 특정 임계값을 넘는 것들을 찾아 그 중에서 최대값을 갖는 상관기(즉, 앞의 16개의 서로 다른 골드코드 중의 하나)를 알아내어 기지국에서 전송한 셀을 탐색하게 된다. 그러나, 이때에도 만일, 특정 임계값을 넘는 코드 그룹을 알아내지 못하면, 마이크로 프로세서는 다시 기지국에서 전송되는 동기 채널신호를 이용하여 첫째 단계를 반복하도록 제어한다.Repeat this process for a predetermined number of symbols and then add the result to accumulator 38 and use comparator 39 to find the ones that exceed a certain threshold among the added values and correlate them with the maximum of them (i.e., the front). One of the 16 different gold codes of) is found and the cell transmitted from the base station is searched. However, even in this case, if it is not possible to find a code group exceeding a certain threshold, the microprocessor controls to repeat the first step using the synchronization channel signal transmitted from the base station.
그러나, 이와 같은 종래기술은 마지막 셋째 단계에서 기지국에서 전송한 셀을 찾지 못했을 때는 첫째 단계로 돌아가 다시 첫째 단계에서 셋째 단계를 반복하여 실행한다. 이러한 종래의 기술은 기지국에서 전송한 셀을 탐색하는데 대부분의 계산량과 시간이 걸리는 첫째 단계부터 다시 실행된다. 따라서, 셀 탐색동작시 마지막 셋째 단계에서 셀을 탐색하지 못할 경우 기지국에서 전송한 셀의 탐색 시간이 상당히 지연되어 전체 셀 탐색 동작의 효율성이 낮아진다.However, in the prior art, when the cell transmitted from the base station is not found in the last third step, the process returns to the first step and repeats the third step from the first step. This conventional technique is executed again from the first step, which takes most of the computation and time to search for the cell transmitted from the base station. Therefore, if the cell cannot be searched in the last third step during the cell search operation, the search time of the cell transmitted from the base station is significantly delayed, thereby reducing the efficiency of the entire cell search operation.
본 발명의 목적은 이상에서 언급한 종래 기술의 문제점을 감안하여 안출한 것으로서, 비동기식 광대역 코드 분할 다중 접속(Code Division Multiple Access : CDMA)방식의 이동 시스템에서 기지국에서 단말기로 동기 채널신호를 전송한 경우, 첫째 단계에서 슬롯의 시작점을 알아낼 때, 하나가 아닌 다수개를 알아내어 둘째 또는 셋째 단계의 실행시 오류가 발생될 경우 첫째 단계를 실행하지 않고 첫째 단계에서 알아낸 다른 슬롯의 시작점을 이용하여 둘째 단계를 반복하여 수행하도록 제어하거나, 첫째 단계를 반복하여 수행되도록 제어하고 이와 동시에 첫째 단계에서 알아낸 다른 슬롯의 시작점을 이용하여 둘째 단계를 반복하여 수행하도록 제어하는 이동 통신 시스템 셀 탐색 방법을 제공하기 위한 것이다.SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned problems of the prior art, and in the case of transmitting a sync channel signal from a base station to a terminal in a mobile broadband asynchronous broadband code division multiple access (CDMA) scheme. When determining the starting point of a slot in the first step, if it finds a number instead of one and an error occurs when executing the second or third step, do not execute the first step but use the starting point of the other slot found in the first step. To provide a mobile communication system cell search method of controlling to perform a step repeatedly, or to control to perform the first step repeatedly and to perform the second step repeatedly by using a starting point of another slot found in the first step. It is for.
이상과 같은 목적을 달성하기 위한 본 발명의 일 특징에 따르면, 이동 통신 시스템 셀 탐색 방법이 기지국에서 제공되는 동기 채널신호를 검출하여 한 프레임당 구성되는 다수개의 슬롯 중 미리 설정된 우선 순위를 갖는 다수개의 슬롯의 시작점을 알아내는 첫째 단계와, 상기 첫째 단계에서 알아낸 다수개의 슬롯의 시작점중 가장 우선 순위가 높은 슬롯의 시작점을 기준으로 하여 기지국에서 제공되는 동기 채널신호를 검출하여 상기 동기 채널신호가 어느 기지국 그룹에 속하고 프레임의 시작 부분은 어디인지를 알아내는 둘째 단계와, 상기 둘째 단계에서 알려진 기지국 그룹과 프레임 시작 부분에 관한 정보를 이용하여 공통 제어 물리채널신호를 검출하여 상기 둘째 단계에서 알아낸 기지국 그룹 속에 있는 다수개의 기지국 중에서 가장 신호의 세기가 강한 기지국과 동기를 맞추는 셋째 단계와, 상기 둘째 단계에서 상기 동기 채널신호가 어느 기지국 그룹에 속하고 프레임의 시작 부분은 어디인지를 알아내지 못한 경우 또는 셋째 단계에서 상기 기지국에서 제공된 셀을 알아내지 못한 경우에는 상기 첫째 단계에서 알아낸 다수개의 슬롯의 시작점중 두 번째 우선 순위가 높은 슬롯의 시작점을 기준으로 하여 상기 둘째 단계를 반복하여 실행하는 단계로 이루어진다.According to an aspect of the present invention for achieving the above object, a mobile communication system cell search method detects a synchronization channel signal provided from a base station and a plurality of slots having a predetermined priority among a plurality of slots configured per frame The first step of determining the starting point of the slot and the starting point of the slot having the highest priority among the starting points of the plurality of slots found in the first step are detected. The second step is to find out where the beginning of the frame belongs to the base station group, and the common control physical channel signal is detected by using the information about the base station group and the beginning of the frame, which are known in the second step. The three signals of the largest number of base stations in the base station group The third step of synchronizing with the strong base station and the second step does not determine which base station group the synchronization channel signal belongs to and where the start of the frame is found. If not, the second step is repeated based on the starting point of the second highest priority slot among the starting points of the plurality of slots found in the first step.
도 1은 종래의 셀 탐색 과정을 나타낸 흐름도.1 is a flowchart illustrating a conventional cell search process.
도 2는 종래 및 본 발명에 따른 셀 탐색기의 블록 구성도.2 is a block diagram of a conventional cell searcher according to the present invention.
도 3은 본 발명의 일 실시 예에 따른 셀 탐색 과정을 나타낸 흐름도.3 is a flowchart illustrating a cell searching process according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10, 14, 32, 33, 39, 40, 44, 45 : 곱셈기Multipliers: 10, 14, 32, 33, 39, 40, 44, 45
11, 15 : 펄스 성형 필터 12, 16 : 정합 여파기11, 15: pulse shaping filter 12, 16: matching filter
13, 17, 22, 23, 35, 36 : 제곱기13, 17, 22, 23, 35, 36: squarer
18, 24, 37 : 덧셈기 19, 38 : 누산기18, 24, 37: Adder 19, 38: Accumulator
20, 26, 39 : 비교기 21, 34 : 상관부20, 26, 39: comparators 21, 34: correlator
25 : 메모리 31, 43 : 채널 코드 저장부25: memory 31, 43: channel code storage unit
42 : PN 코드 발생기 45 : QPSK 복조기42: PN code generator 45: QPSK demodulator
46 : 버퍼46: buffer
이하 본 발명의 바람직한 일 실시 예에 따른 구성 및 작용을 첨부된 도면을 참조하여 설명한다.Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명의 일 실시 예에 따른 셀 탐색과정을 나타낸 흐름도이다.3 is a flowchart illustrating a cell searching process according to an embodiment of the present invention.
도 3을 참조하면, 본 발명은 기지국에서 제공되는 동기 채널신호를 검출하여 한 프레임당 구성되는 다수개의 슬롯 중 미리 설정된 우선 순위를 갖는 다수개의 슬롯의 시작점을 알아내는 첫째 단계(ST1)와, 첫째 단계(ST1)에서 알아낸 다수개의 슬롯의 시작점중 가장 우선 순위가 높은 슬롯의 시작점을 기준으로 하여 기지국에서 제공되는 동기 채널신호를 검출하여 상기 동기 채널신호가 어느 기지국 그룹에 속하고 프레임의 시작 부분은 어디인지를 알아내는 둘째 단계(ST2)와, 둘째 단계(ST2)에서 알려진 기지국 그룹과 프레임 시작 부분에 관한 정보를 이용하여 공통 제어 물리채널신호를 검출하여 둘째 단계(ST2)에서 알아낸 기지국 그룹 속에 있는 다수개의 기지국 중에서 가장 신호의 세기가 강한 기지국과 동기를 맞추는 셋째 단계(ST3)와, 둘째 단계(ST2)에서 상기 동기 채널신호가 어느 기지국 그룹에 속하고 프레임의 시작 부분은 어디인지를 알아내지 못한 경우 또는 셋째 단계에서 상기 기지국에서 제공된 셀을 알아내지 못한 경우에는 첫째 단계(ST1)에서 알아낸 다수개의 슬롯의 시작점중 두 번째 우선 순위가 높은 슬롯의 시작점을 기준으로 하여 둘째 단계(ST2)를 반복하여 실행하도록 제어하는 넷째 단계로 이루어진다.Referring to FIG. 3, the present invention provides a first step (ST1) of detecting a start channel of a plurality of slots having a predetermined priority among a plurality of slots configured per frame by detecting a synchronization channel signal provided from a base station. The sync channel signal provided from the base station is detected based on the start point of the slot having the highest priority among the start points of the plurality of slots found in step ST1, and the sync channel signal belongs to which base station group and the start of the frame. The base station group found in the second step (ST2) by detecting the common control physical channel signal by using the second step (ST2) to find out where is, and the information about the base station group and the frame start part in the second step (ST2) The third step (ST3) and the second step (ST2) to synchronize with the base station of the strongest signal strength among the plurality of base stations in the If it is not possible to find out which base station group the synchronization channel signal belongs to and where the start of the frame is, or if the cell provided by the base station is not found in the third step, the number of slots found in the first step ST1 is determined. A fourth step of controlling to execute the second step (ST2) repeatedly based on the starting point of the slot of the second highest priority among the starting point.
여기서, 넷째 단계는 첫째 단계(ST1)에서 알아낸 다수개의 슬롯의 시작점중 두 번째 우선 순위가 높은 슬롯의 시작점을 기준으로 하여 둘째 단계(ST2)를 반복하여 실행하도록 제어하면서, 동시에 첫째 단계(ST1)를 반복하여 실행하도록 제어할 수도 있다.Here, the fourth step is controlled to execute the second step ST2 repeatedly based on the start point of the second higher priority slot among the starting points of the plurality of slots found in the first step ST1, and at the same time, the first step ST1 You can also control to run) repeatedly.
도 2는 본 발명에 따른 기지국에서 전송한 셀 탐색을 실행하는 단말기의 수신단의 블록 구성도이다.2 is a block diagram of a receiver of a terminal for performing cell search transmitted from a base station according to the present invention.
도 2를 참조하여 첫째 단계를 설명하면, 기지국에서 송신된 채널 동기신호(SCH1)는 곱셈기(10,14)에 각각 입력되어 싸인 및 코사인 반송파가 곱해진다. 각 곱셈기(10,14)에서 출력되는 I 및 Q 채널신호는 펄스 성형 필터(11,15)를 각각 통과한 후 직교골드코드 Cp에 매치된 정합 여파기(Matched Filter)(12,16)를 통과하여 필터링된다. 이어, 각 정합 여파기(Matched Filter)(12,16)에서 출력되는 I, Q 채널신호는 제곱기(13,17)에 각각 입력되어 각각의 결과를 제곱한 후 덧셈기(18)를 통하여 더해진다. 즉, 미리 지정된 수의 슬롯에 걸쳐 이상에서 설명한 과정을 반복하고 그 결과를 덧셈기(18)에 저장된 값에 더한다.Referring to FIG. 2, the first step is described. The channel synchronization signal SCH1 transmitted from the base station is input to the multipliers 10 and 14, respectively, to multiply the sine and cosine carriers. The I and Q channel signals output from the multipliers 10 and 14 pass through the pulse shaping filters 11 and 15, respectively, and then through matched filters 12 and 16 matched to the orthogonal gold code Cp. Is filtered. Subsequently, the I and Q channel signals output from the matched filters 12 and 16 are input to the squarers 13 and 17, respectively, to square the respective results and then added through the adder 18. That is, the above-described process is repeated over a predetermined number of slots and the result is added to the value stored in the adder 18.
이어, 덧셈기(18)에서 출력되는 동기신호에 대한 상관값은 누산기(19)를 통해 미리 정해진 기준 슬롯동안 그 결과를 칩별로 각각 누적시킨다. 즉, 누산기(19)는 입력신호의 칩별로 각각 계산된 각 슬롯마다의 결과를 한 슬롯 간격으로 더해서 저장해 주는 역할을 한다.Subsequently, the correlation value for the synchronization signal output from the adder 18 accumulates the result for each chip for a predetermined reference slot through the accumulator 19. That is, the accumulator 19 adds and stores the result of each slot calculated for each chip of the input signal at one slot interval.
이어, 누산기(19)의 출력신호는 비교기(20)로 입력되어 칩별로 각각 게산된 상관값을 차례대로 비교하여 설정된 우선 순위를 갖는 상관값을 나타내는 위치 정보(기준 시점으로부터의 칩지연)를 다수개 알아낸다. 즉, 비교기(20)는 누산기(19)의 출력값들 중에서 특정 임계값을 넘는 것들을 다수개 찾아 그 중에서 최대값을 갖는 수신 신호의 지연을 찾아내어, 이 지연값을 바로 슬롯의 시작점으로 판단한다. 이때, 특정 임계값을 넘는 칩 지연이 없으면 마이크로 프로세서(미도시)는 다시 100으로 표시되는 첫째 단계를 반복시키도록 제어한다.Subsequently, the output signal of the accumulator 19 is input to the comparator 20 to sequentially compare the correlation values calculated for each chip in order to obtain a plurality of positional information (chip delay from the reference time point) indicating the correlation values having a set priority. Find out the dog. That is, the comparator 20 finds a plurality of output values of the accumulator 19 exceeding a specific threshold value, finds a delay of a received signal having a maximum value among them, and determines this delay value as a starting point of a slot. At this time, if there is no chip delay exceeding a certain threshold, the microprocessor (not shown) controls to repeat the first step indicated by 100 again.
여기서, 종래의 기슬과 대비해 볼 때 본 발명의 특징은 비교기(20)가 누산기(19)의 출력값들 중에서 특정 임계값을 넘는 것들을 다수개 찾아내고, 마이크로 프로세서는 다수개의 결과값을 설정된 우선 순위로 관리한다는 것이다.Here, in comparison with the conventional technology, the feature of the present invention is that the comparator 20 finds a plurality of output values of the accumulator 19 that exceed a certain threshold value, and the microprocessor sets a plurality of result values as a set priority. To manage.
200으로 표시되는 둘째 단계에서는 첫째 단계에서 비교기(20)가 특정 임계값을 넘는 칩 지연이 발생한 경우, 슬롯의 시작점에 관한 위치 정보를 상관부(21)에 알려주게 된다. 그러면 첫째 단계에서 수신되어 펄스 성형 필터(11,15)를 통과한 신호에 각 슬롯마다 17개의 상관기(각각 C1에서 C17까지의 직교골드코드)를 첫째 단계에서 알려준 슬롯의 시작점에서부터 적용시킨 다음 I와 Q 채널을 제곱기(22,23)를 통하여 각각 제곱하여 더한 값을 기억장치인 메모리(25)에 저장한다. 그리고 이러한 과정을 16개의 슬롯, 즉 한 프레임에 걸쳐 반복한다.In the second stage, indicated by 200, when the comparator 20 generates a chip delay exceeding a specific threshold in the first stage, the comparator 20 informs the correlator 21 of the position information regarding the starting point of the slot. 17 correlators (orthogonal gold codes from C1 to C17, respectively) for each slot are applied to the signal received in the first stage and passed through the pulse shaping filters 11 and 15 from the beginning of the slot indicated in the first stage, and then I and The Q channels are squared through the squarers 22 and 23, respectively, and stored in the memory 25, which is a storage device. This process is repeated over 16 slots, i.e., one frame.
이어, 비교기(26)는 메모리(25)에 저장된 값들 중에서 특정 임계값을 넘는 것들을 찾아내어, 찾아낸 임계값중에서 코드 그룹 테이블과 비교하여 수신 신호의 코드 그룹과 프레임의 시작점을 알아낸다. 그리고 이러한 정보를 셋째 단계의 채널 코드 저장부(31)로 알려준다. 이때, 만일, 비교기(26)가 특정 임계값을 넘는 코드 그룹을 알아내지 못하면, 마이크로 프로세서는 기지국에서 제공되는 동기 채널신호로부터 첫째 단계를 반복하도록 제어한다. 또한, 선택적으로 기지국에서 제공되는 동기 채널신호로부터 첫째 단계를 반복하도록 제어하면서도 이와 동시에 첫째 단계에서 알아낸 2번째 우선 순위를 갖는 슬롯 시작점을 이용하여 둘째 단계를 반복하여 실행하도록 제어한다.The comparator 26 then finds ones exceeding a certain threshold among the values stored in the memory 25 and compares the code group table with the found thresholds to find the start point of the code group and frame of the received signal. This information is informed to the channel code storage unit 31 of the third step. At this time, if the comparator 26 does not find a code group exceeding a certain threshold value, the microprocessor controls to repeat the first step from the synchronization channel signal provided from the base station. Further, while selectively controlling the first step from the synchronization channel signal provided by the base station, the second step is repeatedly executed by using the slot starting point having the second priority found in the first step.
300으로 표시되는 셋째 단계는 기지국에서 수신되어 펄스 성형 필터(11,15)를 통과한 신호에 둘째 단계에서 알려준 프레임의 시작점에 채널 코드 저장부(31)에서 제공되는 채널 구분 코드를 I와 Q 채널에 곱셈기(32,33)를 통하여 각각 곱한다. 이어, 둘째 단계에서 알아낸 코드 그룹에 속하는 16개의 상관기(각각의 상관기는 초기값이 서로 다른 골드코드를 사용한다)로 이루어진 상관부(34)를 심볼단위로 적용시켜 상관한다. 이어, 상관부(24)에서 출력되는 신호를 제곱기(35,36)를 통하여 각각 제곱하고, 제곱기(35,36)에서 각각 출력되는 I와 Q 채널을 덧셈기(37)를 이용하여 더한 후 저장한다.The third step, denoted by 300, is a channel identification code provided from the channel code storage unit 31 at the start of the frame indicated in the second step to the signal received from the base station and passed through the pulse shaping filters 11 and 15, and the I and Q channels. Multiply by the multipliers 32 and 33, respectively. Subsequently, the correlation unit 34, which consists of 16 correlators belonging to the code group found in the second step (each correlator uses a gold code having a different initial value), is applied by symbol unit. Subsequently, the signals output from the correlator 24 are squared through the squarers 35 and 36, and the I and Q channels respectively output from the squarers 35 and 36 are added using the adder 37. Save it.
이러한 과정을 미리 정해진 수의 심볼 동안 반복한 다음 그 결과를 누산기(38)에 더한 후 비교기(39)를 이용하여 더해진 값들 중에서 특정 임계값을 넘는 것들을 찾아 그 중에서 최대값을 갖는 상관기(즉, 앞의 16개의 서로 다른 골드코드 중의 하나)를 알아내어 기지국에서 전송한 셀을 탐색하게 된다. 그러나, 이때 셋째 단계에 오류가 발생되면, 마이크로 프로세서는 기지국에서 제공되는 동기 채널신호로부터 첫째 단계를 반복하도록 제어한다. 또한, 선택적으로 기지국에서 제공되는 동기 채널신호로부터 첫째 단계를 반복하도록 제어하면서도 이와 동시에 첫째 단계에서 알아낸 2번째 우선 순위를 갖는 슬롯 시작점을 이용하여 둘째 단계를 반복하여 실행하도록 제어한다.Repeat this process for a predetermined number of symbols and then add the result to accumulator 38 and use comparator 39 to find the ones that exceed a certain threshold among the added values and correlate them with the maximum of them (i.e., the front). One of the 16 different gold codes of) is found and the cell transmitted from the base station is searched. However, if an error occurs in the third step at this time, the microprocessor controls to repeat the first step from the synchronization channel signal provided from the base station. Further, while selectively controlling the first step from the synchronization channel signal provided by the base station, the second step is repeatedly executed by using the slot starting point having the second priority found in the first step.
이상의 본 발명을 요약하면, 첫째 단계에서 여러 개의 슬롯 시작점을 둘째 단계에 알려주고, 둘째 단계에서는 첫째 단계에서 알려준 슬롯 시작점중에서 가장 에너지가 큰 시작점에서 기지국 그룹과 프레임 동기를 찾아 셋째 단계로 알려준다. 따라서, 둘째 단계에서 실패했을 경우에는 마이크로 프로세서는 다시 첫째 단계를 반복함과 동시에 이전에 첫째 단계에서 알려준 여러 개의 슬롯 시작점중에서 에너지가 다음으로 큰 시작점에 대해서 둘째 단계를 반복하도록 제어한다. 셋째 단계에서는 둘째 단계에서 알려준 정보를 바탕으로 기지국을 찾게 된다. 그러나, 기지국을 찾지 못했을 때는 마이크로 프로세서는 첫째 단계와 둘째 단계에 오류가 발생했음을 인식하고, 첫째 단계에서 다시 기지국에서 전송한 신호가 센 기지국의 슬롯의 시작점을 찾기 시작하고 둘째 단계는 첫째 단계에서 찾은 새로운 정보가 올 때까지 첫째 단계로부터 받은 슬롯의 시작점중에서 다음으로 에너지가 큰 시작점에서 기지국 그룹과 프레임 동기를 찾아 셋째 단계로 알려준다. 이런 방식으로 계산량이 많고 계산 시간이 비교적 오래 걸리는 첫째 단계를 줄임으로써 전체 기지국 탐색 시간을 줄일 수 있다.In summary, in the first step, several slot start points are informed to the second step, and in the second step, the base station group and the frame synchronization are found at the highest energy starting point among the slot start points indicated in the first step, and the third step is informed. Therefore, if the second step fails, the microprocessor repeats the first step again and simultaneously controls the second step for the next-largest starting point of the multiple slot start points previously indicated in the first step. In the third step, the base station is found based on the information provided in the second step. However, when the base station is not found, the microprocessor recognizes that an error has occurred in the first and second stages, and in the first stage, the signal transmitted from the base station starts to find the starting point of the slot of the base station, and the second stage is found in the first stage. From the start point of the slot received from the first step until the new information comes in, the next step is to find the frame synchronization with the base station group and the third step. In this way, the overall base station discovery time can be reduced by reducing the first step, which is computationally expensive and takes relatively long computation time.
이상의 설명에서와 같은 본 발명에 따르면, 비동기식 광대역 코드 분할 다중 접속(Code Division Multiple Access : CDMA)방식의 이동 통신 시스템에서 기지국에서 단말기로 동기 채널신호를 전송한 경우, 첫째 단계에서 슬롯의 시작점을 알아내는 상관값을 미리 설정된 다수개를 출력한다. 따라서, 셀을 탐색하는 셋째 단계에서 기지국에서 전송한 셀을 찾지 못하면 셀을 탐색하는데 대부분의 계산 시간이 걸리는 첫째 단계부터 다시 실행하며, 동시에 첫 번째 단계에서알아낸 슬롯의 시작점들 중에서 그 다음으로 에너지가 큰 슬롯의 시작점을 이용하여 두 번째 단계를 실행하도록 제어한다.According to the present invention as described above, when a synchronization channel signal is transmitted from a base station to a terminal in an asynchronous wideband code division multiple access (CDMA) mobile communication system, the starting point of the slot is known in the first step. Outputs a plurality of preset correlation values. Therefore, if the third step of searching for the cell does not find the cell transmitted by the base station, it executes again from the first step, which takes most of the calculation time to search for the cell. Controls to execute the second step using the starting point of the larger slot.
이에 따라, 동기식에 비해 기지국에서 전송한 셀을 탐색하는데 어려운 비동기식 광대역 코드 분할 다중 접속방식의 이동 시스템에서 전체 셀 탐색 시간을 줄임으로써 단말기가 전원을 켠 후 빠른 시간 안에 통화가 가능토록 해 준다. 또한, 단말기의 위치가 핸드오프를 실행해야 될 장소에 있더라도 핸드오프도 신속히 할 수 있어 통화 중 끊김 현상을 줄일 수 있다. 그리고 부가적으로 단말기의 전력사용을 줄일 수 있다.Accordingly, in the mobile system of the asynchronous broadband code division multiple access method, which is more difficult to search for a cell transmitted from a base station than a synchronous one, the entire cell search time is reduced, so that a call can be made quickly after the terminal is turned on. In addition, even if the position of the terminal is in the place where the handoff should be performed, the handoff can be quickly, thereby reducing the interruption phenomenon. In addition, it is possible to reduce the power usage of the terminal.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061815AKR100281094B1 (en) | 1998-12-30 | 1998-12-30 | Cell navigation method in mobile communication system |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061815AKR100281094B1 (en) | 1998-12-30 | 1998-12-30 | Cell navigation method in mobile communication system |
| Publication Number | Publication Date |
|---|---|
| KR20000045257A KR20000045257A (en) | 2000-07-15 |
| KR100281094B1true KR100281094B1 (en) | 2001-02-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980061815AExpired - Fee RelatedKR100281094B1 (en) | 1998-12-30 | 1998-12-30 | Cell navigation method in mobile communication system |
| Country | Link |
|---|---|
| KR (1) | KR100281094B1 (en) |
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