JPS6481338A - Method of laying out semiconductor logic integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate wasteful bent of a wiring by wiring a region between lowermost and uppermost cell rows to be regarded as a wiring region at the time of wiring in a logic block, and wiring with the terminals of the cells disposed at the uppermost/lowermost cell rows to be regarded as the terminals of the upper/lower sides of the logic block at the time of wiring between the logic block and already designed block. CONSTITUTION:An imaginary boundary side is provided at a logic block. Then, terminals are set on the side of the block due to certain object function, and logic cells are disposed by considering connecting relations of the terminal and between the cells. Then, a schematic wiring route is determined in accordance with connecting requests of the terminal of the side of the block and between the disposed cells, and the terminals are actually wired therebetween on a region between the uppermost/lowermost cell rows in the block. The blocks are eventually wired therebetween. In this case, the terminals of upper/lower sides of the cells of the uppermost/lowermost cell rows of the block are recognized as the terminals of the upper/lower sides of the block, and wirings are performed.