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JPS6464073A - Image memory - Google Patents

Image memory

Info

Publication number
JPS6464073A
JPS6464073AJP62221694AJP22169487AJPS6464073AJP S6464073 AJPS6464073 AJP S6464073AJP 62221694 AJP62221694 AJP 62221694AJP 22169487 AJP22169487 AJP 22169487AJP S6464073 AJPS6464073 AJP S6464073A
Authority
JP
Japan
Prior art keywords
registers
elements
serial
bus
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62221694A
Other languages
Japanese (ja)
Inventor
Yasuo Masaki
Kimitoshi Hori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Minolta Co Ltd
Original Assignee
Minolta Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minolta Co LtdfiledCriticalMinolta Co Ltd
Priority to JP62221694ApriorityCriticalpatent/JPS6464073A/en
Priority to US07/239,749prioritypatent/US4912680A/en
Publication of JPS6464073ApublicationCriticalpatent/JPS6464073A/en
Pendinglegal-statusCriticalCurrent

Links

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Abstract

PURPOSE:To realize sequential image processing operation that is usually impossible by performing simultaneous serial input and output actions to an image memory and also realizing random access. CONSTITUTION:Writing registers WR0-WR7 are connected to the input parts of memory elements M0-M7 together with double system reading registers RR0-RR7 and MR0-MR7 connected to the output parts of the elements M0-M7 respectively. Then a random access bus 1 and a serial access bus 2 are connected to those registers RR0-RR7 and MR0-MR7 respectively. Data are successively latched every piece by the registers WR0-WR7 via the bus 2. When a prescribed number of pieces of data are stored, these data are written in the elements M0-M7 at one time. Thus a serial writing action is carried out. While the data read simultaneously out of the elements M0-M7 are temporarily latched by the registers RR0-RR7 and then outputted successively every piece to the bus 2. Thus a serial reading action is carried out.
JP62221694A1987-09-031987-09-03Image memoryPendingJPS6464073A (en)

Priority Applications (2)

Application NumberPriority DateFiling DateTitle
JP62221694AJPS6464073A (en)1987-09-031987-09-03Image memory
US07/239,749US4912680A (en)1987-09-031988-09-02Image memory having plural input registers and output registers to provide random and serial accesses

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP62221694AJPS6464073A (en)1987-09-031987-09-03Image memory

Publications (1)

Publication NumberPublication Date
JPS6464073Atrue JPS6464073A (en)1989-03-09

Family

ID=16770814

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP62221694APendingJPS6464073A (en)1987-09-031987-09-03Image memory

Country Status (1)

CountryLink
JP (1)JPS6464073A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JP2018010656A (en)*2008-02-282018-01-18メモリー テクノロジーズ リミティド ライアビリティ カンパニーExpanded utilization range for memory device
US10877665B2 (en)2012-01-262020-12-29Memory Technologies LlcApparatus and method to provide cache move with non-volatile mass memory system
US10983697B2 (en)2009-06-042021-04-20Memory Technologies LlcApparatus and method to share host system RAM with mass storage memory RAM
US11226771B2 (en)2012-04-202022-01-18Memory Technologies LlcManaging operational state data in memory module

Cited By (15)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US11829601B2 (en)2008-02-282023-11-28Memory Technologies LlcExtended utilization area for a memory device
US10540094B2 (en)2008-02-282020-01-21Memory Technologies LlcExtended utilization area for a memory device
US12417022B2 (en)2008-02-282025-09-16Memory Technologies LlcExtended utilization area for a memory device
JP2018010656A (en)*2008-02-282018-01-18メモリー テクノロジーズ リミティド ライアビリティ カンパニーExpanded utilization range for memory device
US11182079B2 (en)2008-02-282021-11-23Memory Technologies LlcExtended utilization area for a memory device
US11907538B2 (en)2008-02-282024-02-20Memory Technologies LlcExtended utilization area for a memory device
US11494080B2 (en)2008-02-282022-11-08Memory Technologies LlcExtended utilization area for a memory device
US10983697B2 (en)2009-06-042021-04-20Memory Technologies LlcApparatus and method to share host system RAM with mass storage memory RAM
US11775173B2 (en)2009-06-042023-10-03Memory Technologies LlcApparatus and method to share host system RAM with mass storage memory RAM
US11733869B2 (en)2009-06-042023-08-22Memory Technologies LlcApparatus and method to share host system RAM with mass storage memory RAM
US12360670B2 (en)2009-06-042025-07-15Memory Technologies LlcApparatus and method to share host system RAM with mass storage memory RAM
US11797180B2 (en)2012-01-262023-10-24Memory Technologies LlcApparatus and method to provide cache move with non-volatile mass memory system
US10877665B2 (en)2012-01-262020-12-29Memory Technologies LlcApparatus and method to provide cache move with non-volatile mass memory system
US11782647B2 (en)2012-04-202023-10-10Memory Technologies LlcManaging operational state data in memory module
US11226771B2 (en)2012-04-202022-01-18Memory Technologies LlcManaging operational state data in memory module

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