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JPS6423564A - Space type semiconductor device - Google Patents

Space type semiconductor device

Info

Publication number
JPS6423564A
JPS6423564AJP17983587AJP17983587AJPS6423564AJP S6423564 AJPS6423564 AJP S6423564AJP 17983587 AJP17983587 AJP 17983587AJP 17983587 AJP17983587 AJP 17983587AJP S6423564 AJPS6423564 AJP S6423564A
Authority
JP
Japan
Prior art keywords
layer
silicon layer
wiring
stuck
wiring electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17983587A
Other languages
Japanese (ja)
Inventor
Mitsuo Matsunami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp CorpfiledCriticalSharp Corp
Priority to JP17983587ApriorityCriticalpatent/JPS6423564A/en
Publication of JPS6423564ApublicationCriticalpatent/JPS6423564A/en
Pendinglegal-statusCriticalCurrent

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Abstract

PURPOSE:To make a device high-density and high-speed, by forming a wiring body on at least one layer of semiconductor single-crystalline layer so that it contains a passive element composed of materials other than a semiconductor. CONSTITUTION:A (n) channel MOSFET 4 is formed on a first silicon layer 1. Wiring electrodes 13-1-13-4 of the lowermost layers are formed with prescribed patterns on a protective insulating film 9 and on a protect insulating film 11 which covers a wiring electrode 10 except the upper surface of the electrode 10. After an interlayer insulating SiO2 film 14-3 and the wiring electrode 13-4 are covered with a polyimide film layer 16, the layer 16 is heated to become semihard and stuck on a second silicon layer 2, so that p-type impurities are diffused into the diffusion layer 6 and the MOSFET 4 becomes a (p) channel. A multilayer interconnection body 12' is formed ranging only up to the wiring electrode 13-3. A through hole 18 is formed, and a protection substrate 20 is stuck on an upper surface of the second silicon layer 2 with wax 21 in between, and a polyimide layer 16 is formed on a rear surface of the layer 2. After a sticking process, the upper surface of the second silicon layer 2 is covered with metallic films 22, 23, and a burial metallic layer 25 is formed by burial processing. Next the upper surface of the wiring electrode 26 is covered with the polyimide film layer 16. A third silicon layer 3 is stuck similarly.
JP17983587A1987-07-171987-07-17Space type semiconductor devicePendingJPS6423564A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP17983587AJPS6423564A (en)1987-07-171987-07-17Space type semiconductor device

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP17983587AJPS6423564A (en)1987-07-171987-07-17Space type semiconductor device

Publications (1)

Publication NumberPublication Date
JPS6423564Atrue JPS6423564A (en)1989-01-26

Family

ID=16072729

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP17983587APendingJPS6423564A (en)1987-07-171987-07-17Space type semiconductor device

Country Status (1)

CountryLink
JP (1)JPS6423564A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
EP0703623A1 (en)*1994-09-221996-03-27Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V.Method of fabrication of a vertical integrated circuit structure
JP2001015683A (en)*1999-04-022001-01-19Interuniv Micro Electronica Centrum Vzw Method for transferring ultra-thin substrate and method for manufacturing multilayer thin-film device using the method
JP2005012180A (en)*2003-05-282005-01-13Okutekku:Kk Semiconductor device and manufacturing method thereof
US6977392B2 (en)1991-08-232005-12-20Semiconductor Energy Laboratory Co., Ltd.Semiconductor display device
JP2009188400A (en)*2008-02-012009-08-20Promos Technologies Inc Semiconductor device having laminated structure and method of manufacturing the semiconductor device
JP2011159869A (en)*2010-02-022011-08-18Nec CorpLaminate structure of semiconductor device and method for manufacturing the same
US8338289B2 (en)2005-06-302012-12-25Shinko Electric Industries Co., Ltd.Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole
US8629059B2 (en)2008-06-102014-01-14Samsung Electronics Co., Ltd.Methods of forming integrated circuit chips having vertically extended through-substrate vias therein

Cited By (9)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US6977392B2 (en)1991-08-232005-12-20Semiconductor Energy Laboratory Co., Ltd.Semiconductor display device
EP0703623A1 (en)*1994-09-221996-03-27Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V.Method of fabrication of a vertical integrated circuit structure
JP2001015683A (en)*1999-04-022001-01-19Interuniv Micro Electronica Centrum Vzw Method for transferring ultra-thin substrate and method for manufacturing multilayer thin-film device using the method
JP2005012180A (en)*2003-05-282005-01-13Okutekku:Kk Semiconductor device and manufacturing method thereof
US8338289B2 (en)2005-06-302012-12-25Shinko Electric Industries Co., Ltd.Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole
JP2009188400A (en)*2008-02-012009-08-20Promos Technologies Inc Semiconductor device having laminated structure and method of manufacturing the semiconductor device
US8629059B2 (en)2008-06-102014-01-14Samsung Electronics Co., Ltd.Methods of forming integrated circuit chips having vertically extended through-substrate vias therein
US9219035B2 (en)2008-06-102015-12-22Samsung Electronics Co., Ltd.Integrated circuit chips having vertically extended through-substrate vias therein
JP2011159869A (en)*2010-02-022011-08-18Nec CorpLaminate structure of semiconductor device and method for manufacturing the same

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