【発明の詳細な説明】産業上の利用分野本発明は、半導体装置特にハロゲン元素を含む酸化膜を
有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly a semiconductor device having an oxide film containing a halogen element.
従来の技術従来からシリコン基板を酸化性雰囲気中を熱処理するこ
とによって得た酸化膜は、拡散のマスクやＰｎ接合を保
護するためのパッシベーション膜に用いられている。し
かしながら、これら酸化膜中には、可動イオンが含まれ
、しばしば、半導体装置の信頼性を欠いていた。その対
策として、塩素や臭素系ガス、たとえば、塩素ガス、臭
素ガス、塩化水素、臭化水素、トリクロルエチレン。BACKGROUND OF THE INVENTION Conventionally, an oxide film obtained by heat-treating a silicon substrate in an oxidizing atmosphere has been used as a diffusion mask and a passivation film for protecting a Pn junction. However, these oxide films contain mobile ions, and the reliability of semiconductor devices is often lacking. As a countermeasure, use chlorine or bromine gases such as chlorine gas, bromine gas, hydrogen chloride, hydrogen bromide, and trichlorethylene.
テトラクロルエチレンなどを含む雰囲気中で、得られた
酸化膜中の可動イオンは、塩素や臭素系ガスを含まない
雰囲気中で得られた酸化膜中の可動イオンよりも著しく
少なく、半導体装置の安定性を良化させることが知られ
ている。（たとえば、６“緒ヅしクトｏｗｔｖ“−χテ
ィＪ、Ｅｌｅｃｔｏｒｏｃｈｅｍ、Ｓｏｃ、１２１．ｍ６
Ｆ８３９゜１９７４のハロゲン添加による耐圧分布
の向上環）すなわち、酸化膜中の可動イオンたとえばナトリウムや
カリウム等のアルカリ金属は、塩素を含む雰囲気中で熱
処理することによって、捕獲され、酸化膜中で動きにく
くなることが知られている。この熱処理によって半導体
装置の電圧や温度に対する安定性は、極めて高くなって
いる。The number of mobile ions in the oxide film obtained in an atmosphere containing tetrachlorethylene etc. is significantly lower than that in the oxide film obtained in an atmosphere not containing chlorine or bromine gas, resulting in a stable semiconductor device. It is known to improve sex. (For example, 6 “Ozushiktoowtv”-χTJ, Electrochem, Soc, 121.m6
In other words, mobile ions in the oxide film, such as alkali metals such as sodium and potassium, are captured by heat treatment in an atmosphere containing chlorine, and are made to move in the oxide film. It is known that it can become difficult. This heat treatment makes the semiconductor device extremely stable with respect to voltage and temperature.
発明が解決しようとする問題点併しながら従来方法では、臭素ガスや塩素ガスは、特に
酸素や水蒸気の存在下においては、高温でシリコンと反
応し、シリコン表面を著しく腐食させる。シリコン表面
の腐食は、ホトエツチング工程での微細加工を阻害した
り、Ｐ−ｎ接合深さをばらつかせ、特性のばらつき発生
や製造歩留を低下させる原因となる。Problems to be Solved by the Invention However, in conventional methods, bromine gas or chlorine gas, especially in the presence of oxygen or water vapor, reacts with silicon at high temperatures and significantly corrodes the silicon surface. Corrosion on the silicon surface impedes microfabrication in the photoetching process, causes variations in the P-n junction depth, causes variations in characteristics, and reduces manufacturing yield.
問題点を解決するための手段前記問題点を解決するために本発明は、半導体基板又は
半導体素子を熱処理炉中のハロゲン元素を含み酸素元素
を含まない雰囲気内で所定の時間熱処理する第１の工程
と、酸素元素を含まないガスを前記熱処理炉中に流し、
所定の時間熱処理し、前記熱処理炉中の前記ハロゲンガ
スを除去する第２の工程と、前記半導体基板又は半導体
素子上に酸化膜を形成する第３の工程とを含む事を特徴
とする半導体装置の製造方法を提供する。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a first method in which a semiconductor substrate or a semiconductor element is heat-treated for a predetermined time in an atmosphere containing a halogen element but not containing an oxygen element in a heat treatment furnace. a step, flowing a gas containing no oxygen element into the heat treatment furnace;
A semiconductor device comprising: a second step of performing heat treatment for a predetermined time and removing the halogen gas in the heat treatment furnace; and a third step of forming an oxide film on the semiconductor substrate or semiconductor element. Provides a manufacturing method.
作用本発明を構成する第１の工程は、シリコン基板中にハロ
ゲン元素を拡散させることにあり、これにより、第３の
工程で酸化膜を形成した際、酸化膜中にハロゲン元素が
含有されることになる。また第２の工程は、第１の工程
から第３の工程に移行する際に石英壇壁等に含まれてい
るハロゲン元素が櫨内の雰囲気中に発生して、シリコン
基板を腐食する事を防止するため、非酸化性ガスを流す
ことによって、残存するハロゲン元素を石英櫨壁等より
追い出すためである。The first step constituting the present invention is to diffuse a halogen element into the silicon substrate, so that when an oxide film is formed in the third step, the halogen element is contained in the oxide film. It turns out. In addition, in the second step, when transitioning from the first step to the third step, halogen elements contained in the quartz platform walls, etc. are generated in the atmosphere inside the oak, and the silicon substrate is corroded. In order to prevent this, the remaining halogen elements are expelled from the quartz wall etc. by flowing a non-oxidizing gas.
実施例第１の実施例を第１図（ａ）について説明する。第１工
程として熱処理装炉１の熱処理管２内に直径１００ｍｍ
の５シリコン基板４を１００枚配置したのち、０．１％
の塩化水素を含む窒素ガスを毎分３ｅ流して、１１００
℃、１２０分加熱した。膜中で捕獲するハロゲン元素を
含む雰囲気中での熱処理方法である。したがって、本発
明は、最初に酸化膜を形成する熱処理工程はもちろんの
こと、既に不純物を拡散させであるシリコン基板の熱処
理にも適用できる。Embodiment A first embodiment will be explained with reference to FIG. 1(a). As the first step, a diameter of 100 mm is placed inside the heat treatment tube 2 of the heat treatment furnace 1.
After placing 100 pieces of 5 silicon substrates 4, 0.1%
of nitrogen gas containing hydrogen chloride was flowed at 3e per minute,
℃ for 120 minutes. This is a heat treatment method in an atmosphere containing halogen elements captured in the film. Therefore, the present invention can be applied not only to a heat treatment step for first forming an oxide film, but also to heat treatment of a silicon substrate in which impurities have already been diffused.
第３図は、ｎ型１ｏΩ帽のシリコン基板に各種酸化法で
厚み０．６μの酸化膜を形成し、その後、選択的にボロ
ンを拡散させて得たブレーナ型ダイオードの高温耐圧試
験（ＨＴＲＢ）結果を示す。第３図中従来法１は、酸素
中で形成した酸化膜、従来法２は、０．１％の塩化水素
を含む酸素ガス中で形成した酸化膜である。従来方法に
よって形成した酸化膜をパッシベーション膜として用い
たブレーナ型ダイオードの安定性は、時間の経過ととも
に劣化するが本発明法で得た酸化膜では、全く劣化して
いない。また第２図には、ＰＮＰ型ブレーナトランジス
タを製造する際のエミッタ拡散工程に本発明法を適用し
た効果例をｈＦＥの劣化とばらつきで示したものである
。ＰＮＰ型トランジスタは、ＰｏｎＰ のエピタキシ
ャルウェハーに選択的に順次リン、ボロンを拡散させて
得たものである。第２図は、特性の一例としてその後、
第２工程として、２ｏｅＺ分の流量で５分間窒素ガスを
流したのち、第３工程として温度６０℃の水中で酸素ガ
スを発泡させて得た水蒸気を含む酸素ガスを５ｅ／分の
流量で流し、１１００℃で１００分間熱処理した。この
熱処理によって、０．６μ僧の酸化膜が得られた。Figure 3 shows a high temperature withstand voltage test (HTRB) of a Brehner diode obtained by forming an oxide film with a thickness of 0.6μ on an n-type 10Ω silicon substrate using various oxidation methods, and then selectively diffusing boron. Show the results. In FIG. 3, Conventional Method 1 is an oxide film formed in oxygen, and Conventional Method 2 is an oxide film formed in oxygen gas containing 0.1% hydrogen chloride. The stability of a Brehner diode using an oxide film formed by the conventional method as a passivation film deteriorates over time, but the stability of the oxide film obtained by the method of the present invention does not deteriorate at all. Further, FIG. 2 shows an example of the effect of applying the method of the present invention to the emitter diffusion process when manufacturing a PNP type brainer transistor, in terms of deterioration and variation in hFE. The PNP transistor is obtained by selectively sequentially diffusing phosphorus and boron into a PonP epitaxial wafer. Figure 2 shows, as an example of the characteristics,
In the second step, nitrogen gas was flowed for 5 minutes at a flow rate of 2 oeZ, and in the third step, oxygen gas containing water vapor obtained by foaming oxygen gas in water at a temperature of 60°C was flowed at a flow rate of 5e/min. , heat treated at 1100°C for 100 minutes. Through this heat treatment, an oxide film with a thickness of 0.6 μm was obtained.
第２の実施例を第１図（ａ）について説明する。第１工
程として熱処理炉１の熱処理管２内に直径１００ｍのシ
リコン基板を１００枚配置したのち、温度３５℃のテト
ラクロルエチレン中を２素に発泡させて形成したテトラ
クロルエチレンを含む窒素ガスを毎分５ｅ流し、１１０
０℃、１２０分加熱した。その後、第２工程として２０
ｅ／分の流量で５分間窒素ガスを流したのち、温度６０
℃の水中で酸素ガスを発泡させて得た水蒸気を含む酸素
ガスを５ｅ／分の速度で流し、１１００℃で８０分間熱
処理し、この熱処理によって、０．９μｍの酸化膜を得
た。The second embodiment will be explained with reference to FIG. 1(a). As the first step, 100 silicon substrates with a diameter of 100 m are placed in the heat treatment tube 2 of the heat treatment furnace 1, and then nitrogen gas containing tetrachlorethylene, which is formed by foaming diarytetrachlorethylene in tetrachlorethylene at a temperature of 35°C, is introduced. 5e flow per minute, 110
Heated at 0°C for 120 minutes. After that, as the second step, 20
After flowing nitrogen gas for 5 minutes at a flow rate of e/min, the temperature was reduced to 60
Oxygen gas containing water vapor obtained by bubbling oxygen gas in water at 0.degree.
第１図（ｂ）には、典型的な本発明法の温度プログラム
を示した。FIG. 1(b) shows a typical temperature program for the method of the present invention.
発明の効果本発明は、上述のように、表面の腐食を防止し、微細加
工を阻害することなく、酸化膜中の可動イオンを酸化直
流電流増幅率（ｈＦＥ）の高温電圧試験の前後値を比較
して示した。第２図かられかるように、従来法１では、
試験後ｈＦＥは著しく低下し、安定性に欠ける。また、
従来法２では、試験前後の変化は少ないが、ｈＦＥのば
らつきが大きい。それに対し、本発明法は、ｈＦＥのば
らつきは少なく、また、試験前後のｈＦＥ変動も少ない
。Effects of the Invention As described above, the present invention prevents surface corrosion and oxidizes mobile ions in an oxide film without inhibiting microfabrication. A comparison is shown. As can be seen from Figure 2, in conventional method 1,
After the test, hFE decreased significantly and lacked stability. Also,
In conventional method 2, there are few changes before and after the test, but the variation in hFE is large. In contrast, in the method of the present invention, there is less variation in hFE, and there is also less variation in hFE before and after the test.
以上のように、本発明法によって得られた酸化膜を半導
体装置に用いれば、従来法に比らべて特性のばらつきが
少なくかつ信頼性の高い半導体装置が得られる。As described above, if the oxide film obtained by the method of the present invention is used in a semiconductor device, a semiconductor device with less variation in characteristics and higher reliability than the conventional method can be obtained.
また、実施例では、第１工程、゛第２工程および第３工
程の順で熱処理方法を示したが、第３工程、第２工程お
よび第１工程の順で熱処理を行なっても同一の効果が得
られたことは言うまでもない。In addition, in the examples, the heat treatment method was shown in the order of the first step, the second step, and the third step, but the same effect can be obtained even if the heat treatment is performed in the order of the third step, second step, and first step. Needless to say, this was obtained.
第１図の（ａ）は本発明法に用いた熱処理装置の断面図
、第１図の（ｂ）は本発明法の典型的温度プログラノシ
第２図はブレナー型ＰＮＰトランジスタに対するＨＴＲ
ＢテストによるｈＦＥの変動特性図、第３図はブレナー
型ダイオードに対するＨＴＲＢテストによる劣化率の比
較図である。１・・・・・・熱処理炉、２・・・・・・熱処理管、３
・・・・・・シリコン基板保持用器具、４・・・・・・
シリコン基板。代理人の氏名 弁理士 中尾敏男 ほか１名／−熱処理
炉２−−一薫処夏管３−−−シリコン基板第１図 珠樒娯４−一一シリコス【阪第１１程茅２二匿 第３二程第 ２ 図第３図FIG. 1(a) is a cross-sectional view of the heat treatment equipment used in the method of the present invention, FIG. 1(b) is a typical temperature programming diagram of the method of the present invention, and FIG.
FIG. 3 is a diagram showing the fluctuation characteristics of hFE according to the B test, and a comparison diagram of the deterioration rate according to the HTRB test for a Brenner diode. 1...Heat treatment furnace, 2...Heat treatment tube, 3
...Silicon substrate holding device, 4...
silicon substrate. Name of agent: Patent attorney Toshio Nakao and 1 other person/-Heat treatment furnace 2--1st heat treatment tube 3--Silicon substrate Figure 1 32 Step 2 Figure 3
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61148777AJPH0727897B2 (en) | 1986-06-25 | 1986-06-25 | Method for manufacturing semiconductor device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61148777AJPH0727897B2 (en) | 1986-06-25 | 1986-06-25 | Method for manufacturing semiconductor device |
| Publication Number | Publication Date |
|---|---|
| JPS635534Atrue JPS635534A (en) | 1988-01-11 |
| JPH0727897B2 JPH0727897B2 (en) | 1995-03-29 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61148777AExpired - LifetimeJPH0727897B2 (en) | 1986-06-25 | 1986-06-25 | Method for manufacturing semiconductor device |
| Country | Link |
|---|---|
| JP (1) | JPH0727897B2 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0473133U (en)* | 1990-11-05 | 1992-06-26 | ||
| EP0594172A1 (en)* | 1992-10-21 | 1994-04-27 | Akebono Brake Industry Co., Ltd. | Method for producing friction materials |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4978483A (en)* | 1972-11-30 | 1974-07-29 | ||
| JPS5373072A (en)* | 1976-12-13 | 1978-06-29 | Sony Corp | Formation of oxidized film |
| JPS5585068A (en)* | 1978-12-21 | 1980-06-26 | Sony Corp | Preparation of semiconductor device |
| JPS55166960A (en)* | 1979-06-14 | 1980-12-26 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
| JPS60231351A (en)* | 1984-04-27 | 1985-11-16 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4978483A (en)* | 1972-11-30 | 1974-07-29 | ||
| JPS5373072A (en)* | 1976-12-13 | 1978-06-29 | Sony Corp | Formation of oxidized film |
| JPS5585068A (en)* | 1978-12-21 | 1980-06-26 | Sony Corp | Preparation of semiconductor device |
| JPS55166960A (en)* | 1979-06-14 | 1980-12-26 | Fujitsu Ltd | Manufacture of field effect semiconductor device |
| JPS60231351A (en)* | 1984-04-27 | 1985-11-16 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0473133U (en)* | 1990-11-05 | 1992-06-26 | ||
| EP0594172A1 (en)* | 1992-10-21 | 1994-04-27 | Akebono Brake Industry Co., Ltd. | Method for producing friction materials |
| Publication number | Publication date |
|---|---|
| JPH0727897B2 (en) | 1995-03-29 |
| Publication | Publication Date | Title |
|---|---|---|
| CA1093217A (en) | Use of nitric oxide to clean a semiconductor | |
| US4231809A (en) | Method of removing impurity metals from semiconductor devices | |
| US2802760A (en) | Oxidation of semiconductive surfaces for controlled diffusion | |
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| JPS6327846B2 (en) | ||
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| KR960012288A (en) | Wafer for semiconductor device manufacturing and its manufacturing method | |
| JPS61113238A (en) | Selective surface treatment method | |
| JPH07130676A (en) | Boron diffusion into semiconductor wafer | |
| JPH01255217A (en) | Manufacture of semiconductor device | |
| JPS5980928A (en) | Manufacture of semiconductor device |
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |