【発明の詳細な説明】〈産業上の利用分野〉本発明はＭＯ５型半導体装置に関し、特には接合リーク
電流の少ないＭＯＳ型半導体装置に関するＯ〈従来の技術〉電気的に書き込み消去が可能な読み出し専用メモリであ
るＥＥＰＲＯＭや半導体上の容量に電荷を蓄えることで
記憶を行なうＤＲＡＭ等のメモリセルには、半導体基板
の空乏化を防ぐために半導体基板に形成されたドレイン
領域と素子分離領域領域七に連続し、半導体基板上に絶
縁膜を介して形成されたゲート領域下を覆う領域にドレ
イン領域と同一導電型の不純物領域が形成されている。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an MO5 type semiconductor device, and in particular to a MOS type semiconductor device with low junction leakage current. Memory cells such as EEPROMs, which are dedicated memories, and DRAMs, which perform storage by storing charge in a capacitor on a semiconductor, have a drain region and an element isolation region formed on the semiconductor substrate to prevent depletion of the semiconductor substrate. An impurity region of the same conductivity type as the drain region is continuously formed on the semiconductor substrate with an insulating film interposed therebetween in a region covering the bottom of the gate region.
第３図はＥＥＰＲＯＭ として用いられるＭＯＳトラン
ジスタの一部断面図である。ｐ型Ｓｉ基板１にはｎ型不
純物を拡散してドレイン領域２が形成され、また前記基
板１の素子分離領域にはフィールド絶縁膜３が形成され
る。ドレイン領域２とフィールド絶縁膜３０間の基板１
上には第１のゲート絶縁膜４が形成され、該第１のゲー
ト絶縁膜４上にはフローティングゲート５、層間絶縁膜
６及びコントロールゲート７が順次形成され、ゲートを
なしている。このゲートやドレイン領域２及びフィール
ド絶縁膜３を含むＳｉ基板１は絶縁膜８で覆われ、保護
されている。前記フィールド絶縁膜３直下の基板１には
チャネル・ストッパとしてｐ十不純物領域９が形成され
、隣接する素子間を電気的に分離している。更に基板ｌ
のゲート直下には、ｐ十不純物領域９とドレイン領域２
とに両側が隣接し、ｎ型不純物としてＡｓ を７Ｘ １
０” ｔｙｎ−２程度注入した高濃度ｎ＋不純物領域ｌ
Ｏが形成され、該不純物領域１０がＳｉ基板１の空乏化
を防いでいる。FIG. 3 is a partial cross-sectional view of a MOS transistor used as an EEPROM. A drain region 2 is formed in a p-type Si substrate 1 by diffusing n-type impurities, and a field insulating film 3 is formed in an element isolation region of the substrate 1. Substrate 1 between drain region 2 and field insulating film 30
A first gate insulating film 4 is formed thereon, and a floating gate 5, an interlayer insulating film 6, and a control gate 7 are sequentially formed on the first gate insulating film 4 to form a gate. The Si substrate 1 including the gate and drain regions 2 and the field insulating film 3 is covered and protected with an insulating film 8. A p-type impurity region 9 is formed as a channel stopper in the substrate 1 directly under the field insulating film 3, and electrically isolates adjacent elements. Furthermore, the board l
Immediately below the gate of , there is a p-type impurity region 9 and a drain region 2.
are adjacent on both sides, and As is added as an n-type impurity to 7X 1
Highly concentrated n+ impurity region implanted to the extent of 0” tyn-2
O is formed, and the impurity region 10 prevents the Si substrate 1 from being depleted.
〈発明が解決しようとする問題点〉Ｅ Ｅ Ｐ ＲＯＭ或いｆｄＤＲＡＭ等の半導体装置に
用いられるＭＯＳ）ランジスタのゲート絶縁膜は半導体
装置の高集積化・高密度化に伴って従来に比べ薄くなっ
ている。ところで、上記第３図からも明らかなように、
チャネル・ストッパをなすｐ十不純物領域９と高濃度ｎ
＋不純物領域１０とのＰＮ接合はゲート絶縁膜４下に形
成されている。このため、ゲート絶縁膜４が薄くなると
、リークの発生する電圧が低下し、使用電圧範囲内のゲ
ート電圧を印加した時にも前記ＰＮ接合にリーク電流が
発生してしまう。リーク電流はＥＥＰＲＯＭでは書き込
み消去時の電流損失となり、ＤＲＡＭにおいてはメモリ
保持特性の悪化の原因となる。<Problems to be solved by the invention> Gate insulating films of MOS transistors used in semiconductor devices such as EEPROM and fdDRAM have become thinner than before as semiconductor devices become more highly integrated and densely packed. ing. By the way, as is clear from Figure 3 above,
P impurity region 9 forming a channel stopper and high concentration n
A PN junction with the + impurity region 10 is formed under the gate insulating film 4. Therefore, when the gate insulating film 4 becomes thinner, the voltage at which leakage occurs decreases, and even when a gate voltage within the working voltage range is applied, a leakage current occurs in the PN junction. Leakage current causes current loss during writing and erasing in EEPROMs, and causes deterioration of memory retention characteristics in DRAMs.
このリーク電流の発生を抑制させるにｆｄＰＮ接合をよ
り厚い絶縁膜下に形成するとよい。そこで高濃度ｎ＋不
純物領域ＩＯ中のｎ型不純物をより高濃度にし、ｎ型不
純物をより広く拡散させることによってＰＮ接合をフィ
ールド絶縁膜３といったゲート絶縁膜４よジ厚い絶縁膜
下に形成する方法がある。しかし、この方法ではリーク
電流の発生を抑制することはできるが、第４図に示すよ
うにｎ型不純物が高濃度化することによって高濃度ｎ＋
不純物領域１０上の絶縁膜の寿命等の特性が悪化すると
いう問題が生じる。In order to suppress the occurrence of this leakage current, it is preferable to form the fdPN junction under a thicker insulating film. Therefore, there is a method of forming a PN junction under an insulating film that is thicker than the gate insulating film 4, such as the field insulating film 3, by increasing the concentration of the n-type impurity in the high concentration n+ impurity region IO and diffusing the n-type impurity more widely. There is. However, although this method can suppress the occurrence of leakage current, as shown in Figure 4, the high concentration of n+
A problem arises in that the characteristics such as the lifetime of the insulating film on the impurity region 10 are deteriorated.
く問題点を解決するための手段〉本発明は上述する問題点を解決するためになされたもの
で、第１の導電型の半導体基板に形成された第２の導電
型のドレイン領域と、前記半導体基板に形成された素子
分離領域とに両端が連続し、且つ前記半導体基板上に絶
縁膜を介して形成されたゲート領域下を覆う高濃度不純
物領域は、第２の導電型であり且つ拡散係数の異なる少
なくとも２種の不純物量からなるＭＯ５型半導体装置を
提供するものである。Means for Solving the Problems> The present invention has been made to solve the above problems, and includes a drain region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; A high concentration impurity region whose both ends are continuous with the element isolation region formed on the semiconductor substrate and which covers the bottom of the gate region formed on the semiconductor substrate via an insulating film is of the second conductivity type and is diffused. The present invention provides an MO5 type semiconductor device comprising at least two kinds of impurity amounts having different coefficients.
〈作用〉本発明の如く、半導体基板の空乏化を防ぐための高濃度
不純物領域を拡散係数の異なる少なくとも２種の不純物
量にて形成することに、ｌ：り、空乏化を防ぐに足りる
従来とほぼ同じ不純物量であっても、高濃度不純物領域
を、ｒ、ジ広く形成することが可能になる。<Function> According to the present invention, by forming a high-concentration impurity region to prevent depletion of a semiconductor substrate with at least two types of impurity amounts having different diffusion coefficients, l: Even with approximately the same amount of impurity, it is possible to form a high concentration impurity region as wide as r.
〈実施例〉以下、図面を用いて本発明の詳細な説明するが、本発明
はこれに限定されるものではない。<Example> The present invention will be described in detail below with reference to the drawings, but the present invention is not limited thereto.
第１図（ａ）〜（ｄ）は本発明の一実施例の製造プロセ
スを示す断面図であるｏｐ型Ｓｉ基板ｌの主面上を洗浄
し、該主面上に５ｉ０２膜１３を３００〜厚さに順次形
成した後、Ｓｉ基板ｌ上の活性領域をレジス）１１で選
択的に覆い、前記レジスト１１をマスクにしてプラズマ
エツチングを行なって、第１図（ａ）の如くＳｉＯ２膜
１３とＳｉ３Ｎ４膜１２とをバターニングする。次いで
レジス）ＩＩをマスクとしてｐ型Ｓｉ基板】に寄生チャ
ネル防止のための硼素イオンを＋２０ＫｅＶでｌＸｌ０
ｃｍ 注入した後、レジストＩ＋を除去し、Ｓｉ
３Ｎ４膜１２をマスクにして９５０℃Ｈ２０雰囲気中で
、〜１ｏ時間の熱酸化を行なうと、第１図（ｂ）の如く
ｐ＋不純物領域９及び０７〜１．５μｍ の膜厚のフィ
ールド絶縁膜３が形成される。次いで上記Ｓｉ３Ｎ４膜
Ｉ２とＳｉＯ３膜１３を除去し、Ｓｉ基板１上を新たに
レジスト１４で選択的に覆い、該レジメ）１４をマスク
としてＳｉ基板ｌに砒素及びリンのイオン注入を行な−
で、第１及び第２の高濃度ｎ＋不純物領域＋５ａ、ｂを
形成する。次に前記レジス）＋４を除去した後、第１図
（ｃ）の如く熱酸化法によりＳｉ基板１上に５００〜１
００ＯＡ程度のゲート絶縁膜４を形成し、該ゲート絶縁
膜４上に電荷注入用の窪みを形成する。このゲート絶縁
膜４上に、ポリシリコンからなるフローティングゲート
５と層間絶縁膜６、及びリンをドープしたポリシリコン
からなるコントロールゲート７を順次形成する。この後
、第１図（ｄ）の如く前記コントロールゲート７をマス
クとしてＳｉ基板１に砒素を高濃度にイオン注入してド
レイン領域２を形成し、Ｓｉ基板ｌ全面をＰＳＧ等の絶
縁膜８で覆う。この絶縁膜８にコンタクトホール（図示
せず）を形成し、Ａｔ等からなる電極（図示せず）を形
成する。FIGS. 1(a) to 1(d) are cross-sectional views showing the manufacturing process of an embodiment of the present invention. The main surface of an op-type Si substrate 1 is cleaned, and a 5i02 film 13 is deposited on the main surface at a thickness of 300 to After sequentially forming the SiO2 film 13 to a certain thickness, the active region on the Si substrate 1 is selectively covered with a resist 11, and plasma etching is performed using the resist 11 as a mask to form a SiO2 film 13 as shown in FIG. 1(a). The Si3N4 film 12 is patterned. Next, using the resist II as a mask, boron ions were applied to the p-type Si substrate at +20 KeV to prevent parasitic channels.
cm After implantation, the resist I+ is removed and the Si
Using the 3N4 film 12 as a mask, thermal oxidation is performed at 950° C. for ~10 hours in a H20 atmosphere to form a p+ impurity region 9 and a field insulating film 3 with a thickness of 0.7 to 1.5 μm, as shown in FIG. 1(b). is formed. Next, the Si3N4 film I2 and the SiO3 film 13 are removed, the Si substrate 1 is selectively covered with a new resist 14, and arsenic and phosphorus ions are implanted into the Si substrate 1 using the resist 14 as a mask.
Then, first and second high concentration n+ impurity regions +5a and b are formed. Next, after removing the resist (resist) +4, as shown in FIG. 1(c), 50 to 1
A gate insulating film 4 having a thickness of about 000 OA is formed, and a recess for charge injection is formed on the gate insulating film 4. On this gate insulating film 4, a floating gate 5 made of polysilicon, an interlayer insulating film 6, and a control gate 7 made of phosphorus-doped polysilicon are sequentially formed. Thereafter, as shown in FIG. 1(d), arsenic is ion-implanted into the Si substrate 1 at a high concentration using the control gate 7 as a mask to form a drain region 2, and the entire surface of the Si substrate 1 is covered with an insulating film 8 such as PSG. cover. A contact hole (not shown) is formed in this insulating film 8, and an electrode (not shown) made of At or the like is formed.
上述の如く高濃度ｎ＋＋純物領域の不純物様として拡散
係数の大きいリンと小さい砒素の２種を用いることにＬ
す、リンにより第１の高濃度ｎ＋＋純物領域＋５ａが形
成され、ゲート絶縁膜４．ｒ。As mentioned above, L
A first high concentration n++ pure region +5a is formed of phosphorus, and the gate insulating film 4. r.
り厚いフィールド絶縁膜３の下で前記第１の高濃度ｎ十
不純物領域＋５ａとチャネル・ストッパ用のｐ十不純物
領域９とによるＰＮ接合が形成されるため、リーク電流
の発生を抑制できる。更に砒素に、ｒ、！ｌｌ第２の高
濃度ｎ＋＋純物領域＋５ｂが従来と同様に形成され、基
板の空乏化を防ぐことが可能になる。Since a PN junction is formed between the first high concentration n+ impurity region +5a and the p+ impurity region 9 for the channel stopper under the thick field insulating film 3, the generation of leakage current can be suppressed. Furthermore, arsenic, r,! A second high-concentration n++ pure region +5b is formed in the same manner as in the prior art, making it possible to prevent depletion of the substrate.
上記本実施例において、ｎ型不純物を基板にイオン注入
したが、本発明はこれに限定されるものではなく、拡散
等信の方法であってもよい。In the above embodiment, n-type impurities were ion-implanted into the substrate, but the present invention is not limited to this, and a method such as diffusion may be used.
第２図は高濃度ｎ＋＋純物領域を形成する際、砒素注入
量を７Ｘ］Ｏ”ＬＭ” にし、リン注入量を変化させ
た時のＰＮ接合のリーク電流の変化を表した図である。FIG. 2 is a diagram showing the change in leakage current of the PN junction when the arsenic implantation amount is set to 7X]O"LM" and the phosphorus implantation amount is changed when forming a high concentration n++ pure region.
同図から、リンを注入するとリーク電流が低下すること
は明らかである。また、砒素を７Ｘ Ｉ Ｏ”謡−２と
リンをｌＸｌ０”ｆｆ１２とを注入する、つｔりｎ型不
純物を８Ｘ］ ０ ” ｃｍ−２種度Ｓｉ基板に注入し
、高濃度ｎ＋＋純物領域を形成しても、第４図から明ら
かなように該高濃度ｎ＋＋純物領域上のゲート絶縁膜の
寿命は従来とほぼ変わらない。From the figure, it is clear that the leakage current decreases when phosphorus is injected. In addition, arsenic is implanted with 7X IO" 2 and phosphorus is implanted with 1X10"ff12, and n-type impurity is implanted with 8X] 0"cm-2 into the Si substrate to form a high concentration n++ impurity region. As is clear from FIG. 4, the life of the gate insulating film on the high-concentration n++ purity region is almost the same as in the prior art.
上記本実施例において高濃度ｎ＋＋純物領域をなし、拡
散係数の異なるｎ型不純物としてリンと砒素を用いたが
、本発明はこれに限定されるものではなく、リンとアン
チモンの組合せ、或いはリンと砒素とアンチモンの組合
せであってもよく、凍り他のｎ型不純物であっても上記
と同様の効果が得られるならば、それを用いてもよい。In the above embodiment, phosphorus and arsenic were used as n-type impurities that formed a high concentration n++ purity region and had different diffusion coefficients, but the present invention is not limited to this, and a combination of phosphorus and antimony, or phosphorus A combination of arsenic, antimony, and other n-type impurities may also be used as long as the same effect as described above can be obtained.
〈発明の効果〉本発明に、ｌ：９、リーク電流の減小をゲート絶縁膜の
特性を悪化させることな〈実施することが可能になる。<Effects of the Invention> According to the present invention, it is possible to reduce the leakage current at 1:9 without deteriorating the characteristics of the gate insulating film.
したがって、本発明は信頼性の高いＭＯ５型半導体装置
の製造に寄与するものである。Therefore, the present invention contributes to manufacturing highly reliable MO5 type semiconductor devices.
第１図（ａ）〜（ｄ）は本発明の一実施例の製造プロセ
スを示す断面図、第２図ｉｄ ＩＪン注入量に対するリ
ーク電流の変化を示す図、第３図は従来例を示す十断面図、第４図は高濃度ｎ 不純物領域をなす層不純物
濃度に対する前記高濃度ｎ＋＋純物領域上のゲート絶縁
膜の寿命の変化を示す図である０１・・・ｐ型Ｓｉ基板
２・・・ドレイン領域 ３・・・フィールド絶縁膜
４・・・ゲート絶縁膜 ５・・・フローティングゲート
６・・・層間絶縁膜 ７・・・コントロールゲート
８・・・絶縁膜 ９・・・ｐ＋＋純物領域１５ａ・・・
第１の高濃度ｎ＋＋純物領域 ＋５ｂ・・・第２の高濃
度ｎ＋不不純頭領−域理人 弁理士 杉 山 毅 至 （他１名）◆目目１
◆目番（Ａｓ、Ｐ目目目舎目目リン波へ量（σが）第２図第１図第３図０／ ２３４ ５ ６ ７ｘ／Ｑ／ｒｎイ万虎押濱人
ｔ（ｃが２）第４図手続補正書特願昭６２−１１３３８５２、発明の名称ＭＯＳ型半導体装置３、補正をする者事件との関係 特許出願人住 所 弓５４５大阪市阿倍野区長池町２２番２２号名
称 （５０４）シャープ株式会社代表者 辻 晴 雄４、代理人７、補正の内容（１）明細書の第５頁第１９行のｒ６０００ＡＪを「１
０００〜２０００Ａ」と訂正します０（２）明細書の第
６頁第６行の「α 」を「ｃｒｎ」と訂正します。以上Figures 1 (a) to (d) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, Figure 2 is a diagram showing changes in leakage current with respect to IJ injection amount, and Figure 3 is a diagram showing a conventional example. FIG. 4 is a diagram showing the change in the lifetime of the gate insulating film on the high concentration n++ purity region with respect to the layer impurity concentration forming the high concentration n impurity region. 01...p-type Si substrate 2. ...Drain region 3...Field insulating film
4... Gate insulating film 5... Floating gate 6... Interlayer insulating film 7... Control gate
8... Insulating film 9... P++ pure region 15a...
First high concentration n++ pure region +5b...Second high concentration n+ impurity head region- Area Attorney Patent Attorney Takeshi Sugiyama (1 other person) ◆ Eye 1
◆Mock number (As, P Amount (σ) of the eyes, eyes, eyes, eyes, eyes, eyes, eyes, eyes, phosphorus waves) 2) Figure 4 Written amendment to the procedure Patent application No. 62-113385 2. Name of the invention MOS type semiconductor device 3. Relationship with the person making the amendment Patent applicant address Yumi 545 22-22 Nagaike-cho, Abeno-ku, Osaka-shi Name (504) Sharp Corporation Representative Haruo Tsuji 4, Agent 7 Contents of amendment (1) r6000AJ on page 5, line 19 of the specification was changed to “1
000-2000A" 0 (2) Correct "α" on page 6, line 6 of the specification to "crn". that's all
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62113385AJPH0642546B2 (en) | 1987-05-08 | 1987-05-08 | MOS semiconductor device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62113385AJPH0642546B2 (en) | 1987-05-08 | 1987-05-08 | MOS semiconductor device |
| Publication Number | Publication Date |
|---|---|
| JPS63278276Atrue JPS63278276A (en) | 1988-11-15 |
| JPH0642546B2 JPH0642546B2 (en) | 1994-06-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62113385AExpired - LifetimeJPH0642546B2 (en) | 1987-05-08 | 1987-05-08 | MOS semiconductor device |
| Country | Link |
|---|---|
| JP (1) | JPH0642546B2 (en) |
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|---|---|---|---|---|
| US5539217A (en)* | 1993-08-09 | 1996-07-23 | Cree Research, Inc. | Silicon carbide thyristor |
| US5719409A (en)* | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
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|---|---|---|---|---|
| JPS60223165A (en)* | 1984-04-19 | 1985-11-07 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6276676A (en)* | 1985-09-30 | 1987-04-08 | Toshiba Corp | MOS type semiconductor integrated circuit device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60223165A (en)* | 1984-04-19 | 1985-11-07 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6276676A (en)* | 1985-09-30 | 1987-04-08 | Toshiba Corp | MOS type semiconductor integrated circuit device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539217A (en)* | 1993-08-09 | 1996-07-23 | Cree Research, Inc. | Silicon carbide thyristor |
| US5719409A (en)* | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
| US5831288A (en)* | 1996-06-06 | 1998-11-03 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
| Publication number | Publication date |
|---|---|
| JPH0642546B2 (en) | 1994-06-01 |
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| US5489791A (en) | Field effect transistor having impurity regions of different depths and manufacturing method thereof | |
| US4141027A (en) | IGFET integrated circuit memory cell | |
| US4646118A (en) | Semiconductor memory device | |
| JPH09232448A (en) | Thin film transistor and method of manufacturing the same | |
| JPH08167705A (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
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