【発明の詳細な説明】〔産業上の利用分野〕本発明はＧａＡｓ等化合物半導体を主に用いた絶縁ゲー
ト型トランジスタ等の半導体装直に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices such as insulated gate transistors mainly using compound semiconductors such as GaAs.
本発明は化合物半導体単結晶層をチャンネル領域に用い
た絶縁ゲート型トランジスタで、チャンネル領域とゲー
ト型絶縁膜の間に１００原子層以下のシリコン単結晶薄
膜を挿入して化合物半導体チャンネル領域とゲート絶縁
膜の間の界面準位の低減を図ったものである。The present invention is an insulated gate transistor using a compound semiconductor single crystal layer as a channel region, and a silicon single crystal thin film of 100 atomic layers or less is inserted between the channel region and gate type insulating film to insulate the compound semiconductor channel region and gate. This is intended to reduce the interface level between the films.
ＧａＡｓ等化合物半導体を用いたトランジスタは主にシ
ョットキーゲート型（ＭＥＳ）電界効果トランジスタ（
ＦＥＴ）であり、最近ＨＥＭＴ、ＨＢＴ等が開発されて
いる。一方、Ｓｉでは絶縁ゲート型ＦＥＴ特にＭＯＳ
Ｆ ＥＴが高集積回路に用いられている。化合物半導体
でＭＯＳ Ｆ ＥＴを用いないのは主にＳｉにおけるＳ
ｉＯ□のように良質の絶縁膜が形成しにくいことと、化
合物半導体のＭＯ３構造において界面準位が多いことに
起因する。また、半導体としてＧｅを用いた場合も同様
である。Transistors using compound semiconductors such as GaAs are mainly Schottky gate type (MES) field effect transistors (
FET), and recently HEMT, HBT, etc. have been developed. On the other hand, Si is used for insulated gate FETs, especially MOS
FETs are used in highly integrated circuits. Compound semiconductors that do not use MOS FETs are mainly S in Si.
This is due to the difficulty in forming a high-quality insulating film like iO□ and the fact that there are many interface states in the MO3 structure of a compound semiconductor. Further, the same applies when Ge is used as the semiconductor.
（発明が解決しようとする問題点〕本発明はＧａＡｓ等化合物半導体などＳｉ以外の半導体
を用いた絶縁ゲート型トランジスタを提供し、高速・高
集積ＭＯ５ＩＣの実現を可能ならしめるものである。(Problems to be Solved by the Invention) The present invention provides an insulated gate transistor using a semiconductor other than Si, such as a compound semiconductor such as GaAs, and makes it possible to realize a high-speed, highly integrated MO5IC.
本発明におけるＭＯＳＦＥＴは、Ｐ型ＧａＡｓチャンネ
ル領域と該領域を挟んで互いに離間するＮ型ソースおよ
びドレイン領域とチャンネル領域上に設けられたゲート
絶縁膜と該絶縁膜上に設けられたゲート電極より成り、
前記チャンネル領域とデー４絶縁膜の間に１００原子層
以下のシリコン単結晶薄膜を挿入したものである。 Ｇ
ａＡｓ以外には他のｍ−ｖ化合物半導体やＧｏなど■族
半導体が用いられる。The MOSFET in the present invention consists of a P-type GaAs channel region, an N-type source and drain region spaced apart from each other with the region in between, a gate insulating film provided on the channel region, and a gate electrode provided on the insulating film. ,
A silicon single crystal thin film of 100 atomic layers or less is inserted between the channel region and the Day 4 insulating film. G
Other than aAs, other m-v compound semiconductors and group III semiconductors such as Go are used.
シリコン単結晶薄膜は非常に薄いので電子または正札の
多くはシリコン薄膜よりもＧａＡｓチャネル領域を流れ
るため移動度が大きい。またチャンネル領域とゲート絶
縁膜の間の界面準位はＳｉとＳｉｎｇ界面のため充分小
なくできる。さらに、シリコン薄膜は非常に薄いのでＧ
ａＡｓとの格子定数の不整合があっても欠陥は発生しに
くい、チャンネル領域の表面電位即ち、しきい電圧ｖｔ
ｈはチャンネル領域の不純物密度および分布、ゲート絶
縁膜の種類や膜厚、ゲート電極の材料などでも制御され
るが、シリコン薄膜の原子層数（膜厚）、添加不純物の
導電型および添加密度によっても制御できる。Since the silicon single crystal thin film is very thin, most of the electrons or regular particles flow through the GaAs channel region than in the silicon thin film, so their mobility is higher. Further, the interface level between the channel region and the gate insulating film can be made sufficiently small due to the interface between Si and Sing. Furthermore, since the silicon thin film is very thin,
Even if there is a mismatch in lattice constant with aAs, defects are unlikely to occur.The surface potential of the channel region, that is, the threshold voltage vt
Although h is controlled by the impurity density and distribution in the channel region, the type and thickness of the gate insulating film, and the material of the gate electrode, h is also controlled by the number of atomic layers (thickness) of the silicon thin film, the conductivity type of the added impurity, and the doping density. can also be controlled.
以下に図面を用いて本発明を詳述する。The present invention will be explained in detail below using the drawings.
＋１１実施例１ （第１図）第１図には本発明によるＭＯＳ Ｆ ＥＴの断面構造例
を示す、ｐ型ＧａＡｓ層１の表面をｐ型チャンネル４と
し、これを挟んでＧａＡｓによるｎ型ソースおよびドレ
イン領域２．４が設けられ、ｐチャンネル頭載４上には
Ｓｔ単結晶薄１１！ＪＴ、ゲート絶＆！膜５が形成され
、さらにその上にはゲート電極６を設けている。ＧａＡ
ｓ層ｌの表面結晶面は特に限定はないがＳｉ単結晶が成
長しやすい面であることが望ましく、例えば（１００１
面などが用いられる＊ Ｓｉｎ膜７の厚みは制御可能で
極力薄いことが望ましく単原子層〜１００原子層である
。ゲート絶縁膜５にはＳｉＯ□をはじめＳｉＮなどが使
用できる。 ＳｉＯ□としては熱酸化膜やＣＶＤ酸化膜
が用いられる。ゲート絶縁膜５の厚みやチャンネル長さ
は任意の値を選択できる。ｐチャンネル領域４はＧａＡ
ｓ０外にＩｎＰなど他のｍ−ｖ半導体、Ｇｅなどの■族
半導体も用いることができる。+11 Example 1 (Fig. 1) Fig. 1 shows an example of the cross-sectional structure of a MOS FET according to the present invention. and a drain region 2.4 are provided on the p-channel head 4, and an St single crystal thin layer 11! JT, Gate Zetsu &! A film 5 is formed, and a gate electrode 6 is further provided thereon. GaA
The surface crystal plane of the s-layer l is not particularly limited, but it is desirable that it be a plane on which Si single crystals can easily grow; for example, (1001
*The thickness of the Sin film 7 is controllable and desirably as thin as possible, ranging from a monoatomic layer to 100 atomic layers. For the gate insulating film 5, SiO□, SiN, etc. can be used. A thermal oxide film or a CVD oxide film is used as the SiO□. The thickness of the gate insulating film 5 and the channel length can be arbitrarily selected. p channel region 4 is GaA
In addition to s0, other m-v semiconductors such as InP and group II semiconductors such as Ge can also be used.
（２）実施例２（第２図）第２図は本発明のＭＯＳ Ｆ ＥＴの他の断面構造例を
示す、この例ではｐ型Ｓｉ領域１０上にｐ型ＧａＡｓチ
ャンネル領域４を島状に設け、Ｓｔ薄＠１．ゲー）Ｓｉ
０□５．ゲート電極６をその上に形成したものである。(2) Example 2 (FIG. 2) FIG. 2 shows another example of the cross-sectional structure of the MOS FET of the present invention. In this example, a p-type GaAs channel region 4 is formed in an island shape on a p-type Si region 10. Provided, St thin@1. Game) Si
0□5. A gate electrode 6 is formed thereon.
フィールド絶縁膜１６に設けたコンタクト開孔を通して
ソースおよびドレイン電極１２．１３を形成している。Source and drain electrodes 12 and 13 are formed through contact openings provided in field insulating film 16.
ｐ型Ｓｉ領域１０の結晶面はＧａＡｓ単結晶が成長しや
すいことが望ましく、例えば［１００１面から数度傾い
た面などが選ばれる。ｐ型ＧａＡｓチャンネル領域４の
厚みは任意であるが典型的には０．１〜２μｍ程度に選
択される。It is desirable that the crystal plane of the p-type Si region 10 is such that a GaAs single crystal can grow easily, and for example, a plane tilted by several degrees from the [1001 plane is selected. Although the thickness of the p-type GaAs channel region 4 is arbitrary, it is typically selected to be about 0.1 to 2 μm.
（３）実施例３（第３図）第３図ｆａｌ 〜（ｅ）には本発明のＭＯＳ Ｆ ＥＴ
の模式的エネルギー・バンド図（ゲート電圧がＯｖのと
き）を示す６図中、Ｍはゲート電極、 ＯＸはゲート絶
縁膜、 ＣＢは伝導帯、 ＶＢは価電子帯でＰＬはフェ
ルミ・レベルを表わす、ＳｉとＧａＡｓは電子親和力お
よび禁制帯幅が異なるのでバンド不連続ΔＥｃ、 ΔＥ
ｖが生じる。伝導帯側にはΔＥｃ−電子親和力の差＝０
．０６ｅＶ、価電子帯側にはΔＥｖ−禁制帯幅の差−Δ
［ＩＣ＃０．２６ｅＶができるといわれている。第３図
（ａ）はＰ型ＧａＡｓ１ｉ４上のＳｉ薄膜７の不純物密
度が低いとき、第３図（ｂｌはＳｉ薄膜７にはｐ型不純
物を比較的高密度で添加したときでエンハンスメント型
に近く、第３図（Ｃ１はＳｉｎ膜７にｎ型不純物を添加
したときでデプレッション型に近くなる。即ち、このＭ
ＯＳＦＥＴのしきい電圧ｖｔｈはＳｉ！膜７の添加不純
物の導電型、密度で制御可能なことを示す。実際には、
ＳｉとＧａＡｓ０間でバンドの不連続性があるので、こ
の境界で空乏層または電位障壁が形成されバンドは曲が
るため、しきい電圧ｖｔｈはＳｉ薄膜７の厚みの関数で
もある。ＧａＡｓチャンネル領域４の速い電子伝導を有
効に利用するためには、Ｓｉｎ膜７の厚みはできるだけ
薄いことが望ましく、理想的には１原子層であり実質的
には数原子層〜１００原子層である。Ｓｉ薄膜７の厚み
が極度に薄いとＳｉのエネルギー準位が量子化するが、
本発明ではこれは重要ではない。(3) Example 3 (Fig. 3) Fig. 3 fal to (e) shows the MOS FET of the present invention.
In Figure 6 showing the schematic energy band diagram (when the gate voltage is Ov), M is the gate electrode, OX is the gate insulating film, CB is the conduction band, VB is the valence band, and PL is the Fermi level. , Si and GaAs have different electron affinities and forbidden band widths, so band discontinuities ΔEc, ΔE
v occurs. On the conduction band side, ΔEc - difference in electron affinity = 0
．． 06eV, ΔEv - difference in forbidden band width - Δ on the valence band side
[It is said that IC #0.26eV can be produced. Figure 3 (a) shows when the impurity density of the Si thin film 7 on P-type GaAs1i4 is low, and Figure 3 (bl) shows when the Si thin film 7 is doped with p-type impurities at a relatively high density, which is close to the enhancement type. , FIG. 3 (C1 becomes close to the depletion type when n-type impurities are added to the Sin film 7. That is, this M
The threshold voltage vth of OSFET is Si! This shows that it is possible to control the conductivity type and density of the impurity added to the film 7. in fact,
Since there is band discontinuity between Si and GaAs0, a depletion layer or potential barrier is formed at this boundary and the band is bent, so the threshold voltage vth is also a function of the thickness of the Si thin film 7. In order to effectively utilize the fast electron conduction of the GaAs channel region 4, it is desirable that the thickness of the Sin film 7 be as thin as possible, ideally one atomic layer, but substantially between several atomic layers and 100 atomic layers. be. If the thickness of the Si thin film 7 is extremely thin, the energy level of Si will be quantized.
This is not important for the present invention.
（４）実施例４（第４図および第５図）第４図には本発
明の他の断面構造例を、第５図には第４図の構造例の模
式的バンド図を示す。第４図のＭＯＳ Ｆ ＥＴのチャ
ンネル領域４はｐ型Ｇｅで形成している。この構造では
、低抵抗ｐ型Ｓｉ領域１０の内部にｎソース・ドレイン
領域２．３を設け、ソース・ドレイン領域２．３に両端
が接する形でｐ型Ｓｉ領域１０上にＧｅチャンネル９Ｉ
域４を形成し、その上にＳｉ薄膜７．ゲート絶縁膜５．
ゲート電極６が配されている。第５図はこの構造におい
てｐ−３ｉ／ Ｉ） −Ｇｅ／ ｐ−３ｉに対するバン
ド図を示す、バンド不連続はΔ［！ｃ ’＝ ０．１２
ｅＶ、 ΔＥｖ ＃０．３３ｅＶと近位され、Ｇｅチャ
ンネル領域４は電子に対する移動になり、２次電子雲が
生じやすい構造となっている。Ｇｅ中の電子の高移動度
に加えて２次元電子雲の効果でこのＦＥＴは高速性に優
れる。チャンネル領域４としてＧｅの例を述べたが、他
の■族半導体例えば５ｉＧｅ混晶、ＳｉＣなども用いら
れるし、ｍ−ｖ半導体やＩＩ−Ｖｌ半導体にも適用でき
る。(4) Embodiment 4 (FIGS. 4 and 5) FIG. 4 shows another example of the cross-sectional structure of the present invention, and FIG. 5 shows a schematic band diagram of the structure example of FIG. 4. The channel region 4 of the MOS FET shown in FIG. 4 is made of p-type Ge. In this structure, an n source/drain region 2.3 is provided inside a low resistance p-type Si region 10, and a Ge channel 9I is provided on the p-type Si region 10 with both ends in contact with the source/drain region 2.3.
area 4 and a Si thin film 7. Gate insulating film 5.
A gate electrode 6 is arranged. Figure 5 shows the band diagram for p-3i/I)-Ge/p-3i in this structure, where the band discontinuity is Δ[! c'=0.12
eV, ΔEv #0.33 eV, and the Ge channel region 4 has a structure in which electrons are moved and secondary electron clouds are likely to occur. This FET has excellent high-speed performance due to the effect of the two-dimensional electron cloud in addition to the high mobility of electrons in Ge. Although Ge has been described as an example for the channel region 4, other group III semiconductors such as 5iGe mixed crystal, SiC, etc. can also be used, and the present invention can also be applied to m-v semiconductors and II-Vl semiconductors.
（５）実施例５（第６図）第６図（ａ） 〜（ｅ）により、本発明ＭＯ３ＦＥＴの
製造工程例を説明する。第６図ｆａ）は半絶縁性ＧａＡ
ｓ基板１にＣＶ Ｄ ＳｉＯｘ膜２６等をマスクにｐ
型ＧａＡｓチャンネル領域４を選択的に形成した断面で
ある。(5) Example 5 (Fig. 6) An example of the manufacturing process of the MO3FET of the present invention will be explained with reference to Figs. 6(a) to (e). Figure 6fa) shows semi-insulating GaA
s onto the substrate 1 using a CVD SiOx film 26 etc. as a mask.
This is a cross section in which a type GaAs channel region 4 is selectively formed.
第６図世）はさらにＣＶ Ｄ ５ＩＯｔ膜３６等をマ
スクにｎ型ＧａＡｓソース・ドレイン領域２．３を設け
た状態である。第６図（Ｃ１はチャンネル領域４を露出
後、５ｉｆｔ膜２６等をマスクにＳｉ単結晶薄膜７を選
択成長した断面である。この選択成長は公知のＳｉ −
Ｈ−Ｃｌ系の常圧または減圧ＣＶＤが利用できるが、分
子層エピタキシー（ＭＬＥ）の利用が有効である。FIG. 6) shows a state in which n-type GaAs source/drain regions 2.3 are further provided using a CVD 5IOt film 36 or the like as a mask. FIG. 6 (C1 is a cross-section of the Si single crystal thin film 7 selectively grown using the 5ift film 26 etc. as a mask after exposing the channel region 4. This selective growth is performed using the known Si-
Although H-Cl-based atmospheric or low pressure CVD can be used, molecular layer epitaxy (MLE) is effective.
分子線エビ（ＭＢＥ）もを効ではあるが、選択成長が難
しい。第６（ｄ）はＳｉ薄膜７を熱酸化して、ゲート酸
化膜５を形成した状態である。勿論、ゲート酸化膜５と
してＣＶＤ酸化膜やＣＶＤ窒化膜も使用できる。第６図
＋８１はコンタクト開孔後、金属膜によりゲート電極６
．ソース・ドレイン電極１２゜１３を形成して完成した
断面図である。Molecular beam shrimp (MBE) is also effective, but selective growth is difficult. 6(d) shows a state in which the Si thin film 7 is thermally oxidized to form the gate oxide film 5. Of course, a CVD oxide film or a CVD nitride film can also be used as the gate oxide film 5. Figure 6+81 shows the gate electrode 6 formed by the metal film after the contact hole is opened.
．． It is a cross-sectional view of the completed structure after forming source/drain electrodes 12°13.
（６）実施例６（第７図）第７図ｆａｔ 〜ｔｅｌにより、本発明ＭＯ３ＦＥＴの
他の製造工程例を説明する。第６図＋８１はｎ型Ｓｉ５
板１１にｐウェル１０を設は選択Ｓ ｉ ＯｔＷｌ、１
６で分離し、さらにｐ型ＧａＡｓ層４．Ｓｔ薄ｌ！！７
をＭＯＣＶＤ、ＭＢＥ等で全面成長した状態を示す。ｐ
ウェル１０上のＧａＡｓ層、Ｓｉｉ膜７は単結晶となる
が他は多結晶となる。第７図世）はＧａＡｓ層４．Ｓｉ
薄膜７の不嬰部を除去した後、ゲート酸化膜５をＣＶＤ
等で堆積した断面であり、第７図ｔｃ＋はゲート電極６
をＳｉ多結晶や金属またはシリサイドで形成した後、イ
オン注入でｎ型ＧａＡｓソース・ドレイン領域２，３を
設けた状態である。第７図ｆｄ＋はフィールド絶縁膜２
６を堆積した断面である。その後、コンタクト開花を行
ない、各電極、配線を形成して第７図（ｅｌのように完
成する。ｐウェル１０とＧａＡｓ層４の間にバッファ層
としてＧｅＦＩ膜やｍ−ｖ超格子を挿入することもでき
る。(6) Example 6 (FIG. 7) Another manufacturing process example of the MO3FET of the present invention will be explained with reference to FIG. 7. Figure 6 +81 is n-type Si5
Setting the p-well 10 on the plate 11 is selected S i OtWl, 1
6, and a p-type GaAs layer 4. St thin l! ! 7
This shows a state in which the entire surface has been grown by MOCVD, MBE, etc. p
The GaAs layer on the well 10 and the Sii film 7 are single crystal, but the others are polycrystalline. Figure 7) shows the GaAs layer 4. Si
After removing the unwanted portion of the thin film 7, the gate oxide film 5 is deposited by CVD.
FIG. 7 tc+ shows the gate electrode 6.
After forming Si polycrystal, metal, or silicide, n-type GaAs source/drain regions 2 and 3 are provided by ion implantation. Fig. 7 fd+ is field insulating film 2
This is a cross-section of 6 deposited. After that, contact blooming is performed, and each electrode and wiring are formed to complete the process as shown in FIG. You can also do that.
（７）実施例７ （第８図）第８図（ａｌ 〜＋ｄ）により、本発明ＭＯＳ Ｆ Ｅ
Ｔの製造工程例を説明する。第８図ｉｌ＋１はｐ型Ｓｉ
基板１０の表面にｎ型Ｓｉソース・ドレイン領域２．３
を設けた後、５ｉＯ１膜１６をマスクにソース・ドレイ
ン領域２．３の一部とその間の基板１０を露出した状態
を示す。第８図（ｂ）は５ｉｆｔ膜１６をマスクにＧａ
Ａｓ−？）Ｇｅ等のチャンネル領域４をＭＯＣＶ［）や
ＭＬＥ等で選択形成した後、続いて５ｉｙｔ膜７を選択
成長した断面を示す、第８図ｆｃｌはゲート絶縁膜５を
堆積した断面、第８図（ｄｉはゲート電極６などを設け
て完成した断面を示す。(7) Example 7 (Fig. 8) According to Fig. 8 (al to +d), the present invention MOS F E
An example of the manufacturing process of T will be explained. Figure 8 il+1 is p-type Si
N-type Si source/drain regions 2.3 are formed on the surface of the substrate 10.
After forming the 5iO1 film 16, a part of the source/drain region 2.3 and the substrate 10 therebetween are shown exposed. FIG. 8(b) shows Ga using the 5ift film 16 as a mask.
As-? )Ge etc. is selectively formed by MOCV[), MLE, etc., and then a 5iyt film 7 is selectively grown.FIG. (di indicates the completed cross section with the gate electrode 6 etc. provided.
以上のように本発明によれば、ＧａＡｓやＧｅなどの高
移動度材料をチャンネル領域にした絶縁ゲート型ＦＥＴ
がＳｉ技術の応用で実現できる。ＧａＡｓやＧｅを主に
例として述べたが、ＩｎＰなどの他の■−■半導体や５
ｉＧｅなどの他の■族混晶または化合物半導体さらに■
−■半導体にも応用できる。実施例はｎチャンネルを説
明したが、勿論ｐチャンネルにも、またデプレッション
型にも適用される。そのため、本発明はＣＭＯ３にも有
効である。上記のように本発明は、高速・高集積密度・
多機能ＩＣの実現に果たす役割は大きい。As described above, according to the present invention, an insulated gate FET with a channel region made of a high mobility material such as GaAs or Ge
can be realized by applying Si technology. Although GaAs and Ge were mainly used as examples, other ■-■ semiconductors such as InP and 5
Other Group ■ mixed crystals or compound semiconductors such as iGe, and ■
-■Can also be applied to semiconductors. Although the embodiment has been described for n-channel, it is of course applicable to p-channel and depletion type as well. Therefore, the present invention is also effective for CMO3. As mentioned above, the present invention provides high speed, high integration density,
It plays a major role in realizing multifunctional ICs.
第１図は本発明によるＭＯＳＦＥＴの構造断面図、第２
図は本発明によるＭＯＳＦＥＴの他の構造断面図、第３
図（ａ）〜（Ｃ）は本発明ＭＯＳ Ｆ ＥＴのバンド図
、第４図は本発明によるＭＯＳＦＥＴの他の構造断面図
、第５図は第４図のＭＯＳ Ｆ ＥＴのバンド構造側図
、第６図（ａｌ〜＋８１は本発明ＭＯ３ＦＥＴの製造工
程順断面図、第７図（３）〜Ｔｅｌは本発明ＭＯ３ＦＥ
Ｔの他の製造工程順断面図、第８図（ａｌ〜ｆｄｌは本
発明ＭＯ３ＦＥＴの他の製造工程順断面図である。２・・・ソース領域３・・・ドレイン領域４・・・チャンネル領域５・・・ゲート絶縁膜６・・・ゲート電極７・・・Ｓｉ単結晶薄膜１２・・・ソース電極１３・・・ドレイン電極 以 上。−・４−・Ｉ代理人 弁理士 最 上 務（他１名）＼ノ本ｙ；ｅ
ｅＦ１のＭＯ５ＦＥＴハ橋造ｆｆ１ａ図第１図２ ４ ７ ３ １０ｐ−３ｉ本発明のＭＯ５ＦＥＴ／′１ｌｅｌｌ’ｌ溝逍面面図￥
ｙ２図本発明のＭＯＳＦＥＴの榎代的バント′図乎３図本発明ハＭＣ）ＳＦＥＴの構造断面図も４図Ｍ ５ｉ０２Ｓｉ Ｇｅ Ｓｉ本完ＢＩ
ｌｌｌのＭＯ５ＦＥＴハ八ソト°構造列図第５図第６図第７０Figure 1 is a cross-sectional view of the structure of the MOSFET according to the present invention, Figure 2
Figure 3 is another structural cross-sectional view of the MOSFET according to the present invention.
Figures (a) to (C) are band diagrams of the MOSFET of the present invention, Figure 4 is a cross-sectional view of another structure of the MOSFET of the present invention, Figure 5 is a side view of the band structure of the MOSFET of Figure 4, Figure 6 (al~+81 is a cross-sectional view of the MO3FET of the present invention in the order of manufacturing steps, Figure 7 (3)~Tel is a cross-sectional view of the MO3FE of the present invention
FIG. 8 is a cross-sectional view of another manufacturing process of T (al to fdl is a cross-sectional view of another manufacturing process of MO3FET of the present invention. 2... Source region 3... Drain region 4... Channel region 5...Gate insulating film 6...Gate electrode 7...Si single crystal thin film 12...Source electrode 13...Drain electrode That's all. -・4-・I Agent Patent attorney Top management ( 1 other person)\nomotoy;e
MO5FET of eF1 Hasashi structure ff1a Figure 1 2 4 7 3 10p-3i MO5FET of the present invention/'1lell'l Groove side view
Fig. y2 Fig. Enoki's bunt' diagram of the MOSFET of the present invention Fig. 3 Fig. 3 Structural cross-sectional view of the MOSFET of the present invention Fig. 4 M 5i02Si Ge Si book complete BI
Figure 5 Figure 6 Figure 70
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62087370AJPS63252478A (en) | 1987-04-09 | 1987-04-09 | Insulated gate type semiconductor device |
| DE3811821ADE3811821A1 (en) | 1987-04-09 | 1988-04-08 | SEMICONDUCTOR COMPONENT |
| US07/180,359US5036374A (en) | 1987-04-09 | 1988-04-11 | Insulated gate semiconductor device using compound semiconductor at the channel |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62087370AJPS63252478A (en) | 1987-04-09 | 1987-04-09 | Insulated gate type semiconductor device |
| Publication Number | Publication Date |
|---|---|
| JPS63252478Atrue JPS63252478A (en) | 1988-10-19 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62087370APendingJPS63252478A (en) | 1987-04-09 | 1987-04-09 | Insulated gate type semiconductor device |
| Country | Link |
|---|---|
| US (1) | US5036374A (en) |
| JP (1) | JPS63252478A (en) |
| DE (1) | DE3811821A1 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033366A (en)* | 1989-05-15 | 1991-01-09 | Internatl Business Mach Corp <Ibm> | Field-effect transistor and forming method thereof |
| JPH0318062A (en)* | 1989-06-15 | 1991-01-25 | Toshiba Corp | Semiconductor device |
| US5086321A (en)* | 1988-06-15 | 1992-02-04 | International Business Machines Corporation | Unpinned oxide-compound semiconductor structures and method of forming same |
| US5168330A (en)* | 1990-12-03 | 1992-12-01 | Research Triangle Institute | Semiconductor device having a semiconductor substrate interfaced to a dissimilar material by means of a single crystal pseudomorphic interlayer |
| US5241197A (en)* | 1989-01-25 | 1993-08-31 | Hitachi, Ltd. | Transistor provided with strained germanium layer |
| JP2008112774A (en)* | 2006-10-30 | 2008-05-15 | Fuji Electric Device Technology Co Ltd | Insulated gate type semiconductor device using wide band gap semiconductor and manufacturing method thereof |
| WO2010134334A1 (en)* | 2009-05-22 | 2010-11-25 | 住友化学株式会社 | Semiconductor substrate, electronic device, semiconductor substrate manufacturing method, and electronic device manufacturing method |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4987095A (en)* | 1988-06-15 | 1991-01-22 | International Business Machines Corp. | Method of making unpinned oxide-compound semiconductor structures |
| EP0380077A3 (en)* | 1989-01-25 | 1990-09-12 | Hitachi, Ltd. | Transistor provided with strained germanium layer |
| US5272361A (en)* | 1989-06-30 | 1993-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Field effect semiconductor device with immunity to hot carrier effects |
| US5272365A (en)* | 1990-03-29 | 1993-12-21 | Kabushiki Kaisha Toshiba | Silicon transistor device with silicon-germanium electron gas hetero structure channel |
| JPH03280437A (en)* | 1990-03-29 | 1991-12-11 | Toshiba Corp | Semiconductor device and its manufacturing method |
| US5196907A (en)* | 1990-08-20 | 1993-03-23 | Siemens Aktiengesellschaft | Metal insulator semiconductor field effect transistor |
| JP2947654B2 (en)* | 1990-10-31 | 1999-09-13 | キヤノン株式会社 | MIS type transistor |
| US5124762A (en)* | 1990-12-31 | 1992-06-23 | Honeywell Inc. | Gaas heterostructure metal-insulator-semiconductor integrated circuit technology |
| JPH0691249B2 (en)* | 1991-01-10 | 1994-11-14 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Modulation-doped MISFET and manufacturing method thereof |
| US6004137A (en)* | 1991-01-10 | 1999-12-21 | International Business Machines Corporation | Method of making graded channel effect transistor |
| US5268324A (en)* | 1992-05-27 | 1993-12-07 | International Business Machines Corporation | Modified silicon CMOS process having selectively deposited Si/SiGe FETS |
| US5561302A (en)* | 1994-09-26 | 1996-10-01 | Motorola, Inc. | Enhanced mobility MOSFET device and method |
| JP3461274B2 (en)* | 1996-10-16 | 2003-10-27 | 株式会社東芝 | Semiconductor device |
| US5872031A (en)* | 1996-11-27 | 1999-02-16 | The Regents Of The University Of California | Enhancement-depletion logic based on gaas mosfets |
| US6350993B1 (en) | 1999-03-12 | 2002-02-26 | International Business Machines Corporation | High speed composite p-channel Si/SiGe heterostructure for field effect devices |
| US6472695B1 (en) | 1999-06-18 | 2002-10-29 | The Regents Of The University Of California | Increased lateral oxidation rate of aluminum indium arsenide |
| AU2001263211A1 (en)* | 2000-05-26 | 2001-12-11 | Amberwave Systems Corporation | Buried channel strained silicon fet using an ion implanted doped layer |
| US6743680B1 (en)* | 2000-06-22 | 2004-06-01 | Advanced Micro Devices, Inc. | Process for manufacturing transistors having silicon/germanium channel regions |
| US6709935B1 (en) | 2001-03-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Method of locally forming a silicon/geranium channel layer |
| US6861326B2 (en) | 2001-11-21 | 2005-03-01 | Micron Technology, Inc. | Methods of forming semiconductor circuitry |
| KR100625175B1 (en)* | 2004-05-25 | 2006-09-20 | 삼성전자주식회사 | Semiconductor device having channel layer and method of manufacturing same |
| JP5047486B2 (en)* | 2004-10-13 | 2012-10-10 | アイメック | Manufacturing method of semiconductor device |
| EP1936696A1 (en)* | 2006-12-22 | 2008-06-25 | INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) | A field effect transistor device and methods of production thereof |
| EP1936697B1 (en) | 2006-12-22 | 2016-03-09 | Imec | A field effect transistor device, and methods of production thereof |
| US8329541B2 (en)* | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
| US8610172B2 (en) | 2011-12-15 | 2013-12-17 | International Business Machines Corporation | FETs with hybrid channel materials |
| US9093264B2 (en)* | 2012-04-20 | 2015-07-28 | Applied Materials, Inc. | Methods and apparatus for forming silicon passivation layers on germanium or III-V semiconductor devices |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58188165A (en)* | 1982-04-28 | 1983-11-02 | Nec Corp | Semiconductor device |
| JPS59119869A (en)* | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | Semiconductor device |
| JPS59232426A (en)* | 1983-06-16 | 1984-12-27 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS60211946A (en)* | 1984-04-06 | 1985-10-24 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| JPH0783107B2 (en)* | 1984-04-19 | 1995-09-06 | 日本電気株式会社 | Field effect transistor |
| JPS60239062A (en)* | 1984-05-11 | 1985-11-27 | Seiko Epson Corp | Inp semiconductor device |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5086321A (en)* | 1988-06-15 | 1992-02-04 | International Business Machines Corporation | Unpinned oxide-compound semiconductor structures and method of forming same |
| US5241197A (en)* | 1989-01-25 | 1993-08-31 | Hitachi, Ltd. | Transistor provided with strained germanium layer |
| JPH033366A (en)* | 1989-05-15 | 1991-01-09 | Internatl Business Mach Corp <Ibm> | Field-effect transistor and forming method thereof |
| JPH0318062A (en)* | 1989-06-15 | 1991-01-25 | Toshiba Corp | Semiconductor device |
| US5168330A (en)* | 1990-12-03 | 1992-12-01 | Research Triangle Institute | Semiconductor device having a semiconductor substrate interfaced to a dissimilar material by means of a single crystal pseudomorphic interlayer |
| JP2008112774A (en)* | 2006-10-30 | 2008-05-15 | Fuji Electric Device Technology Co Ltd | Insulated gate type semiconductor device using wide band gap semiconductor and manufacturing method thereof |
| WO2010134334A1 (en)* | 2009-05-22 | 2010-11-25 | 住友化学株式会社 | Semiconductor substrate, electronic device, semiconductor substrate manufacturing method, and electronic device manufacturing method |
| JP2011009718A (en)* | 2009-05-22 | 2011-01-13 | Sumitomo Chemical Co Ltd | Semiconductor substrate, electronic device, method of manufacturing semiconductor substrate, and method of manufacturing electronic device |
| US8890213B2 (en) | 2009-05-22 | 2014-11-18 | Sumitomo Chemical Company, Limited | Semiconductor wafer, electronic device, a method of producing semiconductor wafer, and method of producing electronic device |
| Publication number | Publication date |
|---|---|
| DE3811821A1 (en) | 1988-10-27 |
| US5036374A (en) | 1991-07-30 |
| Publication | Publication Date | Title |
|---|---|---|
| JPS63252478A (en) | Insulated gate type semiconductor device | |
| US7435987B1 (en) | Forming a type I heterostructure in a group IV semiconductor | |
| US9991172B2 (en) | Forming arsenide-based complementary logic on a single substrate | |
| US20110180867A1 (en) | Metal transistor device | |
| JPH0371776B2 (en) | ||
| JPH07101739B2 (en) | Semiconductor device | |
| US7301180B2 (en) | Structure and method for a high-speed semiconductor device having a Ge channel layer | |
| JPH03775B2 (en) | ||
| EP0080714A2 (en) | Hetero-junction semiconductor device | |
| JPH02266569A (en) | field effect transistor | |
| JPS60134481A (en) | semiconductor equipment | |
| JPH03187269A (en) | Semiconductor device | |
| US8575595B2 (en) | P-type semiconductor devices | |
| JPS61147577A (en) | Complementary semiconductor device | |
| JP2710309B2 (en) | Heterojunction field effect transistor | |
| JPH01119065A (en) | Group 3-5 compound semiconductor field effect transistor | |
| JP2655594B2 (en) | Integrated semiconductor device | |
| JPS60136380A (en) | semiconductor equipment | |
| JPH02196436A (en) | semiconductor equipment | |
| JPH03159135A (en) | Semiconductor device and its manufacturing method | |
| JP3020578B2 (en) | Semiconductor device | |
| JPH01183164A (en) | High electron mobility field effect transistor | |
| JPS63219176A (en) | Method of manufacturing field effect transistor | |
| JP2680821B2 (en) | Heterostructure field effect transistor | |
| JPS609174A (en) | semiconductor equipment |