【発明の詳細な説明】〔産業上の利用分野〕この発明は半導体チップが実装される改良形の回路基板
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to an improved circuit board on which a semiconductor chip is mounted.
第３図は従来の回路基板を示す断面図であり、図におい
て、（１）および（２）は半導体チップで、シリコン等
からなる半導体基板（１ａ）および（２ａ）の−主面に
所定の処理工程を酢で機能パターン部（ｌｂ）および（
２ｂ）が形成されているものである。（３１ハスバツタ
法によるアルミニウム膜等からなる電極で、上記機能パ
ターン部（ｉｂ）（２ｂ）の所定位置に配設されている
。（４１はセラミック等からなる板状の絶縁基板で、そ
の主面に銅、金等からなる所定形状の配線パターン（図
示せず）が形成されている。（６）は上記配線パターン
と同材料からなる基板電極で、上記配線パターンに含ま
れて上記半導体チップｆｉ＋ １２１の近傍周辺に配設
されている。（６）は絶電性の樹脂等からなる接着材で
、上記基板電極（５ｍ ） （５ｂ ）の内側のほぼ中
央部に位置して上記絶縁基板（４）に被着し、上記半導
体チップｉｌ＋ ＋２１を上記絶縁基板（４）と平行の
状態で、その半導体基板（１ａＸ２ｍ）部で接着させて
いる。（７）は配線部材（Ａ）で、この場合、金等から
なるワイヤで、上記半導体チップ［１１＋２１の電極（
３ａ）（３ｂ）と絶縁基板（４）の基板電極（５ａ）（
５ｂ）とを電気的に接続させている。（８）は樹脂等か
らなる封止材で、上記半導体チップｆｌＬｆ２＋ 。FIG. 3 is a cross-sectional view showing a conventional circuit board. In the figure, (1) and (2) are semiconductor chips, which are made of silicon or the like and have a predetermined shape on the main surface of the semiconductor substrates (1a) and (2a). The processing step is to remove the functional pattern part (lb) and (
2b) is formed. (31 is an electrode made of an aluminum film or the like made by the Hasbatta method, and is arranged at a predetermined position of the functional pattern part (ib) (2b). (41 is a plate-shaped insulating substrate made of ceramic or the like, and its main surface A wiring pattern (not shown) of a predetermined shape made of copper, gold, etc. is formed on the substrate.(6) is a substrate electrode made of the same material as the wiring pattern, and is included in the wiring pattern and is connected to the semiconductor chip fi+. 121. (6) is an adhesive made of electrically insulating resin, etc., and is located approximately at the center inside the substrate electrode (5m) (5b). 4), and the semiconductor chip il+ +21 is bonded to the insulating substrate (4) at the semiconductor substrate (1a x 2m) portion in parallel with the insulating substrate (4).(7) is the wiring member (A); In this case, wires made of gold or the like can be used to connect the electrodes of the semiconductor chip [11+21 (
3a) (3b) and the substrate electrode (5a) (of the insulating substrate (4))
5b) are electrically connected. (8) is a sealing material made of resin or the like for the semiconductor chip flLf2+.
接着材（６ｍ ）（６ｂ） 、ワイヤ（７ａ）（７ｂ）
および基板電極（５ａ）（５ｂ）を含む領域を被覆させ
ている。Adhesive material (6m) (6b), wire (7a) (7b)
and a region including the substrate electrodes (5a) and (5b) is covered.
ところで、上記のように構成された回路基板は、大路次
のように組立てられる。By the way, the circuit board configured as described above is assembled as follows.
すなわち、まず絶縁基板（４）の表面で、基板電極（５
ｍ）（５ｂ）より内側のほぼ中央部に適度の粘度をもつ
接着材（６ｍ）（６ｂ）が塗布され、この接着材（６ａ
） （６ｂ）に半導体チップ＋１１ ＋２１の半導体
基板（ｌａ Ｘ２１）面を押圧させて半導体チップ＋１
１＋２１を絶縁基板（４）に平行の状態で接着・支持さ
せる。次に、ワイヤポンディングにより半導体チップｆ
ｉ＋ ＋２１の電極（（３ａ）（３ｂ）と絶縁基板（４
）の各対応する基板電極（５ａ） （５ｂ）とをワイヤ
（７＾Ｘ７ｂ）で接続させる。その後、上記半導体チッ
プ１ｌｌ（２＋、接着材（６ａ）（６ｂ） 。That is, first, the substrate electrode (5) is placed on the surface of the insulating substrate (4).
Adhesive material (6m) (6b) with a moderate viscosity is applied approximately in the center inside of (5b), and this adhesive material (6a
) (6b) presses the semiconductor substrate (la X21) surface of semiconductor chip +11
1+21 is adhered and supported in parallel to the insulating substrate (4). Next, the semiconductor chip f is bonded by wire bonding.
i+ +21 electrodes ((3a) (3b) and insulating substrate (4
) are connected to the corresponding substrate electrodes (5a) (5b) by wires (7^X7b). After that, the semiconductor chip 111 (2+, adhesive material (6a) (6b)) is applied.
ワイヤ（７ａ）（７ｂ）および基板電極（５ａ）（５ｂ
）を含む領域を封止材（８ａ）（８ｂ）の樹脂で被覆・
保護させて、上記回路基板とされる。Wires (7a) (7b) and substrate electrodes (5a) (5b)
) is coated with the resin of the sealing material (8a) (8b).
The circuit board is then protected.
また、第４図は従来の他の回路基板を示す断面図であり
、図において、（４）および（８）は第４図に示したも
のと全く同一のものである。（９）および（１０）は半
導体チップで、第３図に示した半導体チップｆｌｌ（２
）と同じく、その機能パターン部（９ｂ） （１０ｂ）
を対向させて上記絶縁基板（４）と平行の状態で絶縁基
板（４）の両面に配設されている。（ｌｌａ）（ｌｌｂ
）はそれぞれ上記機能パターン部（９ｂ） （１ｏｂ）
に含まれる電極で、スパッタ法によるアルミニウム膜等
が形成されたものの上面に、さらに真空蒸着法によるク
ロム、銅、錫等からなる三層膜等が形成されている。（
１２ａ）（１２ｂ）はそれぞれ配線部材（Ｂ）で、この
場合鉛、錫のハンダ等で形成されたバンブ電極である。Further, FIG. 4 is a sectional view showing another conventional circuit board, and in the figure, (4) and (8) are exactly the same as those shown in FIG. 4. (9) and (10) are semiconductor chips shown in FIG.
), its functional pattern part (9b) (10b)
are disposed on both sides of the insulating substrate (4), facing each other and parallel to the insulating substrate (4). (lla) (llb
) are the above functional pattern parts (9b) (1ob), respectively.
In the electrode included in the above, a three-layer film or the like made of chromium, copper, tin, etc. is further formed by a vacuum evaporation method on the upper surface of the electrode on which an aluminum film or the like is formed by a sputtering method. (
12a and 12b are wiring members (B), which in this case are bump electrodes made of lead, tin solder, or the like.
（１３ａ）（１３ｂ）はそれぞれ上記半導体チップｆ９
） Ｑｏ＋のバンブ電極（１２ｇ）（１２ｂ）の当接部
に位置するバンプ対向電極で、上記絶縁基板（４）の表
面に所定形状に形成された銅、金等からなる配線パター
ン（図示せず）に配設されて、この配線パターンと同材
料で形成されている。（１４ａ）（１４ｂ）はそれぞれ
配線部材（Ｃ）で、この場合ハンダペースト等からなる
等電性の接着材で、上記バンブ電極（１２ｓ）（１２ｂ
）とバンプ対向電極（１３ａ Ｘ１３ｂ）とを電気的に
接続させている。これら半導体チップ＋９）ｔｌｏｌ
、バンブ電極（１２ｍ）（１２ｂ） ＝バンプ対向電極
（１３ａ）（１３ｂ）および導電性の接着材（１４ｍ）
（１４ｂ）を含む領域は封止材（８ｇ）（８ｂ）で被覆
されている。(13a) and (13b) are the semiconductor chip f9, respectively.
) A bump counter electrode located at the contact portion of the bump electrodes (12g) (12b) of Qo+, and a wiring pattern (not shown) made of copper, gold, etc. formed in a predetermined shape on the surface of the insulating substrate (4). ) and is made of the same material as this wiring pattern. (14a) and (14b) are wiring members (C), in which case they are made of isoelectric adhesive such as solder paste, and the bump electrodes (12s) and (12b) are made of isoelectric adhesive such as solder paste.
) and the bump counter electrode (13a X13b) are electrically connected. These semiconductor chips +9) tlol
, bump electrodes (12m) (12b) = bump counter electrodes (13a) (13b) and conductive adhesive (14m)
The region including (14b) is covered with sealing material (8g) (8b).
ところで、上記のように構成された回路基板は大路次の
ように組立てられる。By the way, the circuit board configured as described above is assembled as follows.
丁なわち、まず、スクリーン印刷等の技術によって、絶
縁基板（４）のバンプ対向電極（１３ｓ）（１３ｂ）に
導電性の接着材（１４ａ）（１４ｂ）が塗布される。次
に、半導体チップ（９１（１０）が、そのバンブ電極（
１２ｍ）（１２ｂ）と上記絶縁基板（４）のバンプ対向
電極（１３ａ）（１３ｂ）とが当接する位置で、離間さ
れた状態にて位置合せされた後、導電性の接着材（１４
ｍ） （１４ｂ）に押圧されて絶縁基板（４）に接着・
支持されるとともに、電気的に接続される。その後、半
導体チップ［９１Ｆ＋０１ 、バンブ電極（１２ａ）（
１２ｂ） 、導電性の接着材（１４ａ Ｘ１４ｂ）およ
びバンプ対向電極（１３ａ ） （１３ｂ）を含むｗ４
域を封止材（８ａ ） （８ｂ）の樹脂で被覆・保護さ
せて、上記回路基板とされる。That is, first, conductive adhesives (14a) (14b) are applied to the bump counter electrodes (13s) (13b) of the insulating substrate (4) by a technique such as screen printing. Next, the semiconductor chip (91 (10)) is connected to its bump electrode (
12m) (12b) and the bump counter electrodes (13a) (13b) of the insulating substrate (4) are aligned in a spaced state, and then a conductive adhesive
m) Pressed by (14b) and adhered to the insulating substrate (4).
It is supported and electrically connected. After that, the semiconductor chip [91F+01, bump electrode (12a)
12b), w4 including conductive adhesive (14a x 14b) and bump counter electrode (13a) (13b)
The area is covered and protected with the resin of the sealing material (8a) (8b) to form the above-mentioned circuit board.
従来の回路基板は以上のように構成されており、絶縁基
板の各面には単チップの実装構造であるため、高密度、
高集積あるいは多機能の回路基板を得ようとすると、絶
縁基板を平面的にしか使用せさるを得なく、従って、回
路基板のサイズが大きくなってしまうという問題を有す
るものであった。Conventional circuit boards are constructed as described above, and each side of the insulating board has a single chip mounted structure, allowing for high-density,
In order to obtain a highly integrated or multi-functional circuit board, it is necessary to use an insulating substrate only in a two-dimensional manner, resulting in a problem that the size of the circuit board becomes large.
１だ、接層材を介して半導体チップが絶縁基板に接層さ
れているため、接層材の厚みの＃ｒかに、機能に直接寄
与しない半導体チップの当接領域の絶縁基板の厚みを有
するものであるため、必要以上に１厚い回路基板となっ
てしまうという問題点をも有するものであった。1. Since the semiconductor chip is bonded to the insulating substrate through the contact layer material, the thickness of the insulating substrate in the contact area of the semiconductor chip that does not directly contribute to the function is determined by #r of the thickness of the contact layer material. However, this also has the problem that the circuit board becomes thicker than necessary.
との発明は上記のような問題点を解決するためになされ
たもので、小型・薄型で、高密度化できる回路基板を得
ることを目的とする。The invention was made to solve the above-mentioned problems, and its purpose is to obtain a circuit board that is small, thin, and capable of high density.
この発明に係る回路基板は、第１の半導体チップと、こ
の第１の半導体チップと平行に配設される第２Ｊｊｌの
半導体チップと、これら両名間に介在してこれら半導体
基板を互いに対面させて接着させる接着材とから階層状
の半導体チップを構成させ、この階Ｉｍ状の半導体チッ
プを絶縁基板に配設させたものである。The circuit board according to the present invention includes a first semiconductor chip, a second semiconductor chip disposed parallel to the first semiconductor chip, and a circuit board interposed between the two semiconductor chips so as to face each other. A layered semiconductor chip is constructed from an adhesive material that is bonded to the substrate, and this layered Im-shaped semiconductor chip is disposed on an insulating substrate.
この発明においては、ｗ、１の半導体チップと第２の半
導体チップとが、接着材にて接合されて一つの階層状の
半導体チップを構成し、この階層状の半導体チップが絶
縁基板に配設されて、鳩密反夾装化に機能するものであ
る。In this invention, the semiconductor chip w, 1 and the second semiconductor chip are bonded with an adhesive to form one layered semiconductor chip, and this layered semiconductor chip is disposed on an insulating substrate. It is designed to function as an anti-contamination method.
第１図はこの発明の一実施例の回路基板を示す断面図で
あり、図において、（３）〜（８）および（１１１〜（
１４１は従来の回路基板と全く同一のものである。＋１
５）はシリコン等からなる半導体基板（１５ａ）の−主
面に所定の処理工程を経て機能パターン部（１５ｂ）が
形成された第１の半導体チップで、機能パターン部（１
５ｂ）の所定位置には電極（ｌｌａ）が配設されており
、この電極（ｌ１ｍ）には、スパッタ法によるアルミニ
ウム膜等が形成されたものの上面に、真空蒸着法による
クロム、銅、錫等からなる三層膜等が形成され、さらに
その上面には鉛、錫のハンダ等からなるバンブ電極（１
２ａ）となる配線部材（Ｂ）が形成されている。（＋６
１およびαηは第２の半導体チップおよび第３の半導体
チップで、ともに上記第１の半導体チップ（１５）と同
じく半導体基板（１６ａ）（１７ａ）の−主面に機能パ
ターン部（１６ｂ）（１７ｂ）が形成されたものであり
、この機能パターン部（１６ｂ）（ｉ７ｂ）の所定位置
にはスパッタ法によるアルミニウム膜等からなる電極（
３ａ）（３ｃ）が配設されている。この第２の半導体チ
ップαφと第３の半導体チップ（１７１とは互いに離間
されて配置され、上記第１の半導体チップαｎに対し、
それぞれ平行にかつ離間された状態にて、他主面同志が
これら両名間に介在される接着材（６ａ）により接着さ
れて、二層状を呈する第１の階層状の半導体チップを構
成させている。そして、第１の半導体チップ（１５１の
電極（ｌ１ｍ）は、配線部材（Ｂ） （Ｃ）で、この場
合バンプ電極（１２ｍ）と導電性の接着材（１４ａ）と
で、絶縁基板（４）の一方の面上にあって、銅、金等か
らなる配線パターン（図示せず）に含まれ上記バンブ電
極（１２１）との当接位置に配設されるバンプ対向電極
（１３ｍ）に電気的に接続され、かつ接着・支持されて
いる。また、第２の半導体チップ（１６）およびｗＪ３
の半導体チップ（１７１の各電極（３ａ ）（３ｃ）は
、配線部材（Ａ）で、この場合ワイヤ（７ａ）（７ｃ）
で、上記絶縁基板（４）の同じ面上にあって、上記配線
パターンとは別に形成された上記と同じ材料からなる配
線パターン（図示せず）に含まれ、上記ｗｃ１の半導体
チップ０５１の近傍周辺に配設された基板電極（５ｍ）
（５ｃ）に電気的に接続されている。さらに、これら第
１．第２および第３の半導体チップ０５）αφおよびａ
カ、接着材（６ａ） 、バンブ電極（１２ｍ） 、導電
性の接着材（１４ｇ）。FIG. 1 is a sectional view showing a circuit board according to an embodiment of the present invention. In the figure, (3) to (8) and (111 to (111) to (
141 is exactly the same as a conventional circuit board. +1
5) is a first semiconductor chip in which a functional pattern portion (15b) is formed on the main surface of a semiconductor substrate (15a) made of silicon or the like through a predetermined processing step;
An electrode (lla) is arranged at a predetermined position of 5b), and this electrode (l1m) is coated with chromium, copper, tin, etc. by vacuum evaporation on the top surface of which an aluminum film or the like is formed by sputtering. A three-layer film, etc. consisting of
A wiring member (B) serving as 2a) is formed. (+6
1 and αη are a second semiconductor chip and a third semiconductor chip, both of which have functional pattern portions (16b) (17b) on the main surfaces of semiconductor substrates (16a) (17a), similar to the first semiconductor chip (15). ) are formed, and electrodes (
3a) (3c) are provided. This second semiconductor chip αφ and the third semiconductor chip (171) are arranged spaced apart from each other, and with respect to the first semiconductor chip αn,
The other principal surfaces are bonded to each other with an adhesive (6a) interposed between the two in parallel and spaced apart from each other, thereby forming a first layered semiconductor chip having a two-layered structure. There is. The electrode (l1m) of the first semiconductor chip (151) is a wiring member (B) (C), in this case, a bump electrode (12m) and a conductive adhesive (14a) are connected to an insulating substrate (4). The bump counter electrode (13m), which is included in a wiring pattern (not shown) made of copper, gold, etc., and is placed in contact with the bump electrode (121), is electrically connected to the bump counter electrode (13m). The second semiconductor chip (16) and the wJ3
Each electrode (3a) (3c) of the semiconductor chip (171) is a wiring member (A), in this case wires (7a) (7c)
, which is on the same surface of the insulating substrate (4), is included in a wiring pattern (not shown) made of the same material as the above, formed separately from the wiring pattern, and is near the semiconductor chip 051 of the wc1. Substrate electrodes placed around the area (5m)
(5c) is electrically connected. Furthermore, these first. Second and third semiconductor chips 05) αφ and a
F, adhesive (6a), bump electrode (12m), conductive adhesive (14g).
基板電極（５ｍ）（５ｃ）およびワイヤ（７ａ）（７ｃ
）を含む領Ｖｉ、ハ封止材（８ａ）で被覆されている。Substrate electrode (5m) (5c) and wire (7a) (7c
) are covered with a sealing material (8a).
一方、上記絶縁基板（４１の他方の面には、上記第１の
階層状の半解体チップとほぼ対称をなす位置に、上記−
と同じく接着材（６ｂ）を介して第１１−を構成する第
４の半導体チップ０８１と第２層を構成する第５の半導
体チップＱ９１とで形成されるａＪ２の階層状の半解体
チップが配設さ孔、上記と同じく各電極間が接続されて
、封止材（８ｂ）で被覆されている。On the other hand, on the other surface of the insulating substrate (41), the -
Similarly, layered half-disassembled chips of aJ2 formed of the fourth semiconductor chip 081 constituting the 11th layer and the fifth semiconductor chip Q91 constituting the second layer are arranged via the adhesive (6b). The provided holes are connected between the respective electrodes and covered with a sealing material (8b) in the same manner as described above.
ところで、上記のように構成された回路基板は、大路次
のように組立てられる。すなわち、まず、第１層となる
第１の半導体チップ（１５）の半解体基板（１５ｍ）面
にほぼ均一に絶縁性の接着材（６ａ）が塗布され、この
接着材（６ａ）に、第２層となる第２の半導体チップ（
１６）および第３の半導体チップ（１７１を離間させて
、これら半導体基板（１６ａ）（１７ａ）を第１の半導
体チップ（１５）の半導体基板（１５ａ）と平行を保持
させながら押圧して接着・支持させて、第１の階層状の
半導体チップを形成させる。同じく第４の半導体チップ
（ｌネに塗布された絶縁性の接着材（６ｂ）に第５の半
導体チップ！１９）を接着・支持させて、第２の階層状
の半導体チップを形成させる。By the way, the circuit board configured as described above is assembled as follows. That is, first, an insulating adhesive (6a) is applied almost uniformly to the surface of the semi-disassembled substrate (15m) of the first semiconductor chip (15) serving as the first layer, and a second layer is applied to the adhesive (6a). A second semiconductor chip with two layers (
16) and the third semiconductor chip (171) are separated and pressed while keeping these semiconductor substrates (16a) and (17a) parallel to the semiconductor substrate (15a) of the first semiconductor chip (15) for bonding. Support to form a first layered semiconductor chip.Similarly, a fourth semiconductor chip (a fifth semiconductor chip! 19) is bonded and supported to the insulating adhesive (6b) applied to the first layer. In this way, a second layered semiconductor chip is formed.
次に、絶、橡基板（４）の両面上のバンプ対向成極（１
３ａ）（１３ｂ）にスクリーン印刷等の技術により導電
性の接着材（１＋ａ）（１４ｂ）がほぼ均一に塗布され
、上記第１の階層状の半導体チップと第２の階層状の半
導体チップの各バンブ電極（１２ｍ）と（１２ｂ）は、
バンプ対向電極（１３畠）（１３ｂ）に轟接する位置で
、離間された状態にて位置合わせ後、押圧されて接続・
接着される。つづいて、上記各階層状の半導体チップの
電極（３ｍ）（３ｂ）（３ｃ）と絶縁基板（４）の各基
板電極（５ａ）（５ｂ）（５ｃ）とはワイヤポンディン
グにより接続される。その後、これら第１およびｇ２の
階層状の半導体チップ、バンブ電極（１２ｍ）（１２ｂ
） 。Next, bump opposing polarization (1
Conductive adhesive (1+a) (14b) is applied almost uniformly to 3a) (13b) using a technique such as screen printing, thereby forming each of the first layered semiconductor chip and the second layered semiconductor chip. The bump electrodes (12m) and (12b) are
After aligning in a spaced state at the position where the bump counter electrode (13 hatake) (13b) contacts, it is pressed and connected.
Glued. Subsequently, the electrodes (3m), (3b), and (3c) of the layered semiconductor chips are connected to the substrate electrodes (5a, 5b, and 5c) of the insulating substrate (4) by wire bonding. After that, these first and g2 hierarchical semiconductor chips, bump electrodes (12m) (12b
).
導電性の接着材（１４ａ）（１４ｂ） 、ワイヤ（７ａ
）（７ｂ）（７Ｃ）および基板電極（５ａ）（５ｂ）（
５ｃ）を含む領域は、封止材（８ｇ ） （８ｂ ）の
樹脂で被覆・保護させて、上記回路基板とされる。Conductive adhesive (14a) (14b), wire (7a
) (7b) (7C) and substrate electrodes (5a) (5b) (
The region including 5c) is covered and protected with a resin of a sealing material (8g) (8b) to form the above-mentioned circuit board.
このように階層状の半導体チップを絶縁基板に実装させ
ることによって、平面サイズは変えることなく厚みをわ
ずか大きくするのみで、従来の約２倍の実装密度が得ら
れるものとなる。By mounting hierarchical semiconductor chips on an insulating substrate in this manner, it is possible to obtain a packaging density approximately twice that of the conventional method by only slightly increasing the thickness without changing the planar size.
第２図はこの発明の他の実施例の回路基板を示す断面図
であり、図において、（３）〜（８）は上記第１図に示
したものと全く同一のものである。嶽および（２１＋は
第１層を構成する第６の半導体チップおよび第２層を構
成する第７の半導体チップで、ともに上記例と同じく半
導体基板（２０ａ）（２１ａ）の−主面に、電極（５ａ
）（５ｂ）を配設させた機能パターン部（２０ｂ）（２
１ｂ）が形成されているものである。これら第６の半導
体チップ（社）と第７の半導体チップ（２１）は、絶縁
性基板（４）に形成された開孔部−に接着して介在され
る接着材（６）に、これら半導体基板（２０ａ）（２１
ｍ）を互いに平行に対面して他主面同志が接着されて、
第３の階層状の半導体チップを形成させている。そして
、この階層状の半導体チップの電極（３ｍ）（３ｂ）と
絶縁基板（４）の各基板電極（５ｍ）（５ｂ）とはワイ
ヤ（７ｍ）（７ｂ）で電気的に接続され、これら階層状
の半導体チップ、ワイヤ（７ｍ）（７ｂ）および基板電
極（５ｍ）（５ｂ）を含む領域は、封止材（８ａ）（８
ｂ）で被覆されている。FIG. 2 is a sectional view showing a circuit board according to another embodiment of the present invention, and in the figure, (3) to (8) are exactly the same as those shown in FIG. 1 above. Dake and (21+) are the sixth semiconductor chip constituting the first layer and the seventh semiconductor chip constituting the second layer, both of which have electrodes on the negative main surfaces of the semiconductor substrates (20a) and (21a), as in the above example. (5a
) (5b) is arranged in the functional pattern section (20b) (2
1b) is formed. The sixth semiconductor chip (21) and the seventh semiconductor chip (21) are bonded to an adhesive (6) interposed in an opening formed in an insulating substrate (4). Substrate (20a) (21
m) are bonded to each other with other principal surfaces facing each other in parallel,
A third layered semiconductor chip is formed. The electrodes (3m) (3b) of this layered semiconductor chip and the substrate electrodes (5m) (5b) of the insulating substrate (4) are electrically connected by wires (7m) (7b), and these layered The area including the shaped semiconductor chip, wires (7m) (7b) and substrate electrodes (5m) (5b) is covered with sealing material (8a) (8
b) coated with
ところで、このように構成される回路基板の大略組立て
は、まず、開孔が設けられた絶縁基板（４）の開孔部２
ａに絶縁性の接着材（６）を付着させ、次に、第６の半
導体チップ■および第７の半導体チップ伐１１の各半導
体基板（２０ｇ）（２１ｍ）を互いに対面させ、平行を
保持しつつ接着材（６）に押圧して接着・支持させる。By the way, the general assembly of the circuit board configured as described above is as follows: First, the opening part 2 of the insulating board (4) provided with the opening is
An insulating adhesive (6) is attached to a, and then the semiconductor substrates (20 g) (21 m) of the sixth semiconductor chip (1) and the seventh semiconductor chip (11) are made to face each other and kept parallel. While pressing the adhesive material (6), it is bonded and supported.
つづいて、ワイヤポンディングにより電極（３ａ）（３
ｂ）と基板電極（５ｍ ） （５ｂ）とをワイヤ（７ａ
）（７ｂ）で接続させ、その後、これら第３の階層状の
半導体チップ、接着材（６）ｌワイヤ（７ａ）（７ｂ）
および基板電極（５ｍ） （５ｂ）を含む領域は封止材
（６）の樹脂で被覆・保護させて、上記回路基板とされ
る。Next, electrodes (3a) (3
b) and the substrate electrode (5m) (5b) with a wire (7a
) (7b), and then these third layered semiconductor chips, adhesive (6) l wires (7a) (7b)
The region including the substrate electrodes (5m) (5b) is covered and protected with a resin of a sealing material (6) to form the above-mentioned circuit board.
このように構成される回路基板は、絶縁基板（４）を開
孔させ、その開孔部□□□に階層状の半導体チップを位
置させて、その中間に介在される接着材（６）により支
持させたものとなされているので、絶縁穴状の厚みが削
減され、しかも接着材（６）の厚みは半ノリ体チップ１
層分が確保されれば良く、非常に薄をに形成させること
ができるものとなる。The circuit board constructed in this way is made by opening holes in the insulating substrate (4), positioning layered semiconductor chips in the openings, and using an adhesive (6) interposed between the holes. Since it is supported, the thickness of the insulating hole is reduced, and the thickness of the adhesive (6) is smaller than that of the semi-glued chip 1.
It is sufficient to ensure enough layers, and it is possible to form a very thin film.
なお、上記実施例の説明において、接着材は絶縁性の材
料で形成させたものであったが、半導体基板が接地され
る半纏体チップのものにおいては、導電性の材料で形成
させたものとすれば良く、このとき接着材と絶縁基板上
の所定配線パターンとを上記例と別の配線部材で接続さ
せれば良い。In the description of the above embodiments, the adhesive material was made of an insulating material, but in the case of a semi-integrated chip in which the semiconductor substrate is grounded, it may be made of a conductive material. At this time, the adhesive and the predetermined wiring pattern on the insulating substrate may be connected using a wiring member different from that in the above example.
また、第１図に示すものにおいて、第１の階層状の半導
体チップと第２の階層状の半導体チップとは、絶縁基板
の両面にほぼ対称の状態に各１個配設させたが、これに
限定されず、１個以上であれば良く、また半導体チップ
のサイズ等に応じてこれらを互いにずらして配設させた
ものであっても良く、さらに、必要に応じて一方の面の
みに形成させたものであっても良い。In addition, in the device shown in FIG. 1, the first layered semiconductor chip and the second layered semiconductor chip are arranged approximately symmetrically on both sides of the insulating substrate. It is not limited to , but it is sufficient to have one or more, or they may be arranged offset from each other depending on the size of the semiconductor chip, etc. Furthermore, if necessary, they may be formed only on one side. It may be something that has been done.
さらに、上記実施例において、階ｒ−状の半導体チップ
が２個又は３個の半導体チップで構成される場合を示し
たが、これに限定されず必要に応じて２個以上の半導体
チップとさせれば良い。このとき各半導体チップが同種
のものの構成でも、多種のものの構成でも良く、特に後
者の場合、多橿の半導体チップの組合せが自由だでき、
用途に応じた多種の機能を有するものを容易に実現でき
、しかも高度なａ造波術によらず従来の製造ＭＬ術を利
用して得ることができるため、低価格化がはかられるも
のとなる。Furthermore, in the above embodiment, the case where the r-shaped semiconductor chip is composed of two or three semiconductor chips is shown, but the present invention is not limited to this, and two or more semiconductor chips may be used as necessary. That's fine. At this time, each semiconductor chip may have a configuration of the same type or a configuration of various types, and in the latter case in particular, a wide variety of semiconductor chips can be freely combined.
Products with a wide variety of functions depending on the application can be easily realized, and they can be obtained using conventional manufacturing ML techniques rather than advanced a-wave-making techniques, resulting in lower costs. Become.
なお、上記において、階層状の半導体チップは二層状を
呈するものを示したが、これに限定されず、上記実施例
に示す技術によれば、二層以上からなる階層状の半導体
チップを構成させることもでき、上記と同様の効果を奏
するものである。In addition, although the hierarchical semiconductor chip has been shown to have a two-layer structure in the above, it is not limited to this, and according to the technology shown in the above embodiment, a hierarchical semiconductor chip consisting of two or more layers can be configured. It is also possible to achieve the same effect as above.
以上説明したように、この発明によれば、互いに平行に
配設された半導体チップが、その他主面同志を接着材を
介して接合した階層状の半導体チップとし、この階層状
の半導体チップを絶縁基板に配設させた回路基板とした
ので、小型・薄型で高密度実装ができ、装置等の省スペ
ース化がはかられるという効果がある。As explained above, according to the present invention, semiconductor chips arranged in parallel to each other are formed into a layered semiconductor chip whose main surfaces are bonded to each other through an adhesive, and the layered semiconductor chips are insulated. Since the circuit board is disposed on the board, it is small, thin, and can be mounted with high density, which has the effect of saving space for devices, etc.
第１図はこの発明の一害施例による回路基板を示す断面
図、第２図はこの発明の他の実施例による回路基板を示
す断面図、第３図は従来の回路基板を示す断面図、第４
図は従来の他の回路基板を示す断面図である。図において、（３）は電極、（４）は絶縁基板、（５）
は基板電極、（６）は接着材、（７）は配線部材（Ａ）
、ｆ８１は封止材、Ｑ２１は配線部材（Ｂ）、０３）は
バンプ対向電極、（１４）は配線部材（Ｃ）、０５１
Ｑ６１ ［１，（ｉａ） （ｌｆｌ）四シｌ）は半導体
チップ、（ロ）は開孔部である。なお、各図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a sectional view showing a circuit board according to a harmful embodiment of the present invention, FIG. 2 is a sectional view showing a circuit board according to another embodiment of the invention, and FIG. 3 is a sectional view showing a conventional circuit board. , 4th
The figure is a sectional view showing another conventional circuit board. In the figure, (3) is an electrode, (4) is an insulating substrate, and (5)
is the substrate electrode, (6) is the adhesive, and (7) is the wiring member (A).
, f81 is the sealing material, Q21 is the wiring member (B), 03) is the bump counter electrode, (14) is the wiring member (C), 051
Q61 [1, (ia) (lfl)4sil) is a semiconductor chip, and (b) is an opening. In each figure, the same reference numerals indicate the same or equivalent parts.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62046007AJPS63211663A (en) | 1987-02-26 | 1987-02-26 | circuit board |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62046007AJPS63211663A (en) | 1987-02-26 | 1987-02-26 | circuit board |
| Publication Number | Publication Date |
|---|---|
| JPS63211663Atrue JPS63211663A (en) | 1988-09-02 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62046007APendingJPS63211663A (en) | 1987-02-26 | 1987-02-26 | circuit board |
| Country | Link |
|---|---|
| JP (1) | JPS63211663A (en) |
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