【図面の簡単な説明】[Brief explanation of the drawing] 第１図はこの考案の一実施例の接続図、第２図
はこの考案の他の実施例の接続図、第３図はこの
考案の更に他の実施例の接続図、第４図はこの考
案の更に他の実施例の説明に用いる各部波形図、
第５図は従来のＭＯＳインバータの一例の接続図
、第６図は従来のＭＯＳインバータの他の例の接
続図、第７図は従来のＭＯＳインバータを２段接
続した構成の接続図、第８図は第７図の構成の説
明に用いる各部波形図である。 １，２，１１，１２：ＭＯＳトランジスタ、３
，１３：入力端子、５，１５：電圧リミツト用の
ＭＯＳトランジスタ、６，１６：出力端子。 Fig. 1 is a connection diagram of one embodiment of this invention, Fig. 2 is a connection diagram of another embodiment of this invention, Fig. 3 is a connection diagram of yet another embodiment of this invention, and Fig. 4 is a connection diagram of another embodiment of this invention. Waveform diagrams of various parts used to explain still other embodiments of the invention,
Fig. 5 is a connection diagram of an example of a conventional MOS inverter, Fig. 6 is a connection diagram of another example of a conventional MOS inverter, Fig. 7 is a connection diagram of a configuration in which two stages of conventional MOS inverters are connected, and Fig. 8 is a connection diagram of an example of a conventional MOS inverter. The figure is a waveform diagram of each part used to explain the configuration of FIG. 7. 1, 2, 11, 12: MOS transistor, 3
, 13: input terminal, 5, 15: MOS transistor for voltage limit, 6, 16: output terminal.