【発明の詳細な説明】 本発明は半導体装置に関するもので、配線基板
を厚さ方向にのみ導電性を有する異方導電性ゴム
状シートを介して半導体チツプに圧接させ、以つ
てワイヤボンデング等を行なうことなしに半導体
チツプの所要部を電気的に外部に導出し得るよう
にした装置に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, in which a wiring board is pressed into contact with a semiconductor chip through an anisotropically conductive rubber sheet having conductivity only in the thickness direction, and wire bonding, etc. The present invention relates to a device that can electrically lead out a required part of a semiconductor chip to the outside without performing any process.
第１図に示すように、一般に半導体チツプ１に
おける所要部を取付基体２に設けた電極取出部３
等を介して電気的に外部に導出する場合、半導体
チツプ１上にボンデングパツド４を設け、このボ
ンデングパツド４に細いワイヤ５（25μφ位）の
一端部をボンデングさせ、さらにこのワイヤ５の
他端部を電極取出部３にボンデングさせるという
方式がとられている。 As shown in FIG. 1, an electrode lead-out portion 3 is generally provided in a mounting base 2 at a required portion of a semiconductor chip 1.
When electrically leading out to the outside via a wire, etc., a bonding pad 4 is provided on the semiconductor chip 1, one end of a thin wire 5 (about 25 μφ) is bonded to this bonding pad 4, and the other end of this wire 5 is bonded to the bonding pad 4. A method is adopted in which the electrode is bonded to the electrode extraction portion 3.
ところでこのボンデングパツド４は、ボンデン
グしたワイヤ５の先端部が偏平に変形した状態で
接合されるために、通常、ワイヤ５径の４倍位の
辺をもつ４角形状に形成させるものである。即ち
面積にしてワイヤ５の断面積の20倍程度の大きさ
を必要とする。そしてこのボンデングパツド４の
所要個数は、ICやLSI等になると第２図にも示す
ようにかなりの数量を必要とする。このため半導
体チツプ１全体の所要面積が大きくなつてしまう
という難点があつた。 Since the bonding pad 4 is bonded with the tip of the bonded wire 5 deformed into a flat shape, it is usually formed into a rectangular shape with sides about four times the diameter of the wire 5. That is, it requires an area approximately 20 times larger than the cross-sectional area of the wire 5. As shown in FIG. 2, the required number of bonding pads 4 is quite large for ICs, LSIs, etc. Therefore, there was a problem in that the required area of the entire semiconductor chip 1 became large.
また半導体チツプ１上におけるこのボンデング
パツド４，４…の配設位置は、ワイヤ５の交叉を
避けるためや、ボンデング作業を容易ならしめる
ため等の理由から半導体チツプ１の周辺部に配列
するものである。しかるにボンデングパツド４，
４…を半導体チツプ１の周辺部に配列すると、機
能素子等所要の電気的導出部が半導体チツプ１の
中心部近くにあるときは、内部配線が長くなつて
しまうという難点が生ずるので、このために前記
と同様に半導体チツプ１全体の所要面積が大きく
なつてしまうとともに、素子の高速化を図る上に
おいても不向きであるという難点があつた。 Furthermore, the bonding pads 4, 4, . . . on the semiconductor chip 1 are arranged around the periphery of the semiconductor chip 1 in order to avoid crossing of the wires 5 and to facilitate the bonding work. . However, Bondengpad 4,
4... on the periphery of the semiconductor chip 1, if the necessary electrical lead-out parts such as functional elements are located near the center of the semiconductor chip 1, there will be a problem that the internal wiring will become long. Similarly to the above, there are disadvantages in that the area required for the entire semiconductor chip 1 becomes large, and it is also unsuitable for increasing the speed of the device.
さらにワイヤボンデング方式の場合は、前記し
たように25μφ程度の細線を用いるために振動や
機械的ストレスに対する強度が劣り、またボンデ
ング部のはがれも故障原因を招くために、何れに
しても信頼性の点で万全とは言えないものであつ
た。 Furthermore, in the case of the wire bonding method, as mentioned above, since a thin wire of about 25μφ is used, the strength against vibration and mechanical stress is inferior, and peeling of the bonded part can also cause failure, so in any case, reliability is low. In this respect, it could not be said to be perfect.
ここにおいて本発明はワイヤレス接続方式を採
用することにより上記した技術的課題を解決し得
るようにした半導体装置を提供しようとしたもの
である。 Here, the present invention attempts to provide a semiconductor device that can solve the above technical problems by employing a wireless connection method.
以下本発明をIC（集積回路）を適用した図の
実施例に基づいて具体的に説明する。 The present invention will be specifically explained below based on the embodiments shown in the drawings to which an IC (integrated circuit) is applied.
第３図、および第４図Ａ，Ｂはそれぞれ本発明
に適用する半導体チツプおよび異方導電性ゴム状
シートの一例を示すもので、まず半導体チツプＳ
については、半導体基板上に、よく知られている
ように当該半導体基板の表面保護と、次に述べる
内部配線層および半導体基板間の絶縁のための第
１層絶縁膜１１を形成し、この第１層絶縁膜１１
を適宜にパターン化して素子（図示せず）を作り
込んだ後、この第１層絶縁膜１１上に前記の素子
間等を接続するためのAl膜等で形成した内部配
線層（図示せず）を形成させる。次いでこの上に
さらに低温気相成長法等により内部配線層を異方
導電性ゴム状シートＥの圧接、および腐蝕等から
保護するための第２層絶縁膜１２を被覆させ、こ
の第２層絶縁膜１２における所望の任意位置を穿
設し、この穿設部に接続パツド１３，１３…を装
填ける。 FIG. 3 and FIGS. 4A and 4B respectively show an example of a semiconductor chip and an anisotropically conductive rubber sheet applied to the present invention.
As is well known, a first layer insulating film 11 is formed on the semiconductor substrate for protecting the surface of the semiconductor substrate and for insulating between the internal wiring layer and the semiconductor substrate, which will be described next. Single layer insulation film 11
After suitably patterning to form elements (not shown), an internal wiring layer (not shown) formed of an Al film or the like for connecting the above-mentioned elements etc. is formed on the first layer insulating film 11. ) to form. Next, a second layer insulating film 12 for protecting the internal wiring layer from pressure bonding with an anisotropically conductive rubber sheet E and corrosion etc. is further coated on this layer by a low temperature vapor phase growth method or the like. A desired arbitrary position in the membrane 12 is drilled, and the connecting pads 13, 13, . . . are loaded into the drilled portion.
この接続パツド１３，１３…は図示のように半
導体チツプＳの周辺部に配列させる必要はなく任
意の位置を選ぶことができ、また内部配線層と同
じくAl膜等で形成させ、さらにその面積は100μ
□程度以下で従来のボンデングパツド４よりも小
面積に形成させる。 These connection pads 13, 13... do not need to be arranged around the periphery of the semiconductor chip S as shown in the figure, and can be selected at any position.Also, they are formed of an Al film or the like like the internal wiring layer, and their area is 100μ
The bonding pad 4 can be formed in a smaller area than the conventional bonding pad 4 by approximately □ or less.
次に第４図Ａ，Ｂの異方導電性ゴム状シートＥ
について説明すると、このものは厚さ方向に導電
性を有し、且つ横方向（ひろがり方向）には絶縁
性を有するもので、この基体は一例としてシリコ
ンゴム等のゴム状絶縁材１４で形成され、厚さ方
向に導電性を有せしめるに当つては、第４図Ｂの
拡大断面図にも示すようにこのゴム状絶縁材１４
中に厚さ方向に導電領域１５，１５…を多数個形
成させたものである。この導電領域１５は金属粒
子、又はグラフアイト繊維、金属細線等をゴム状
絶縁材１４中に埋め込むことにより形成する。 Next, the anisotropically conductive rubber sheet E in Figure 4 A and B
To explain this, this device has conductivity in the thickness direction and insulation in the lateral direction (spreading direction), and the base is made of a rubber-like insulating material 14 such as silicone rubber, for example. In order to provide conductivity in the thickness direction, this rubber-like insulating material 14 is used as shown in the enlarged cross-sectional view of FIG.
A large number of conductive regions 15, 15, . . . are formed in the thickness direction. The conductive region 15 is formed by embedding metal particles, graphite fibers, thin metal wires, etc. in the rubber-like insulating material 14.
この異方導電性ゴム状シートＥにおける横方向
の絶縁性は、一例として100μ間隔程度の近接点
間において109Ω程度以上という高い値を有す
る。またシートの厚さについては一例として100
μｍ〜２mm位の範囲で適宜に選ぶことができる。
面積については本発明においては、半導体チツプ
Ｓと同程度の大きさに切断した方形状のものとす
る。 The lateral insulation of this anisotropic conductive rubber sheet E has, for example, a high value of about 109 Ω or more between adjacent points spaced about 100 μm apart. Also, as an example, the thickness of the sheet is 100
It can be appropriately selected within the range of μm to 2 mm.
In terms of area, in the present invention, it is a rectangular shape cut to approximately the same size as the semiconductor chip S.
さて本発明においては上記した半導体チツプ
Ｓ、および異方導電性ゴム状シートＥ等を次のよ
うに積層させる。 Now, in the present invention, the above-mentioned semiconductor chip S, anisotropically conductive rubber sheet E, etc. are laminated as follows.
即ち第５図に示すように、まず半導体チツプＳ
を取付基体１６上に配置する。 That is, as shown in FIG.
are placed on the mounting base 16.
取付基体１６としては、装置として放熱を重視
する場合にはAl、Cu等の金属板を使用し、一
方、絶縁性を重視する場合においては、セラミツ
クまたは樹脂材等からなる絶縁性基板を使用す
る。 As the mounting base 16, a metal plate such as Al or Cu is used when heat dissipation is important for the device, while an insulating board made of ceramic or resin material is used when insulation is important. .
次いで半導体チツプＳ上に異方導電性ゴム状シ
ートＥを載置し、さらにこの異方導電性ゴム状シ
ートＥ上に配線基板１７を積層させる。 Next, an anisotropically conductive rubber sheet E is placed on the semiconductor chip S, and a wiring board 17 is further laminated on this anisotropically conductive rubber sheet E.
配線基板１７は、プリント基板またはセラミツ
ク基板により形成したもので、半導体チツプＳに
おける接続パツド１３，１３…に対応した位置に
接続電極１８，１８…を備えさせ、この接続電極
１８，１８…の配設部以外の図における下面側は
絶縁層１９とさせたものである。符号２０は外部
導出用の導体配線層である。 The wiring board 17 is formed of a printed circuit board or a ceramic board, and is provided with connection electrodes 18, 18, . . . at positions corresponding to the connection pads 13, 13, . An insulating layer 19 is provided on the lower surface side in the figure other than the installation portion. Reference numeral 20 is a conductor wiring layer for leading to the outside.
而して接続電極１８，１８…配設側を半導体チ
ツプＳに対向させた上で、図における左右両端部
近傍における配線基板１７および取付基体１６間
を加圧状態とさせた上で固定し上記の積層状態を
保持させる。加圧状態とさせることにより、異方
導電性ゴム状シートＥの弾力によつて、この異方
導電性ゴム状シートＥにおける導電領域１５の両
端部が接続パツド１３および接続電極１８にそれ
ぞれ圧接され、この接続パツド１３および接続電
極１８間が電気的に接続されるのである。 Then, with the connection electrodes 18, 18... facing the semiconductor chip S, pressure is applied between the wiring board 17 and the mounting base 16 in the vicinity of both left and right ends in the figure, and then fixed. maintain the laminated state. By applying pressure, the elasticity of the anisotropically conductive rubber sheet E brings both ends of the conductive region 15 of the anisotropically conductive rubber sheet E into pressure contact with the connection pad 13 and the connection electrode 18, respectively. , this connection pad 13 and connection electrode 18 are electrically connected.
そしてこの接続状態は上記した異方導電性ゴム
状シートＥの弾力によつて位置ずれを生ずること
なく保持される。 This connected state is maintained without any displacement due to the elasticity of the anisotropically conductive rubber sheet E mentioned above.
次に上記した加圧保持機構の各態様を第６〜８
図を参照してさらに詳細に説明する。 Next, each aspect of the above-mentioned pressure holding mechanism is explained in the sixth to eighth sections.
This will be explained in more detail with reference to the drawings.
なお以下の図において前記第３〜５図と共通す
る部材については前記と同一の符号を附すものと
する。 In the following figures, members common to those in FIGS. 3 to 5 are given the same reference numerals as above.
まず第６図Ａ，Ｂの事例は、配線基板１７と取
付基体１６とを加圧状態で樹脂接着剤２１により
接着させたものである。加圧状態で接着させるに
当つては、樹脂接着剤２１が非硬化状態にあると
きに、配線基板１７および取付基体１６間を錘あ
るいはクリツプ（図示せず）により加圧させ、こ
の加圧状態を樹脂接着剤２１が硬化するまで続行
させる。 First, in the case shown in FIGS. 6A and 6B, the wiring board 17 and the mounting base 16 are bonded together using a resin adhesive 21 under pressure. When adhering under pressure, pressure is applied between the wiring board 17 and the mounting base 16 using a weight or a clip (not shown) while the resin adhesive 21 is in an uncured state. This is continued until the resin adhesive 21 is cured.
因みに第６図の事例は配線基板１７と取付基体
１６との間に複数個の半導体チツプＳ，Ｓ…を保
持させ、この半導体チツプＳ，Ｓ…間を配線基板
１７における導体配線層２０等により相互接続さ
せて混成集積化させたものである。また図示のよ
うに取付基体１６における半導体チツプＳ，Ｓ…
の配設位置に凹嵌部を設け、この凹嵌部に各半導
体チツプＳ，Ｓ…を嵌設すれば組立容易性ととも
に、保持状態を一層強固とさせ得るという効果を
有する。 Incidentally, in the case shown in FIG. 6, a plurality of semiconductor chips S, S, etc. are held between the wiring board 17 and the mounting base 16, and the semiconductor chips S, S, etc. are connected by a conductive wiring layer 20, etc. on the wiring board 17. They are interconnected and integrated into a hybrid structure. In addition, as shown in the figure, semiconductor chips S, S... on the mounting base 16 are shown.
By providing a recessed fitting portion at the arrangement position and fitting the respective semiconductor chips S, S, etc. into the recessed fitting portion, it is possible to facilitate assembly and further strengthen the holding state.
次に、上記の第６図Ａ，Ｂの事例においては配
線基板１７と取付基体１６との間を樹脂接着剤２
１によつて接着させたが、樹脂接着剤２１に代え
てろう材を使用してもよい。ろう材としては一例
としてPb／Sn系の低温はんだを適用する。 Next, in the cases shown in FIGS. 6A and 6B above, a resin adhesive 2 is applied between the wiring board 17 and the mounting base 16.
1, but a brazing filler metal may be used instead of the resin adhesive 21. As an example, Pb/Sn-based low-temperature solder is used as the brazing material.
上記のろう材による場合にも、加圧状態で接合
させるに当つては、ろう材が溶融状態に達するま
で、錘あるいはクリツプ等により配線基板１７お
よび取付基体１６間を加圧させ、固着接合後に上
記の錘を取り除く。 Even in the case of using the above-mentioned brazing filler metal, when bonding is performed under pressure, pressure is applied between the wiring board 17 and the mounting base 16 using a weight or a clip until the brazing filler metal reaches a molten state. Remove the weight above.
因みにろう材で接合させる場合にあつては、取
付基体１６における少なくとも接合部は金属材で
構成させる。 Incidentally, in the case of joining using a brazing filler metal, at least the joining portion of the mounting base 16 is made of a metal material.
次いで第７図の事例は配線基板１７および取付
基体１６間をねじ２２およびナツト２３により締
めつけ固定したものである。符号２４はゴムリン
グである。上記のようにねじ２２およびナツト２
３により固定保持させたときは、半導体チツプＳ
等が故障を生じた場合において取換が容易になる
という効果を有する。 Next, in the example shown in FIG. 7, the wiring board 17 and the mounting base 16 are tightened and fixed with screws 22 and nuts 23. Reference numeral 24 is a rubber ring. Screw 22 and nut 2 as above
When held fixed by 3, the semiconductor chip S
This has the effect of facilitating replacement in the event of a failure.
次に第８図Ａ，Ｂの事例は、配線基板１７の背
面部に蓋状金属板２５を配設し、加圧保持機構と
して、この蓋状金属板２５と取付基体１６とを加
圧状態で抵抗溶接２６により接合させたものであ
る。 Next, in the case shown in FIGS. 8A and 8B, a lid-shaped metal plate 25 is arranged on the back side of the wiring board 17, and the lid-shaped metal plate 25 and the mounting base 16 are kept under pressure as a pressure holding mechanism. They are joined by resistance welding 26.
加圧状態で接合させるに当つては前記した各事
例と同様の手段を講ずればよい。 For joining under pressure, the same means as in each case described above may be used.
また上記の事例においては、取付基体１６側も
蓋状金属板２５と同様に皿状に形成させ、この両
者１６，２５を対向させた上でその周辺部（フラ
ンジ部）一体を抵抗溶接させて蓋状金属板２５と
取付基体１６とで半導体チツプＳ等の外囲器を形
成させてもよい。なおこの場合においては取付基
体１６側も金属板で構成させる。 In the above case, the mounting base 16 side is also formed into a dish shape in the same way as the lid-shaped metal plate 25, and after the two sides 16 and 25 are opposed to each other, the peripheral part (flange part) is resistance welded together. The lid-shaped metal plate 25 and the mounting base 16 may form an envelope for the semiconductor chip S or the like. In this case, the mounting base 16 side is also made of a metal plate.
符号２７は外部接続端子で、この外部接続端子
２７は外囲器内において配線基板１７における導
体配線層２０に適宜に接続する。 Reference numeral 27 denotes an external connection terminal, and this external connection terminal 27 is appropriately connected to the conductor wiring layer 20 on the wiring board 17 within the envelope.
本発明は上記した何れの事例においても、配線
基板１７および取付基体１６間は加圧状態で固定
保持されるので、異方導電性ゴム状シートＥにお
ける導電領域１５の両端部は、この異方導電性ゴ
ム状シートＥの弾力により半導体チツプＳにおけ
る接続パツド１３と、配線基板１７における接続
電極１８とにそれぞれ強固に接合し保持される。 In any of the above-described cases, the present invention fixes and holds the wiring board 17 and the mounting base 16 under pressure, so that both ends of the conductive region 15 in the anisotropically conductive rubber sheet E Due to the elasticity of the conductive rubber sheet E, it is firmly bonded and held to the connection pads 13 on the semiconductor chip S and the connection electrodes 18 on the wiring board 17, respectively.
したがつて半導体チツプＳにおける機能素子等
の所要部は、接続パツド１３、異方導電性ゴム状
シートＥにおける導電領域１５、接続電極１８、
および導体配線層２０、さらには外部接続端子２
７を順次介して外部に電気的に導出される。 Therefore, the required parts of the semiconductor chip S, such as functional elements, are the connection pad 13, the conductive region 15 in the anisotropic conductive rubber sheet E, the connection electrode 18,
and conductor wiring layer 20, and further external connection terminal 2
7 and then electrically led out to the outside.
而して上記の電気経路を通じて半導体チツプＳ
に所要の電気的動作をさせることができる。そし
てこの動作時において半導体チツプＳ等に故障が
生じたときは、配線基板１７および取付基体１６
間の接着部乃至は接合部をはがすか、またはねじ
部材を取り外して、当該故障した半導体チツプＳ
等を取り換えることができる。 Through the above electrical path, the semiconductor chip S
can perform the required electrical operation. If a failure occurs in the semiconductor chip S etc. during this operation, the wiring board 17 and the mounting base 16
Remove the adhesive or joint between them or remove the screw member to remove the defective semiconductor chip S.
etc. can be replaced.
以上詳述したように本発明によれば、配線基板
を厚さ方向にのみ導電性を有する異方導電性ゴム
状シートを介して第２層絶縁膜により内部配線層
を保護した半導体チツプに圧接させ、且つこの配
線基板には半導体チツプにおける接続パツドに対
応した位置に接続電極を備えさせたから、半導体
チツプにおける機能素子等の所要部をボンデング
レス乃至はワイヤレスで且つ内部配線層を損傷さ
せることなく電気的に外部に導出することがで
き、また接続パツドは従来例のように半導体チツ
プの周辺部に配列することなく任意の位置に配置
することができる。 As detailed above, according to the present invention, a wiring board is pressure-bonded to a semiconductor chip whose internal wiring layer is protected by a second layer insulating film via an anisotropically conductive rubber sheet that is conductive only in the thickness direction. Moreover, since this wiring board is provided with connection electrodes at positions corresponding to the connection pads on the semiconductor chip, necessary parts such as functional elements on the semiconductor chip can be electrically connected without bonding or wirelessly and without damaging internal wiring layers. Furthermore, the connection pads can be placed at arbitrary positions without having to be arranged around the periphery of the semiconductor chip as in the conventional example.
したがつて接続パツドは、従来のボンデングパ
ツドよりも小面積に形成させることができ、また
半導体チツプにおける内部配線層の長さも最小限
に押えることができるから、半導体チツプ面積を
小形化し得ると同時に、装置の高速化機能性を図
り得、さらには信頼性を向上させることができる
という極めて優れた効果を発揮する。 Therefore, the connection pad can be formed in a smaller area than a conventional bonding pad, and the length of the internal wiring layer in the semiconductor chip can also be minimized, so the area of the semiconductor chip can be reduced, and at the same time, This has the extremely excellent effect of increasing the speed and functionality of the device and further improving its reliability.
また半導体チツプ等に故障が生じた場合に容易
取換性を有せしめ得るという効果も発揮する。 Further, in the event that a semiconductor chip or the like fails, it can be easily replaced.
さらに、半導体チツプは配線基板および取付基
体間に挾持させるだけでよいから、混成集積化も
容易になし得るという優れた効果も発揮する。 Furthermore, since the semiconductor chip only needs to be sandwiched between the wiring board and the mounting base, an excellent effect is exhibited in that hybrid integration can be easily achieved.
第１図は従来例を示す側面図、第２図は同上に
おける半導体チツプを示す斜視図、第３図は本発
明に適用する半導体チツプの一例を示す斜視図、
第４図Ａは本発明に適用する異方導電性ゴム状シ
ートの一例を一部切欠いて示す斜視図、第４図Ｂ
は同上シートにおける導電領域部を示す部分拡大
縦断面図、第５図は本発明の一実施例たる半導体
装置の側断面図、第６図Ａは同上装置に適用する
加圧保持機構の一例を示す側断面図、第６図Ｂは
同上機構における接着部の部分拡大断面図、第７
図は第５図に適用する加圧保持機構の他の例を示
す部分拡大断面図、第８図Ａは第５図に適用する
加圧保持機構の他の例を示す側断面図、第８図Ｂ
は同上機構における接合部の部分拡大断面図であ
る。 １１……第１層絶縁膜、１２……第２層絶縁
膜、１３……接続パツド、１４……ゴム状絶縁
材、１５……導電領域、１６……取付基体、１７
……配線基板、１８……接続電極、１９……絶縁
層、２０……導体配線層、２１……樹脂接着
剤、、２２……ねじ、２３……ナツト、２５……
蓋状金属板、２６……抵抗溶接、２７……外部接
続端子、Ｅ……異方導電性ゴム状シート、Ｓ……
半導体チツプ。 FIG. 1 is a side view showing a conventional example, FIG. 2 is a perspective view showing the semiconductor chip in the above, and FIG. 3 is a perspective view showing an example of the semiconductor chip applied to the present invention.
FIG. 4A is a partially cutaway perspective view of an example of an anisotropic conductive rubber sheet applied to the present invention, and FIG. 4B
5 is a partially enlarged vertical cross-sectional view showing a conductive region in the same sheet, FIG. 5 is a side sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 6A is an example of a pressure holding mechanism applied to the same device. FIG. 6B is a partially enlarged sectional view of the adhesive part in the same mechanism as above, and FIG.
8A is a partially enlarged sectional view showing another example of the pressure holding mechanism applied to FIG. 5; FIG. 8A is a side sectional view showing another example of the pressure holding mechanism applied to FIG. 5; Diagram B
FIG. 2 is a partially enlarged sectional view of a joint in the same mechanism as above. DESCRIPTION OF SYMBOLS 11... First layer insulating film, 12... Second layer insulating film, 13... Connection pad, 14... Rubber-like insulating material, 15... Conductive region, 16... Mounting base, 17
... Wiring board, 18 ... Connection electrode, 19 ... Insulating layer, 20 ... Conductor wiring layer, 21 ... Resin adhesive, 22 ... Screw, 23 ... Nut, 25 ...
Lid-shaped metal plate, 26...Resistance welding, 27...External connection terminal, E...Anisotropic conductive rubber sheet, S...
semiconductor chip.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15798579AJPS5681944A (en) | 1979-12-07 | 1979-12-07 | Semiconductor device |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15798579AJPS5681944A (en) | 1979-12-07 | 1979-12-07 | Semiconductor device |
| Publication Number | Publication Date |
|---|---|
| JPS5681944A JPS5681944A (en) | 1981-07-04 |
| JPS6119108B2true JPS6119108B2 (en) | 1986-05-15 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15798579AGrantedJPS5681944A (en) | 1979-12-07 | 1979-12-07 | Semiconductor device |
| Country | Link |
|---|---|
| JP (1) | JPS5681944A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2358022A1 (en)* | 1976-07-07 | 1978-02-03 | Minnesota Mining & Mfg | IMPROVEMENTS TO CONNECTORS FOR INTEGRATED CIRCUITS |
| Publication number | Publication date |
|---|---|
| JPS5681944A (en) | 1981-07-04 |
| Publication | Publication Date | Title |
|---|---|---|
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