【発明の詳細な説明】本発明はＩＣ，ＬＳＩ等の半導体装置の製造法に係るも
のであり、特に小型高密度実装法に有用な方法を提供す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing semiconductor devices such as ICs and LSIs, and particularly provides a method useful for compact high-density packaging.
従来の構成とその問題点最近システムの小型化、高速度化の要求に伴ない、半導
体装置の実装法も、ワイヤーボンディング法以外にフリ
ップチップ法、あるいはＴａｐθＡｕｔｏｍａｔｅｄ
Ｂｏｎｄｉｎｇ法（いわゆるＴＡＢ法〕等、その目的に
応じて種々の実装法が提案され実用に供されている。Conventional configurations and their problems Recently, with the demand for smaller systems and higher speeds, semiconductor device mounting methods have changed to the wire bonding method, the flip-chip method, or the Tapθ Automated method.
Various mounting methods have been proposed and put into practical use depending on the purpose, such as the bonding method (so-called TAB method).
従来のＴＡＢ実装法は第１図のように半導体素子基板１
上に形成した電極パッド２に−ムＵあるいは半田等から
なるポンディング用バンプ３を形成し一同バンプ３に対
しテープキャリア４のインナーリード６ｆｉ−同時にボ
ンディングするいわゆるギヤングボンディング法によシ
構成するものである。In the conventional TAB mounting method, as shown in Fig. 1, a semiconductor element substrate 1 is
Bonding bumps 3 made of aluminum or solder are formed on the electrode pads 2 formed above, and the inner leads 6fi of the tape carrier 4 are simultaneously bonded to the bumps 3 using the so-called gigantic bonding method. It is something.
なお図中のバンプ３と電極パッド２間に形成されている
層は、バリア金属層６および接合金属層７と称されるも
のである。Note that the layers formed between the bump 3 and the electrode pad 2 in the figure are called a barrier metal layer 6 and a bonding metal layer 7.
このＴＡＢ実装法の欠点は予め半導体基板１上の全チッ
プの電極パッド２上にバンブ３を形成するため、半導体
基板１内の不良チップに対してもバンブ３が形成され一
半導体素子製造プロセスにおけるチップ歩留りの悪い半
導体基板１の場合、バンブ３のコストの上昇、特にムロ
バンプを用いた場合にはそれが顕著になる欠点を有して
いた。The disadvantage of this TAB mounting method is that since the bumps 3 are formed on the electrode pads 2 of all chips on the semiconductor substrate 1 in advance, the bumps 3 are also formed on defective chips on the semiconductor substrate 1. In the case of the semiconductor substrate 1 having a poor chip yield, the cost of the bumps 3 increases, which becomes particularly noticeable when using uneven bumps.
上記問題の解消法として、バンブ３を半導体基８ｉ１上
に形成せず、テープキャリア４のインナーリード６部に
形成し、半導体基板１上の良品チップに対してのみボン
ディングを施こす方法の提案がなされている。As a solution to the above problem, a method has been proposed in which the bumps 3 are not formed on the semiconductor substrate 8i1, but are formed on the inner leads 6 of the tape carrier 4, and bonding is performed only to good chips on the semiconductor substrate 1. being done.
この方法は前述の問題点を解決するのに有用なボンディ
ング法であるが−バンブ３にムｕ’６用いる場合、一般
的に使用されているテープキャリア４のインナーリード
６のｓｎメッキ層（基材はＯｕ ）との共晶が容易に起
るため、半導体基板１上の電極パッド２であるムｌ膜層
とのボンディング条件の選定が難かしい等の欠点があっ
た。This method is a useful bonding method for solving the above-mentioned problems. Since eutectic formation with the material (Ou) easily occurs, there are drawbacks such as difficulty in selecting conditions for bonding with the mulch film layer, which is the electrode pad 2 on the semiconductor substrate 1.
発明の目的本発明は前述のような従来のＴＡＢ法での欠点を解決し
、ＴＡＢ法の利点を活用し、迅速容易に小型高密度の半
導体装を可能とする半導体装置の製造法を提供すること
を目的とするものである。Purpose of the Invention The present invention solves the drawbacks of the conventional TAB method as described above, utilizes the advantages of the TAB method, and provides a method for manufacturing a semiconductor device that enables quick and easy production of small, high-density semiconductor devices. The purpose is to
発明の構成この目的を達成するために本発明は、半導体素子チップ
の電極パッドと相対位置関係を合致させた別置の電極形
成用透明基板上に、電極バンブを形成し、その電極形成
用透明基板を上記半導体基板上の所定位置に載置加圧し
−しかる後電極形成用透明基板後方より熱線ビームを照
射することにより電極バンプを半導体基板上の電極パッ
ドに接合転写させるに当り、電極形成用透明基板を短冊
形状とすることにより半導体基板上の半導体素子チップ
に対して選択的に電極バンプを転写形成することを特徴
とするものである。Structure of the Invention In order to achieve this object, the present invention forms electrode bumps on a separate transparent substrate for electrode formation whose relative position matches the electrode pads of a semiconductor element chip, and The substrate is placed at a predetermined position on the semiconductor substrate and pressed, and then a heat beam is irradiated from behind the transparent substrate for electrode formation to bond and transfer the electrode bumps to the electrode pads on the semiconductor substrate. The present invention is characterized in that electrode bumps are selectively transferred and formed onto semiconductor element chips on a semiconductor substrate by forming the transparent substrate into a rectangular shape.
実施例の説明以下、具体的な説明を実施例によって詳述する。Description of examplesHereinafter, a detailed explanation will be given based on examples.
実施例１第２図は所望の特性を附与した半導体素子チップ８を有
する半導体基板（ウェハー）９の平面略図であシー同図
中の斜線部は所望の特性を有さないいわゆる不良チップ
８′を示したものである。Embodiment 1 FIG. 2 is a schematic plan view of a semiconductor substrate (wafer) 9 having a semiconductor element chip 8 imparted with desired characteristics. The shaded area in the figure is a so-called defective chip 8 that does not have the desired characteristics. ′ is shown.
また、第３図は第２図の局部拡大図であシ、それぞれの
半導体素子チップ８は機能領域１ｏの外周域に電極パッ
ド１１群を備え、その断面構造Ａ −ム′部は第４図（
寸法尺度は第３図と異なる）のようにＳｉ基板１２０表
面の絶縁膜１３上にムｌ電極バッド１１を形成し、その
電極パッド１１の中央開孔部１４以外を表面保護膜１６
で覆った構造を有した通常の半導体素子と同一構成の半
導体基ｆｉＩ９である。3 is a partially enlarged view of FIG. 2, and each semiconductor element chip 8 is provided with a group of electrode pads 11 in the outer peripheral area of the functional area 1o, and its cross-sectional structure A-m' is shown in FIG. (
A thin electrode pad 11 is formed on the insulating film 13 on the surface of the Si substrate 120 as shown in FIG.
This is a semiconductor substrate fiI9 having the same structure as a normal semiconductor element having a structure covered with.
一方、上記半導体素子チップ８の電極パッド１１群上に
設けるバンブの形成は、第６図、第６図に示す通りであ
る。On the other hand, the bumps provided on the group of electrode pads 11 of the semiconductor element chip 8 are formed as shown in FIGS.
すなわち、平滑なガラス基板１６の主面１７全面に酸化
スズと酸化インジウムからなる透明導電電極１８（いわ
ゆるＩＴＯ膜等と称されるもの以下本説明ではＩＴＯ膜
と呼称する）を形成した後その表面全面を８１０２膜、
ホトレジスト膜等の透明あるいは半透明絶縁膜１９で被
覆した後、写真食刻法によシ前述の半導体素子チップ８
のパッド部１１に対応した寸法位置に開孔部２０を形成
する。すなわち、ガラス基板１６の主面１７を前述の半
導体基板９の表面上に重ねて位置合せを行えば主面１７
上の開孔部２０と半導体基板９の表面部位に形成した電
極パッド１１が合致する構成−換言すればホトプロセス
におけるホトマスクと素材基板の関係と同一の構成とす
る。That is, after forming a transparent conductive electrode 18 made of tin oxide and indium oxide (hereinafter referred to as an ITO film in this description) made of tin oxide and indium oxide on the entire main surface 17 of a smooth glass substrate 16, the surface thereof is 8102 film on the entire surface,
After being coated with a transparent or semi-transparent insulating film 19 such as a photoresist film, the semiconductor element chip 8 described above is processed by photolithography.
An opening 20 is formed at a dimensional position corresponding to the pad portion 11 . That is, if the main surface 17 of the glass substrate 16 is aligned over the surface of the semiconductor substrate 9 described above, the main surface 17
The upper opening 20 and the electrode pad 11 formed on the surface of the semiconductor substrate 9 match, in other words, the same structure as the relationship between the photomask and the material substrate in the photo process.
上記のような構成の基板のＩＴＯ膜１８を電極として１
例えばムロバンプの場合、ムロメツキ溶中で電解メッキ
を施こすことにより、第６図のようにＩＴＯ膜１Ｂの開
孔部２ｏにはムロメッキバンプ２１を形成することがで
きる。1 using the ITO film 18 of the substrate configured as above as an electrode.
For example, in the case of uneven bumps, by performing electrolytic plating in a uneven melt, uneven plating bumps 21 can be formed in the openings 2o of the ITO film 1B as shown in FIG.
以上のようにして形成した。その主面１７上にＡｕ メ
ッキバンブ２１を有するガラス基板１６の主面１７を、
第７図のように半導体基板９の主面上に載置し、ガラス
基板１６０ムＵメツキバンプ２１と半導体基板ｅ上のム
ｌ電極パッド部１１に位置合せを行う。この時半導体基
板９とガラス基板１６のアライメントはガラス基板１６
の構成が。It was formed as described above. A main surface 17 of a glass substrate 16 having an Au plating bump 21 on its main surface 17,
As shown in FIG. 7, it is placed on the main surface of the semiconductor substrate 9, and aligned with the glass substrate 160mm U plating bump 21 and the mullion electrode pad portion 11 on the semiconductor substrate e. At this time, the alignment of the semiconductor substrate 9 and the glass substrate 16 is
The composition of.
前述のようにＡｕメッキバング２１部以外の部位がいづ
れも透明あるいは半透明層であるため、ガラス基板１６
の裏面よりのアライメントは容易に可能な構造を有して
いる。As mentioned above, since all parts other than the Au plating bang 21 are transparent or semi-transparent layers, the glass substrate 16
has a structure that allows alignment from the back side easily.
上述のアライメントによシム！電極パッド１１群に対し
ムｑメッキバンプ２１群を合致させた後。Shim with the above alignment! After matching 21 groups of Muq plating bumps to 11 groups of electrode pads.
ガラス基板１６を加圧し、ムｌパッド１１群とムＵメッ
キバンプ２１群全圧接状態で保持させ、赤外線スポット
ビームもしくはレーザビーム等の熱線ビーム２２によシ
、ガラス基板１６後部より、ムロメッキバフ１２１部を
順次あるいは複数箇所同時に局部加熱を施こすことによ
り、ムＵメッキバンブ２１のムＵとムＥ電極パッド１１
のムＥ部が加熱されムロ−五ｌ共晶接合を形成する。The glass substrate 16 is pressurized to hold the MU pad 11 group and the MU plating bump 21 group in a state of pressure contact, and a heat ray beam 22 such as an infrared spot beam or a laser beam is applied to the glass substrate 16 from the rear of the MU plating buff 121. By sequentially or simultaneously applying local heating to multiple locations, the MuU and MuE electrode pads 11 of the MuU plating bump 21
The Muro E part is heated to form a Muro-5L eutectic junction.
しかる後ガラス基板１６を半導体基板９上より取り除け
ば、ムＵメッキバンブ２１はＩＴＯ膜層１８表面部位よ
り剥離し、半導体基板９上のムｌ電極パッド１１部位上
にムロメッキバンプ２１が転写形成される。After that, when the glass substrate 16 is removed from the semiconductor substrate 9, the mullium plating bumps 21 are peeled off from the surface of the ITO film layer 18, and the mullium plating bumps 21 are transferred and formed on the mullion electrode pads 11 on the semiconductor substrate 9. Ru.
以上が本発明の基本的な構成であり一従来例の項で記し
た半導体基鈑土の不良半導体チップ部位に対しては、バ
ンプ部位への局部加熱を施こさなければ、半導体基板９
上にムＵメクキバンブ２１が転写されない構成である。The above is the basic configuration of the present invention, and if the defective semiconductor chip portion of the semiconductor substrate described in the conventional example section is not locally heated to the bump portion, the semiconductor substrate 9
This is a configuration in which the mumekukibanbu 21 is not transferred onto the top.
しかし不良チップ部位に相対したガラス基板１６のムロ
メッキバンプ２１は転写されず、ガラス基板１６上に残
存するため、ガラス基板１６上に形成した全てのムＵメ
クキバンブ２１を有効に活用できない欠点も有している
。However, since the uneven plating bumps 21 on the glass substrate 16 facing the defective chip area are not transferred and remain on the glass substrate 16, there is also the drawback that all the uneven plated bumps 21 formed on the glass substrate 16 cannot be used effectively. are doing.
そこでガラス基鈑１６上に形成したムＵメクキバンブ２
１の全てを効率良く半導体基板９上に転写させる構造の
ガラス基板１６について以下に説明する。Therefore, the mumekuki bump 2 formed on the glass substrate 16
The glass substrate 16 having a structure that allows all of 1 to be efficiently transferred onto the semiconductor substrate 9 will be described below.
第８図は転写用ムロメッキバンプ２１を形成するだめの
短冊状ガラス基板１６の構造を示した局部斜視図である
。短冊状ガラス基板１６の主面１７には、第６図で示し
た構造と同様にＩＴＯ層１Ｂが、さらにその上部には透
明絶縁膜層１９を有している。透明絶縁膜層１９にはバ
ンプを構成すべき半導体基鈑９の半導体素子チップ８の
電極バッド１１ピッチＬ１．Ｌ２（第３図）と同一ピッ
チＬｊ’ 、 Ｌ２’で設計したムロメッキバンプ形成
用開孔２０が配置形成しである。FIG. 8 is a partial perspective view showing the structure of the rectangular glass substrate 16 on which the transfer plated bumps 21 are formed. The main surface 17 of the rectangular glass substrate 16 has an ITO layer 1B similar to the structure shown in FIG. 6, and a transparent insulating film layer 19 above it. The transparent insulating film layer 19 has electrode pads 11 pitches L1 . The apertures 20 for forming the opaque plating bumps are arranged and formed with the same pitch Lj' and L2' as L2 (FIG. 3).
なおガラス基板１６の一端は１７０層１８が露呈した部
位２３を設は電解によるムロメッキによるバンプ形成時
の電極接続を容易にしている０以上の構成の短冊状ガラ
ス基板１６を用い電解ムＵ メッキ処理を施こすと、第
６図で示した場合と同様に透明絶縁膜１９ｆ、マスクと
して、同開孔部２０にはＩＴＯ膜層１８が電極となった
ムＵメクキ層すなわちムロメッキバンプ２１が選択的に
形成された短冊状バンプ転写基板が得られる。（メッキ
バンプ部の断面構造は第６図と同じである。）この短冊
状ガラス基８ｉ１６を用いて、半導体基鈑９の基ｌ電極
パッド１１部に対する。ムロメッキバンプ２１の転写形
成は一第７図で示した製造プロセスと同一である。One end of the glass substrate 16 is provided with a portion 23 where the 170 layer 18 is exposed, which facilitates electrode connection during bump formation by electrolytic chromoplating. Then, as in the case shown in FIG. 6, a transparent insulating film 19f is used as a mask, and in the opening 20, a mullium-plated layer, that is, a muro-plated bump 21 is selected, with the ITO film layer 18 serving as an electrode. A strip-shaped bump transfer substrate is obtained. (The cross-sectional structure of the plating bump portion is the same as that in FIG. 6.) This strip-shaped glass substrate 8i16 is used to attach the base 1 electrode pad 11 portion of the semiconductor substrate 9. The transfer formation of the Muro plating bumps 21 is the same as the manufacturing process shown in FIG.
ただ短冊状ガラス基板１６の形状特性を生かして。However, by taking advantage of the shape characteristics of the rectangular glass substrate 16.
短冊状ガラス基板１６上に形成しであるムＵメッキバン
プ２１ｆｆ：端から順次、半導体基板ｅ上の良品半導体
素子チップ８上へのみ転写形成することができる。U-plated bumps 21ff formed on the rectangular glass substrate 16: These bumps can be transferred and formed sequentially from the end only onto the non-defective semiconductor element chip 8 on the semiconductor substrate e.
すなわち、第９図のようにその主面上に不良半導体素子
チップ８′が散在する半導体基板９の良品半導体素子チ
ップ８に対してのみ選択的にムロメッキバンプ２１を転
写形成する場合に一半導体素子チクグ８の電極パッド１
１部とパン１基板のムＵ７、キバンプ２１の位置合せ（
アライメント）を第９図の２点で行うとすると一半導体
基１ｉｉ９ＩＩｉそれぞれＸ−Ｘ’、Ｙ−Ｙ’力方向同
基鈑上に構成した半導体素子チップ８のチップサイズ寸
法でピッチ送シを行い、順次チップが２点に移動させる
ことになる。That is, when selectively transferring and forming the chrome plated bumps 21 only on the good semiconductor element chips 8 of the semiconductor substrate 9 on which defective semiconductor element chips 8' are scattered on the main surface as shown in FIG. Electrode pad 1 of element Chikugu 8
Aligning part 1 and pan 1 board's bump U7 and bump 21 (
If alignment) is performed at two points in Fig. 9, pitch feeding is performed using the chip size of the semiconductor element chip 8 constructed on the same base board in the X-X' and Y-Y' force directions, respectively. , the chips will be sequentially moved to two points.
例えば第９図において、チップ番地Ｖ−Ｋに対して転写
用ガラス基板１６のａ部のバンプをアライメントおよび
転写形成完了後、転写用ガラス基鈑１６はＹＹ方向に１
ピツチ移動させ２点に対してはｂが位置するようにする
。また半導体基板９はＸ′方向に１ピツチ移動すること
により、チップ番地Ｖｌ −Ｘが、２点で前記ガラス基
板１６上のムＵメッキバンプとのアライメントおよび転
写形成がなされる。またチップ番地■−Ｅの不良チップ
８′が２点に位置した場合は、半導体基板９をさらに１
チツプ移動させることによシ、半導体基板９上の良品半
導体素子チップ８に対してのみ、バンプ転写用ガラス基
板１６に形成したＡｕメッキバンプ２１が順次転写形成
することができる。For example, in FIG. 9, after alignment and transfer formation of the bumps on the portion a of the transfer glass substrate 16 with respect to the chip address VK, the transfer glass substrate 16 is moved 1 in the YY direction.
Move by pitch so that b is located with respect to the two points. Further, by moving the semiconductor substrate 9 one pitch in the X' direction, the chip address Vl-X is aligned and transferred to the M-U plating bump on the glass substrate 16 at two points. In addition, if the defective chip 8' with chip address ■-E is located at two points, the semiconductor substrate 9 is further
By moving the chips, the Au plating bumps 21 formed on the bump transfer glass substrate 16 can be sequentially transferred only to the non-defective semiconductor element chips 8 on the semiconductor substrate 9.
以上のようにして、半導体基板９上の良品半導体素子チ
ップ８に対してのみＡｕメッキバンプ２１を形成した後
は１通常のＴＡＢ法と同様に同バンプに対し、テープキ
ャリアのインナーリードをボンディングすることによシ
ミ極接続が完了することになる。After forming the Au plating bumps 21 only on the non-defective semiconductor chip 8 on the semiconductor substrate 9 as described above, 1. bond the inner leads of the tape carrier to the bumps in the same manner as in the normal TAB method. In this case, the stain electrode connection will be completed.
実施例２前述実施例１では予めＡｕメッキバンプを形成する基板
を短冊状ガラス基板状に形成したが本実施例は−その基
板をロールフィルム（テープキャリア用テープ状のもの
）を用いたものである。Example 2 In Example 1 described above, the substrate on which the Au plating bumps are to be formed was formed in advance in the shape of a rectangular glass substrate, but in this example, the substrate was formed using a roll film (a tape-shaped material for a tape carrier). be.
第１０図が本実施例の構造を示す斜視図であり一基板と
なる基材２４は透明あるいは半透明な例えばポリイミド
フィルムのような耐熱性の高い樹脂フィルムからなシ、
その両端部にはコマ送り用スプロケット２６が設けであ
る。FIG. 10 is a perspective view showing the structure of this embodiment. The base material 24 serving as one substrate is made of a transparent or semi-transparent resin film with high heat resistance such as a polyimide film.
Sprockets 26 for frame feeding are provided at both ends thereof.
基材２４の主面には例えばＩＴＯのような透明電極１８
（数１００人の厚さで蒸着した金属膜層でも良い）およ
び透明絶縁膜１９が積層形成されている。また透明絶縁
膜１９には前記実施例で説明した場合と同様の思想に基
づいた。Ａｕメッキバンプ形成用開孔部２０を有してい
る。A transparent electrode 18 such as ITO is provided on the main surface of the base material 24.
(A metal film layer deposited to a thickness of several hundred layers may also be used) and a transparent insulating film 19 are laminated. Further, the transparent insulating film 19 is based on the same concept as that described in the previous embodiment. It has an opening 20 for forming an Au plating bump.
このロールフィルム状基板の場合は、その特性を生かし
て−ＡｕＡｕメッキバンプ続的に形成することが可能と
なると共に、半導体基板９上へのＡｕメッキバンプの転
写形成も連続自動化が容易になる等の特徴を有している
〇発明の効果以上のように本発明の半導体装置の製造法によれば一半
導体チツブの良品のみに対してバングを形成することが
容易に実現できるため、素材コストの高いムロバンブを
用いる場合等においては。In the case of this roll film-like substrate, it is possible to continuously form -AuAu plated bumps by taking advantage of its characteristics, and it is also easy to continuously automate the transfer formation of Au plated bumps onto the semiconductor substrate 9. Effects of the Invention As described above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to easily form a bang on only a good semiconductor chip, thereby reducing material costs. In cases such as when using high mulobanbu.
ムＵの無駄が完全に排除されるなどコスト面で著しく有
利となり産業上有用な製造法である。It is an industrially useful manufacturing method that is extremely advantageous in terms of cost, such as completely eliminating waste of mu.
第１図は一般的なＴＪｋＢ実装法を示す断面図−第２図
は本発明における半導体基板の平面略図。第３図は同局部拡大図、第４図は半導体素子チップのパ
ッド領域の拡大断面図、第６図、第６図は本発明に用い
るＡｕメッキバンプ形成用短冊型ガラス基板の拡大断面
図、第７図は本発明のＡｕメッキバンプの半導体基板へ
の転写接続の状態を示す断面図、第８図は本発明の短冊
型ガラス基板の構造を示す局部斜視図、第９図は本発明
の短冊型ガラス基板を用いて半導体基板上の良品半導体
素子チップへの選択的転写を示す平面図、第１ｏ図はロ
ールフィルム基板の構造を示す局部拡大斜視図である。８・・・・・・半導体チップ、９・・−・・・半導体基
板（ウェハー）、１１・・・・・・電極パッド、１２・
・・・・・Ｓｉ基板−１３・・・・・・絶縁膜、１６・
・−・・・表面保護膜、１６・・・・・・ガラス基板、
１８・・−・−透明導電電極、１９・・・・−・絶縁膜
−２０・・・・・・開孔部、２１・−・・・−Ａｕメッ
キバンプー２２・・−・・・熱線ビーム＋２４・・・・
・・基材。代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図第３図第５図FIG. 1 is a sectional view showing a general TJkB mounting method, and FIG. 2 is a schematic plan view of a semiconductor substrate in the present invention. 3 is a local enlarged view of the same, FIG. 4 is an enlarged sectional view of the pad region of the semiconductor element chip, FIG. 6 is an enlarged sectional view of the rectangular glass substrate for forming Au plating bumps used in the present invention, FIG. 7 is a cross-sectional view showing the state of transfer connection of the Au plating bump of the present invention to the semiconductor substrate, FIG. 8 is a local perspective view showing the structure of the rectangular glass substrate of the present invention, and FIG. FIG. 1o is a plan view showing selective transfer to a non-defective semiconductor element chip on a semiconductor substrate using a rectangular glass substrate, and FIG. 1o is a partially enlarged perspective view showing the structure of a roll film substrate. 8... Semiconductor chip, 9... Semiconductor substrate (wafer), 11... Electrode pad, 12...
...Si substrate-13...Insulating film, 16.
... surface protective film, 16 ... glass substrate,
18...--Transparent conductive electrode, 19...--Insulating film-20......Opening part, 21...--Au plated bumper 22...--Heat ray beam +24...
··Base material. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 5
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58195645AJPS6086841A (en) | 1983-10-19 | 1983-10-19 | Manufacturing method for semiconductor devices |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58195645AJPS6086841A (en) | 1983-10-19 | 1983-10-19 | Manufacturing method for semiconductor devices |
| Publication Number | Publication Date |
|---|---|
| JPS6086841Atrue JPS6086841A (en) | 1985-05-16 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58195645APendingJPS6086841A (en) | 1983-10-19 | 1983-10-19 | Manufacturing method for semiconductor devices |
| Country | Link |
|---|---|
| JP (1) | JPS6086841A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686318A (en)* | 1995-12-22 | 1997-11-11 | Micron Technology, Inc. | Method of forming a die-to-insert permanent connection |
| US6404063B2 (en) | 1995-12-22 | 2002-06-11 | Micron Technology, Inc. | Die-to-insert permanent connection and method of forming |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686318A (en)* | 1995-12-22 | 1997-11-11 | Micron Technology, Inc. | Method of forming a die-to-insert permanent connection |
| US6133638A (en)* | 1995-12-22 | 2000-10-17 | Micron Technology, Inc. | Die-to-insert permanent connection and method of forming |
| US6387714B1 (en) | 1995-12-22 | 2002-05-14 | Micron Technology, Inc. | Die-to-insert permanent connection and method of forming |
| US6404063B2 (en) | 1995-12-22 | 2002-06-11 | Micron Technology, Inc. | Die-to-insert permanent connection and method of forming |
| Publication | Publication Date | Title |
|---|---|---|
| KR100418059B1 (en) | Bump Formation Method of Semiconductor Device | |
| JPS632332A (en) | Die-bonding process | |
| JP2005026311A (en) | Dicing film, flip chip mounting method, and semiconductor device | |
| JPS6086841A (en) | Manufacturing method for semiconductor devices | |
| JPH0626227B2 (en) | How to attach a semiconductor chip | |
| JP2978902B1 (en) | BGA type semiconductor device and its manufacturing method | |
| JP3267422B2 (en) | Bump transfer body and method of manufacturing semiconductor integrated circuit device | |
| JP2910398B2 (en) | Solder bump formation method | |
| JPS6364916B2 (en) | ||
| JPS61121449A (en) | Mounting structure and process of lsi chip | |
| JP2863426B2 (en) | Semiconductor device mounting structure and mounting method thereof | |
| JPS60130132A (en) | Manufacturing method of semiconductor device | |
| JP3021508B2 (en) | Method of forming conductive protrusions | |
| JPS607139A (en) | Bonding method | |
| JPH0357223A (en) | semiconductor equipment | |
| JPS6247139A (en) | Method for forming a transfer bump substrate | |
| JP3445687B2 (en) | Mounting method of semiconductor chip | |
| JPS6086853A (en) | Manufacturing method of semiconductor device | |
| JPS63124432A (en) | Method of forming wiring of film carrier | |
| JPH11289146A (en) | Composite wiring material and method of manufacturing the same | |
| JPH02232947A (en) | Semiconductor integrated circuit device and mounting thereof | |
| JPH02126647A (en) | bonding equipment | |
| JP2609709B2 (en) | Semiconductor chip mounting method | |
| JPH0469427B2 (en) | ||
| JPH05109734A (en) | Semiconductor device and method of manufacturing semiconductor device |