【発明の詳細な説明】く技術分野〉本発明は薄膜トランジスタ（以下ＴＰＴと称す）に関す
るものであり、特にアモルファスシリコン（以下ａ−８
ｉと称す）又は少なくとも一部が微結晶化したシリコン
（以下単に微結晶シリコンと称す）を用いた場合に特性
が良好で高い信頼性を得ることができるＴＰＴの構造に
関するものである。[Detailed Description of the Invention] Technical Field> The present invention relates to thin film transistors (hereinafter referred to as TPT), and particularly relates to amorphous silicon (hereinafter referred to as a-8
The present invention relates to a TPT structure that has good characteristics and can achieve high reliability when using microcrystalline silicon (hereinafter simply referred to as microcrystalline silicon) or silicon that is at least partially microcrystalline.
〈従来技術〉まず、従来の一般的なＴＰＴの構造及びその形成法につ
いて第１図とともに説明する。絶縁基板１上にゲート電
極２．ゲート絶縁膜３．半導体層４を順次堆積し、半導
体層４上にソース電極５及びドレイン電極６を形成し、
さらに保護膜７．光シールド８を順次堆積することによ
りＴＰＴが作製される。絶縁基板１としては一般的にガ
ラス板。<Prior Art> First, the structure of a conventional general TPT and its formation method will be explained with reference to FIG. A gate electrode 2 is formed on an insulating substrate 1. Gate insulating film 3. Sequentially depositing a semiconductor layer 4, forming a source electrode 5 and a drain electrode 6 on the semiconductor layer 4,
Furthermore, a protective film 7. A TPT is fabricated by sequentially depositing optical shields 8. The insulating substrate 1 is generally a glass plate.
セラミック板１石英板等が用いられる。また、ゲート電
極２はＡ ｔ＋ Ｎ １．Ｃｒ ＋ Ａ ｕ等の金属材
料。Ceramic plate 1 A quartz plate or the like is used. Further, the gate electrode 2 has A t+ N 1. Metal materials such as Cr + Au.
ゲート絶縁膜３はＳ ｉ Ｏ＋ Ｓ １０２ ＋ Ａｌ
２Ｏ３＋ Ｔａ２ｅｓ ＋Ｓｉ３Ｎ＜ 等の酸化物又は
窒化物、半導体層４はＣｄＳ 、 ＣｄＳｅ 、 Ｔｅ
、 ＰｂＳ 、 ａ−８ｉ又は微結晶シリコン等で形
成される。ソース電極５及びドレイン＋電極６としてはＡｔ又はａ−８ｉのｎ 膜等が用いられ
る。保護膜７は５ｔ（ｈ又はＳｉ３Ｎ＜等、光シールド
８はＡｔ等の金属材料が用いられる。The gate insulating film 3 is S i O + S 102 + Al
Oxide or nitride such as 2O3+ Ta2es +Si3N<, semiconductor layer 4 is CdS, CdSe, Te
, PbS, a-8i or microcrystalline silicon. As the source electrode 5 and the drain + electrode 6, an At or a-8i n film or the like is used. The protective film 7 is made of 5T (h or Si3N), and the optical shield 8 is made of a metal material such as At.
半導体層４としてａ−８４を用いた場合、ソース電極及
びドレイン電極材料としては、Ａｔもしくはｎ十ａ−８
ｊと金属の積層膜を使用することが多い。これらを、ソ
ース及びドレイン電極材料としてａ−８ｔのＴＰＴを製
作すると次のような問題が発生する。When a-84 is used as the semiconductor layer 4, At or n0a-8 is used as the source electrode and drain electrode material.
A laminated film of J and metal is often used. When a-8t TPT is manufactured using these as source and drain electrode materials, the following problems occur.
（１）ソース及びドレイン電極としてＡｔを用いた場合
、Ａｔの付着強度、膜質の安定性の観点から、通常Ａｔ
蒸着時に基板温度を高くするのであるが、この時ａ−８
ｉ上にＡｔを蒸着するために、ａ−８ｉ中にＡｔが拡散
し、ソース及びドレイン電極パターン化後もソース電極
とドレイン電極の間のａ−８ｔ中にＡｔが残留し、ソー
ス電極とドレイン電極との短絡ある妃はａ−Ｓｉ膜の変
質の原因となる。一方、低温でＡｔを蒸着すると付着力
、か弱く、膜質が不安定となる。(1) When At is used as the source and drain electrodes, from the viewpoint of At adhesion strength and film quality stability, At
The substrate temperature is raised during vapor deposition, but at this time a-8
In order to deposit At on i, At diffuses into a-8i, and even after patterning the source and drain electrodes, At remains in a-8t between the source and drain electrodes. A short circuit with the electrode causes deterioration of the a-Si film. On the other hand, if At is deposited at a low temperature, the adhesion will be weak and the film quality will be unstable.
（２） ソース及びドレイン電極としてｎ十ａ−８ｉ
と金属の積層膜を用いると、ＴＰＴは第２図の様な構造
となる。ソース及びドレイン電極の金属膜としてはＴｉ
等が用いられる。第２図の様な構造のＴＰＴを形成する
際、ｎ＋ａ−８ｉ ｌｌｉ ５１をパターン化するため
に、ｎ十ａ−８ｔ膜５１をａ−８ｉ半導体層に対して選
択的にエツチングする必要がある。ところが、ｎ＋ａ−
８ｉ膜とａ−８ｉ半導体層はエッチャントである（ＨＦ
十ＨＮＯｘ）混合溶液あるいはＣＦ ４ プラズマに対
して全く選択性がない。従って、ａ−８ｉ半導体層上の
ｎ＋ａ−８ｔをエツチングするためには、時間制御によ
り選択エツチングしなければならない。(2) n0a-8i as source and drain electrodes
If a laminated film of metal and metal is used, the TPT will have a structure as shown in FIG. Ti is used as the metal film for the source and drain electrodes.
etc. are used. When forming a TPT with a structure as shown in FIG. 2, it is necessary to selectively etch the n+a-8t film 51 with respect to the a-8i semiconductor layer in order to pattern the n+a-8i lli 51. . However, n+a-
The 8i film and the a-8i semiconductor layer are etchant (HF
There is no selectivity at all for mixed solutions (10HNOx) or CF 4 plasma. Therefore, in order to etch the n+a-8t layer on the a-8i semiconductor layer, selective etching must be performed by time control.
しかし、ｎａ−８ｉ膜の膜厚、膜質又はエツチング速度
のばらつきのためａ−８ｉＴＦＴ製作上の再現性が乏し
く、従ってＴＰＴ特性の安定性。However, due to variations in the film thickness, film quality, or etching speed of the Na-8i film, the reproducibility in manufacturing the A-8i TFT is poor, and the stability of the TPT characteristics is therefore poor.
再現性に乏しいのが現状である。このようなことがらｎ
ａ−８ｉ膜を選択的にエツチングする技術を確立するこ
とが特性の良好なＴＦ’Ｔを作製するために必要である
。At present, reproducibility is poor. Things like this
It is necessary to establish a technique for selectively etching the a-8i film in order to produce a TF'T with good characteristics.
（３）第１図及び第２図の様な構造のＴＰＴでは、ゲー
ト電極とソース及びドレイン電極との間にかなり大きな
容量が存在し、ＴＰＴの特性が大きな影響を受ける。(3) In a TPT having a structure as shown in FIGS. 1 and 2, a considerably large capacitance exists between the gate electrode and the source and drain electrodes, which greatly affects the characteristics of the TPT.
（４）第１図及び第２図の様なＴＰＴをマトリックス型
液晶表示装置のアドレス用の素子として用いる場合、ゲ
ート電極と絵素電極との間の絶縁膜が薄いため、ゲート
電極と絵素電極が重ならないように、パターンの位置合
せやエツチングの精度を見込んで第３図に平面図で示す
如くゲート電極２と絵素電極１００との間にギャップａ
及びｂを設ける必要がある。このために絵素電極１００
の面積が小さくなり、開口率が低くなってしまう。(4) When using a TPT as shown in Figures 1 and 2 as an addressing element in a matrix type liquid crystal display device, since the insulating film between the gate electrode and the picture element electrode is thin, To prevent the electrodes from overlapping, a gap a is created between the gate electrode 2 and the pixel electrode 100 as shown in the plan view in FIG.
and b need to be provided. For this purpose, the picture element electrode 100
The area becomes smaller, and the aperture ratio becomes lower.
上記問題点の（１）及び（２）を解決するため、第４図
に示す様なＴＰＴの構造が提唱され、使用に供されてい
る。即ち、半導体膜パターン化後ソース及びドレイン電
極を形成する前にソース及びドレイン電極のギャップに
絶縁体膜を形成しパターン化する構造である。しかし、
このＴＰＴ構造に於いても上記問題点の（３）及び（４
）は解決されておらず、良好なＴＰＴ特性を得るために
は、ゲート電極上ソース及びドレイン電極間の浮遊容量
を小さくすることが必要である。さらに、マトリックス
型液晶表示装置のアドレス用の素子としてＴＰＴを用い
た場合画像の明るさ及びコントラストを良くするために
開口率を大きくする必要がある。In order to solve the above problems (1) and (2), a TPT structure as shown in FIG. 4 has been proposed and put into use. That is, after patterning the semiconductor film and before forming the source and drain electrodes, an insulating film is formed and patterned in the gap between the source and drain electrodes. but,
This TPT structure also has the above problems (3) and (4).
) has not been solved, and in order to obtain good TPT characteristics, it is necessary to reduce the stray capacitance between the source and drain electrodes on the gate electrode. Furthermore, when a TPT is used as an addressing element in a matrix type liquid crystal display device, it is necessary to increase the aperture ratio in order to improve the brightness and contrast of an image.
〈発明の目的〉本発明は上述の問題点に鑑み、半導体層とソース及びド
レイン電極の界面にソース及びドレイン電極引き出し孔
を有する絶縁体層を形成することにより、ａ−８ｔ半導
体膜を汚染することなく、ｎ＋ａ−８ｔ膜とａ−８ｔ半
導体膜との選択エツチングも容易で、さらにゲート電極
とソース及びドレイン電極間の浮遊容量も小さくなシ、
ＴＰＴの動作特性及び信頼性も良好となるＴＰＴを提供
することを目的とするものである。<Object of the Invention> In view of the above-mentioned problems, the present invention provides a method for preventing contamination of an A-8T semiconductor film by forming an insulator layer having source and drain electrode extraction holes at the interface between the semiconductor layer and the source and drain electrodes. selective etching between the n+a-8t film and the a-8t semiconductor film is easy, and the stray capacitance between the gate electrode and the source and drain electrodes is small.
It is an object of the present invention to provide a TPT that has good operating characteristics and reliability.
〈実施例〉第５図は本発明の一実施例を示すＴＰＴの構成断面図で
ある。<Embodiment> FIG. 5 is a sectional view of the structure of a TPT showing an embodiment of the present invention.
ガラス基板１０上に蒸着法、スパッタリング等の薄膜生
成法でＴａ膜を層設した後、パターン化処理を介してＴ
ａ膜の不要部をエツチング除去し、ゲート電極２０とす
る。次にゲート電極２ｏを陽極酸化してその表面部分に
Ｔａ２０５のゲート絶縁膜３０を形成する。この上にプ
ラズマＣＶＤ法により５ｉａＮ４膜３１及びａ−８ｔ膜
４ｏを重畳して積層した後、パターン化し、二層、膜構
造を作製する。このａ−８ｉ膜４ｏがＴＰＴの半導体層
となる。After a Ta film is layered on the glass substrate 10 by a thin film forming method such as vapor deposition or sputtering, a T film is formed on the glass substrate 10 through a patterning process.
An unnecessary portion of the a film is removed by etching to form the gate electrode 20. Next, the gate electrode 2o is anodized to form a gate insulating film 30 of Ta205 on its surface. A 5iaN4 film 31 and an a-8t film 4o are superimposed and laminated thereon by the plasma CVD method, and then patterned to produce a two-layer film structure. This a-8i film 4o becomes a TPT semiconductor layer.
更に、プラズマＣＶＤ法により、５ｉｓＮａ膜９゜を堆
積してパターン化するとともにソース及びドレイン電極
引き出し孔を穿設する。次に、Ａｔ膜をＳｉ３Ｎ４膜９
０上に堆積し、ソース電極５０及びドレイン電極６０に
パターン化する。このＡｔ膜は５ｉａＮ４膜９０の引き
出し孔を介してａ−８ｉ膜４０と接触することとなる。Furthermore, a 5isNa film of 9° is deposited and patterned by plasma CVD, and holes for drawing out the source and drain electrodes are formed. Next, the At film is replaced with a Si3N4 film 9.
0 and patterned into a source electrode 50 and a drain electrode 60. This At film comes into contact with the a-8i film 40 through the extraction hole of the 5iaN4 film 90.
プラズマＣＶＤ法によりソース電極５０．ドレイン電極
６０及びＳｉ３Ｎ４膜９０上にＳｉ３Ｎ４保護膜７ｏを
被覆する。最後に、Ｓｉ３Ｎ４保護膜７０上にＡｔ膜を
堆積し、光シールド８０にパターン化して、ＴＰＴとす
る。このＴＰＴはａ−８ｉ半導体層４０とソースドレイ
ン電極５０．６０間にＳｉ３Ｎ４膜９０（７）絶縁層が
介在し、この絶縁層はほぼ全域に形成されている。Source electrode 50. is formed by plasma CVD method. A Si3N4 protective film 7o is coated on the drain electrode 60 and the Si3N4 film 90. Finally, an At film is deposited on the Si3N4 protective film 70 and patterned into a light shield 80 to form TPT. In this TPT, an insulating layer of Si3N4 film 90 (7) is interposed between the a-8i semiconductor layer 40 and the source/drain electrodes 50 and 60, and this insulating layer is formed over almost the entire area.
上記製造工程に於いて、ソース及びドレイン電極５０．
６０となるＡｔ膜は５ｉｓＮａ膜に穿設されたソース及
びドレイン電極引き出し孔を介してのみａ−８ｉ膜４０
に接しており、半導体層と不必要な接触がなく、ソース
電極とドレイン電極との間のａ−８ｔ半導体層がＡｔで
汚染されることがない。従ってＡｔ膜を蒸着法で形成す
る際、基板温度を高くすることが可能で、ａ−８ｉ半導
体層とソース及びドレイン電極との接触が良好となる。In the above manufacturing process, the source and drain electrodes 50.
The At film 60 is connected to the a-8i film 40 only through the source and drain electrode extraction holes drilled in the 5isNa film.
There is no unnecessary contact with the semiconductor layer, and the a-8t semiconductor layer between the source electrode and the drain electrode is not contaminated with At. Therefore, when forming an At film by vapor deposition, it is possible to raise the substrate temperature, and good contact between the a-8i semiconductor layer and the source and drain electrodes is achieved.
更に、ゲート電極とソース及びドレイン電極間の浮遊容
量も絶縁膜が存在することから、小さくなる。Furthermore, the stray capacitance between the gate electrode and the source and drain electrodes is also reduced due to the presence of the insulating film.
第６図は本発明の他の実施例を示すＴＰＴの構造断面図
である。FIG. 6 is a structural sectional view of a TPT showing another embodiment of the present invention.
ガラス基板１０上にＴａ膜を形成し、パターン化してゲ
ート電極２０とする。ゲート電極２ｏを陽極酸化してそ
の表面部分にＴａｚＯｓのゲート絶縁膜３０を形成する
。A Ta film is formed on a glass substrate 10 and patterned to form a gate electrode 20. The gate electrode 2o is anodized to form a TazOs gate insulating film 30 on its surface.
プラズマＣＶＤ法により、Ｓｉ３Ｎ４膜３１及びａ−８
ｉ膜４０を重畳して積層し、パターン化して二層膜とす
る。更に、プラズマＣＶＤ法により、５ｉｓＮ＜膜９０
を積層し、ａ−Ｓｉ膜４０に達する引き出し孔を穿設す
るとともにパターン化する。By plasma CVD method, Si3N4 film 31 and a-8
The i-films 40 are stacked and patterned to form a two-layer film. Furthermore, by plasma CVD method, 5isN<film 90
are laminated, and an extraction hole reaching the a-Si film 40 is formed and patterned.
プラズマＣＶＤ法によりａ−８ｉのｎ＋膜、蒸着法によ
＃）Ｔｉ膜を順次堆積し、ソース電極５５．５０及びド
レイン電極６５．６０にパターン化する。An a-8i n+ film is deposited by plasma CVD and a Ti film is sequentially deposited by vapor deposition, and patterned into a source electrode 55.50 and a drain electrode 65.60.
更にプラズマＣＶＤ法により、Ｓｉ３Ｎ４保護膜７０を
積層し、最後にＡｔ膜を堆積して光シールド８０にパタ
ーン化する。Furthermore, a Si3N4 protective film 70 is laminated by plasma CVD, and finally an At film is deposited and patterned into a light shield 80.
上記製造工程に於いて、ａ−８ｉのｎ 膜をエツチング
する際エツチングされるａ−８ｉＯｎ十膜の直下にはＳ
ｉ３Ｎ４膜があるため、ａ−８ｉのｎ 膜の選択エツチ
ングが可能で、ａ−８ｉ半導体膜の膜厚を薄くすること
が可能である。In the above manufacturing process, when etching the a-8i n film, the S
Because of the i3N4 film, selective etching of the a-8i n film is possible, making it possible to reduce the thickness of the a-8i semiconductor film.
第７図は本発明の他の実施例を示すＴＰＴの構造断面図
である。FIG. 7 is a structural sectional view of a TPT showing another embodiment of the present invention.
製造工程は、光シールドのＡｔ膜がないのを除き、第５
図に示すＴＰＴの製造工程と同様である。The manufacturing process is similar to the fifth one, except that there is no At film for the light shield.
The process is similar to the TPT manufacturing process shown in the figure.
本実施例では、ソース電極とドレイン電極の間隔を小さ
くシ、ソース及びドレイン電極を光シールドとして用、
い、光シールド形成工程を省略することが可能である。In this example, the interval between the source and drain electrodes is made small, and the source and drain electrodes are used as optical shields.
However, it is possible to omit the optical shield forming step.
マ） ＩＪソックス液晶表示装置のアドレス用素子とし
て本発明のＴＰＴを用いた場合、ゲート電極と絵素電極
との間に厚い絶縁体膜が存在することとなるため、設計
上第３図に示したゲート電極と絵素電極とのギャップａ
及びｌ〕をなくすことができ、絵素電極の面積が広くな
るとともに開口率が大きくなる。まだ、ゲート電極とソ
ース電極とのクロス部の電極間にも厚い絶縁体膜が存在
し、ゲート電極とソース電極間のクロス部の浮遊容量も
小さくすることができる。M) When the TPT of the present invention is used as an addressing element in an IJ socks liquid crystal display device, a thick insulating film will exist between the gate electrode and the pixel electrode, so the design shown in FIG. Gap a between the gate electrode and the picture element electrode
and l] can be eliminated, the area of the picture element electrode becomes wider, and the aperture ratio becomes larger. Still, a thick insulating film exists between the electrodes at the cross section between the gate electrode and the source electrode, and the stray capacitance at the cross section between the gate electrode and the source electrode can also be reduced.
〈発明の効果〉以上詳説した如く、本発明によれば、ＴＰＴの半導体膜
が製造プロセス中にソース・ドレイン電極材料で汚染さ
れたり、オーバーエツチングされることがなく、更に不
要なゲート電極とソース及びドレイン電極間の浮遊容量
も小さく押えることが可能となる。従って動作特性が良
好で信頼性の高いＴＰＴを得ることができる。また、光
シールド形成工程を省略することも可能であり、生産性
の高い製造技術が確立される。更に、マトリックス型液
晶表示装置のアドレス用素子としてＴＰＴを用いた場合
も開口率を大きく設定することができる。<Effects of the Invention> As explained in detail above, according to the present invention, the TPT semiconductor film is not contaminated with source/drain electrode materials or overetched during the manufacturing process, and furthermore, unnecessary gate electrodes and source Also, the stray capacitance between the drain electrodes can be kept small. Therefore, a TPT with good operating characteristics and high reliability can be obtained. Furthermore, it is also possible to omit the optical shield forming step, and a highly productive manufacturing technique is established. Furthermore, the aperture ratio can also be set large when TPT is used as an addressing element in a matrix type liquid crystal display device.
第１図及び第２図は従来のＴＰＴの構造を示す断面図で
ある。第３図は、従来のＴＰＴをマトリックス型液晶表
示装置のアドレス用素子として用いた場合の平面図であ
る。第４図は従来の改良されたＴＰＴの構造を示す断面
図である。第５図乃至第７図は各々本発明の１実施例を
説明するＴＰＴの断面図である。１．１０・・・絶縁基板 ２．２０・・・ゲート電極３
．３０．３１・・・ゲート絶縁膜 ４Ｉ４０・・・半導
体膜 ５，５０，５１．５５・・・ソース電極 ６゜６
０．６１．６５・・・ドレイン電極 ７，７０・・・保
護Ｊ１ｇ８．８０・・・光シールド ９．９０・・・絶
縁体膜 １００・・・絵素電極代理人 弁理士 福 士 愛 彦（他２名）第１図第２図第５図１ ２ ４ ３第４図第３図第６図第７図FIGS. 1 and 2 are cross-sectional views showing the structure of a conventional TPT. FIG. 3 is a plan view when a conventional TPT is used as an addressing element of a matrix type liquid crystal display device. FIG. 4 is a sectional view showing the structure of a conventional improved TPT. FIGS. 5 to 7 are cross-sectional views of TPT, each illustrating one embodiment of the present invention. 1.10... Insulating substrate 2.20... Gate electrode 3
．． 30.31...Gate insulating film 4I40...Semiconductor film 5,50,51.55...Source electrode 6゜6
0.61.65...Drain electrode 7,70...Protection J1g8.80...Light shield 9.90...Insulator film 100...Pixel electrode agent Patent attorney Aihiko Fukushi ( 2 others) Figure 1 Figure 2 Figure 5 1 2 4 3 Figure 4 Figure 3 Figure 6 Figure 7
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59016763AJPS60160173A (en) | 1984-01-30 | 1984-01-30 | thin film transistor |
| DE19853502911DE3502911A1 (en) | 1984-01-30 | 1985-01-29 | THIN FILM TRANSISTOR |
| GB08502348AGB2153589B (en) | 1984-01-30 | 1985-01-30 | Thin film transistor |
| GB08723748AGB2197985B (en) | 1984-01-30 | 1987-10-09 | Liquid crystal display |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59016763AJPS60160173A (en) | 1984-01-30 | 1984-01-30 | thin film transistor |
| Publication Number | Publication Date |
|---|---|
| JPS60160173Atrue JPS60160173A (en) | 1985-08-21 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59016763APendingJPS60160173A (en) | 1984-01-30 | 1984-01-30 | thin film transistor |
| Country | Link |
|---|---|
| JP (1) | JPS60160173A (en) |
| DE (1) | DE3502911A1 (en) |
| GB (2) | GB2153589B (en) |
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