【発明の詳細な説明】〔発明の技術分野〕本発明は、ＭＯ８型半導体装置及びその製造方法に係わ
り、特にケ゛−トを共通接続するＣ −ＭＯＳインバー
タ素子及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an MO8 type semiconductor device and a method of manufacturing the same, and more particularly to a C-MOS inverter element in which gates are commonly connected and a method of manufacturing the same.
従来、Ｃ−ＭＯＳインバータ素子は、第１図に示す如く
例えばｎ型Ｓｔ基板Ｉ中のｐ型ウェル２の表面に形成さ
れたｎチャネルＭＯＳ ）ランジスタ３と、ウェル２外
に形成されたｐティネルＭＯＳトランジスタ４とから構
成されている。ｎチャネルトランジスタ３のダート７と
ｐチャネルトランジスタ４０ケ゛−トＩＯとを接続して
入力端子Ａが構成され、ｎチャネルトランジスタ３のド
レイン６とｐチャネルトランジスタ４０ソース８とを接
続して出力端子Ｂが構成されている。また、ｎティネル
トランジスタ３０ンース５は低電位電源（ＧＮＤ ）端
子Ｃに接続され、ｐティネルトランジスタ４のドレイン
９は高電位電源（ｖＤＤ）端子りに接続されている。な
お、この素子の回路構成図を第２図に示す。Conventionally, a C-MOS inverter element consists of an n-channel MOS transistor 3 formed on the surface of a p-type well 2 in an n-type St substrate I, and a p-channel MOS transistor 3 formed outside the well 2, as shown in FIG. It is composed of a MOS transistor 4. An input terminal A is configured by connecting the gate 7 of the n-channel transistor 3 and the p-channel transistor 40 gate IO, and an output terminal B is configured by connecting the drain 6 of the n-channel transistor 3 and the source 8 of the p-channel transistor 40. is configured. Further, the n-channel transistor 30's source 5 is connected to a low potential power supply (GND) terminal C, and the drain 9 of the p-channel transistor 4 is connected to a high potential power supply (vDD) terminal. Incidentally, a circuit diagram of this element is shown in FIG. 2.
ところで、この種の素子では第１図からも判るように１
つのインバータが基板上で占める面を同一基板上に集積
化する場合、上記素子占有面積の大きさが微細化及び高
密度化を妨げる大きな要因となっていた。By the way, in this type of element, as can be seen from Fig.
When integrating the area occupied by two inverters on the same substrate, the size of the area occupied by the elements has been a major factor hindering miniaturization and high density.
本発明の目的は、Ｃ−ＭＯｓトランジスタ素子の素子占
有面積を小さくすることができ、微細化及び高密度化を
はかシ得るＭＯＳ型半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS semiconductor device which can reduce the area occupied by a C-MOS transistor element and which can be miniaturized and increased in density.
また本発明の他の目的は、特殊な技術を要することなく
上記装置を容易に実現できるＭＯＳ型半導体装置の製造
方法を提供する仁とにある。Another object of the present invention is to provide a method for manufacturing a MOS type semiconductor device that allows the above device to be easily realized without requiring any special technology.
本発明の骨子はＣ−ＭＯＳ ｌ−ランノスタを３次元的
に形成しそれぞれのｒ−計電極を共通接続することにあ
る。The gist of the present invention is to form a C-MOS l-rannostar three-dimensionally and connect the respective r-meter electrodes in common.
すなわち、本発明は、Ｃ−ＭＯＳトランジスタからなる
ＭＯＳ型半導体装置において、第１導電型の半導体基板
上に成長形成された第１導電型のエピタキシャル層と、
上記基板中の一部に設けられた第２導電型の第１のウェ
ルと、上記エピタキシャル層片の一部に上記第１のウェ
ルに接するよう設けられた第２導電型の第２のウェルと
、これら第１及び第２のウェルにそれぞれ設けられた第
１導電型の高濃度不純物層と、前記基板及び工げタキシ
ャル層にそれぞれ設けられた第２導電型の高濃度不純物
層と、上記名高。That is, the present invention provides a MOS semiconductor device including a C-MOS transistor, which includes: an epitaxial layer of a first conductivity type grown on a semiconductor substrate of a first conductivity type;
a first well of a second conductivity type provided in a part of the substrate; and a second well of a second conductivity type provided in a part of the epitaxial layer piece so as to be in contact with the first well. , a first conductivity type high concentration impurity layer provided in each of the first and second wells, a second conductivity type high concentration impurity layer provided in the substrate and the etched taxial layer, respectively; High.
旋回不純物層にそれぞれ接するよう前記エピタキシャル
層及び基板に設けられた穴部と、この穴部にダート絶縁
膜を介して設けられたダート電極とを具備してなるもの
である。The device includes a hole provided in the epitaxial layer and the substrate so as to be in contact with the swirling impurity layer, respectively, and a dirt electrode provided in the hole with a dirt insulating film interposed therebetween.
また、本発明は上記ＭＯＳ型半導体装置を製造するに際
し、第１導電型の半導体基板中の一部に第２導電型の第
１のつ為ルを形成し、該ウェルの表層に第１導電型の第
１の高濃度不純物層を形成し、かつ上記基板の表層に第
２導電型の第２の高濃度不純物層を形成したのち、前記
基板上に第１導電型のエビタキシイル層を成長形成し該
エピタキシャル層中に前記第１のウェルと接するよう第
２導電型の第２のウェルを形成し、この第２のウェルの
表層に第１導電型の第３の高濃度不純物層を形成し、か
つ上記エビタキシイル層の表層に第２導電型の第４の高
濃度不純物層を形成し、次いで上記エピタキシャル層の
表面から前記基板に至る深さまで前記第１乃至第４の高
濃度不純物層にそれぞれ接する穴部を形成し、しかるの
ち上記穴部にダート絶縁膜を介してｒ−計電極を形成す
るようにした方法である。Furthermore, when manufacturing the above-mentioned MOS type semiconductor device, the present invention includes forming a first hole of a second conductivity type in a part of the semiconductor substrate of the first conductivity type, and forming a first conductivity hole on the surface layer of the well. After forming a first high concentration impurity layer of a mold and forming a second high concentration impurity layer of a second conductivity type on the surface layer of the substrate, an Ebitaxyl layer of a first conductivity type is grown on the substrate. A second well of a second conductivity type is formed in the epitaxial layer so as to be in contact with the first well, and a third high concentration impurity layer of a first conductivity type is formed in a surface layer of the second well. , and forming a fourth high concentration impurity layer of a second conductivity type on the surface layer of the epitaxial layer, and then forming a fourth high concentration impurity layer of the first to fourth high concentration impurity layers from the surface of the epitaxial layer to the depth of the substrate, respectively. In this method, a contacting hole is formed, and then an r-meter electrode is formed in the hole through a dirt insulating film.
以下、本発明の詳細を第３図（、）〜（ｄ）を参照して
説明する。The details of the present invention will be explained below with reference to FIGS. 3(a) to (d).
まず、第３図（、）に示す如くｎ型半導体基板ＩＩの一
部にｐ型の第１のウェル１２ｆ形成し、このウェル１２
０表層にｎ型の第１の＾濃度不純物層Ｚ３を形成すると
共に、基板ＩＩの表層にｐ型の第２の高濃度不純物）＠
Ｚ ４を形成する。First, a p-type first well 12f is formed in a part of the n-type semiconductor substrate II as shown in FIG.
At the same time, an n-type first ^-concentration impurity layer Z3 is formed in the surface layer of the substrate II, and a p-type second high-concentration impurity layer) is formed in the surface layer of the substrate II.
Form Z 4.
次いで、気相成長法等によシ基板りｌ上に第３図（ｂ）
に示す如くエピタキシャル層ｚ５を成長し、このエピタ
キシャル層Ｉ５の一部に前記ウェル１２と接するようｐ
型の第２のウェル１６を形成する。そして、第２のウェ
ルＩ６の表層にｎ型の第３の高濃度不純物層１７を形成
すると共に、エピタキシ１ル層Ｉ６の表層にｐ型の第４
の高濃度不純物層Ｉ８を形成する。次いで、第３図（ｃ
）に示す如く前記第１乃至第４の高濃度不純物層１３，
１４，１７．１８の一部を含みエピタキシ丁ル層Ｉ５及
び基板１１を一部エッチングし、穴部１９ｆ形成し、こ
の穴部Ｚ９の底部に素子分離用の絶縁膜２０を埋め込む
。次いで、第３図（ｄ）に示す如く穴部側面及び試料表
面にダート絶縁膜２１を形成したのち、穴部１９にケ゛
−ト寛極２２を埋め込む。かくして、第１及び第３の高
濃度不純物層１３．１７とダート電極２２とからｎテヤ
ルＭＯ８）う／ジスタが構成され、第２及び第４の画濃
度不純物Ｎ１４゜１８とダート電極２２とからｐチャネ
ルＭＯ８トランジスタが構成されることになる。さらに
、第１及び第２の尚濃度不純物層１３．１４を接続する
ことによυ、Ｃ−ＭＯＳインバータが構成されることに
なる。Next, by a vapor phase growth method or the like, the substrate is deposited as shown in FIG. 3(b).
An epitaxial layer z5 is grown as shown in FIG.
A second well 16 of the mold is formed. Then, an n-type third high concentration impurity layer 17 is formed in the surface layer of the second well I6, and a p-type fourth impurity layer 17 is formed in the surface layer of the epitaxial layer I6.
A high concentration impurity layer I8 is formed. Next, Figure 3 (c
), the first to fourth high concentration impurity layers 13,
A hole 19f is formed by etching a portion of the epitaxial layer I5 and the substrate 11, including a portion of the holes Z9, and an insulating film 20 for element isolation is buried in the bottom of the hole Z9. Next, as shown in FIG. 3(d), a dirt insulating film 21 is formed on the side surface of the hole and the surface of the sample, and then a cathode electrode 22 is embedded in the hole 19. In this way, the first and third high-concentration impurity layers 13,17 and the dirt electrode 22 constitute an n-type MO8), and the second and fourth high-concentration impurity layers N14,18 and the dirt electrode 22 constitute an n-type MO8). A p-channel MO8 transistor will be configured. Furthermore, by connecting the first and second heavily doped impurity layers 13 and 14, a C-MOS inverter is constructed.
本発明によれば、同一のケ９−ト電極を介してｎチャネ
ル及びｐチャネルの各ＭＯ８）ランジスタが向い合うよ
う３次元的に構成されるので、これら一対のＭＯＳトラ
ンジスタの素子占有面積を大幅に小さくすることができ
る。このため、ＭＯ８型半導体装置の微細化及び商密度
化をはかることができる。また、特殊な技術を要するこ
となく、現在実用化されている公知の製造技術によシ容
易に実現することが可能である。According to the present invention, since the n-channel and p-channel MO8) transistors are three-dimensionally configured to face each other via the same gate electrode, the area occupied by the pair of MOS transistors can be greatly reduced. can be made smaller. Therefore, it is possible to miniaturize the MO8 type semiconductor device and increase its commercial density. Furthermore, it can be easily realized using known manufacturing techniques that are currently in practical use, without requiring special techniques.
第４図（−）〜（ｇ）は本発明の一実施例に係わるＣ−
ＭＯＳインバータ製造製造工水す断面図である。FIG. 4(-) to (g) are C- according to an embodiment of the present invention.
It is a sectional view of a MOS inverter manufacturing plant.
まず、第４図（−）に示す如くｎ型別基板４１の一部表
層にｐ型ウェル（第１のウェル）４２を形成し、このウ
ェル４２０表１鉛にれ崩（第１の高濃度不純物層）４３
を形成する。そして、ｐ型ウェル４２の両列側の基板４
Ｉの表面にｐ＋）ｔ４（第２の高濃度不純物）−） ４
ｎをそれぞれ形成する。次いで、気相成長法を用い第４
図（ｂＪに示す如く基板４１上にｎ型Ｓ１工ピタキシτ
ル層４５ｆ：成長形成し、こ６工ビタキシτル層４５の
一部に前記ｐ型ウェル４２と連接するｐ型ウェル（第２
のウェル）４６を形成する。その後、ｐ型ウェル４６０
表面にｎ＋層（第３の高濃度不純物層）４７を形成し、
ｐ型ウェル４６の外ｉｔ＋＋の基板４１の表面にｐ＋層
（第４の高濃度不純物１ｍ ） ａ ｓをそれぞれ形成
する。なお、図中４９はフィールド酸化膜であシ、この
フィールド酸化膜４９によシ上記層層４７を２つに分離
している。First, as shown in FIG. 4(-), a p-type well (first well) 42 is formed on a part of the surface layer of an n-type substrate 41, and this well 420 collapses into lead (the first high-concentration well). impurity layer) 43
form. Then, the substrate 4 on both row sides of the p-type well 42
p+)t4 (second high concentration impurity)-)4 on the surface of I
n respectively. Next, a fourth layer is grown using the vapor phase growth method.
As shown in Figure (bJ), an n-type S1 pitaxe
layer 45f: grown and formed in a part of this hexagonal bitaxy layer 45 (second p-type well 45f) connected to the p-type well 42
A well) 46 is formed. After that, the p-type well 460
Forming an n+ layer (third high concentration impurity layer) 47 on the surface,
A p+ layer (fourth high-concentration impurity 1m) a s is formed on the surface of the it++ substrate 41 outside the p-type well 46. Note that 49 in the figure is a field oxide film, and this field oxide film 49 separates the layer 47 into two.
次に、ドライエツチング法を用い第４図（ｄ）に示す如
くエビクキシャル層４５及び基板４１を一部エッチング
し、穴部５０を形成する。ここで、上記穴部５０は前記
層層４３．４７及び２層４４．４８に接するよう形成さ
れる。また、＋第４図（ｄ）に示す工程までの試料の平面図を第５図（
ａ）に示す。第４図（ｄ）は第５図（、）の矢視Ａ−Ａ
断面に対応するものである。Next, using a dry etching method, as shown in FIG. 4(d), part of the evictional layer 45 and the substrate 41 are etched to form a hole 50. Here, the hole 50 is formed so as to be in contact with the layer 43.47 and the second layer 44.48. In addition, Figure 5 (+) shows the plan view of the sample up to the step shown in Figure 4 (d).
Shown in a). Figure 4(d) is the arrow view A-A in Figure 5(,).
This corresponds to a cross section.
記穴部５０の底部に素子分離のためのＳｉＯ２膜（絶縁
膜）５Ｚを埋め込む。続いて、熱酸化法を用い試料板面
及び穴部側面にダート酸化膜５２を形成する。次いで、
上記穴部５０に第４図（ｆ）に示す如く一部が試料表面
に突出するより多結晶シリコン膜（ケ゛−ト電極）５３
を埋め込む。この後、第４図（ｇ）に示す如く菓子保護
膜５４を堆積し、この保膿膜５４に所望のコンタクトホ
ールを形成し、さらにＡＡ配線膜５５を堆積することに
よって、Ｃ−ＭＯＳインバータが構成される。この状態
の平面図葡第５図（ｂ）に示す。An SiO2 film (insulating film) 5Z for element isolation is buried in the bottom of the recording hole 50. Subsequently, a dart oxide film 52 is formed on the sample plate surface and the hole side surface using a thermal oxidation method. Then,
As shown in FIG. 4(f), a polycrystalline silicon film (gate electrode) 53 is placed in the hole 50, with a portion protruding onto the sample surface.
Embed. Thereafter, as shown in FIG. 4(g), a confectionery protective film 54 is deposited, a desired contact hole is formed in this purulent retention film 54, and an AA wiring film 55 is deposited to form a C-MOS inverter. configured. A plan view of this state is shown in FIG. 5(b).
ここで、第４図（ｇ）は第５図（ｂ）の矢視Ｂ−Ｂ断面
に対応している。また、基板４１中のｐＪｆｉ４４はＧ
ＮＤ電源に接続するため、コンタクトホールを介してＡ
／＝配線膜５６に接続される。同様にｐ型ウェル４２中
のｎｌ脅４３は”ＤＩ、電源に接続するため、コンタク
トホール合弁してｋｔ配縁膜５７に接続されるものとな
っている。Here, FIG. 4(g) corresponds to the cross section taken along arrow BB in FIG. 5(b). Furthermore, pJfi44 in the substrate 41 is G
A through the contact hole to connect to the ND power supply.
/=connected to the wiring film 56. Similarly, the Nl gate 43 in the p-type well 42 is connected to the KT dielectric film 57 through a joint hole in order to connect to the DI and power source.
かくして本実施例によれば、ｎ層４．１．４７ランジス
タと、１層４４．４８及びダート電極５３からなるｐチ
ャネルＭＯ８トランジースタとが、同一のダート電極５
３を共有して構成され、かつ互いに対向する形に３次元
的に構成されるので、素子占有面積の極めて小さいＣ−
ＭＯＳインバータが実現できる。このため、多数のＣ−
ＭＯＳインバータを集積化してなるＭＯ８型半導体装置
の微組化及び高密度化に寄与し得る等の効果を奏する。Thus, according to this embodiment, the n-layer 4.1.47 transistor and the p-channel MO8 transistor consisting of the single layer 44.48 and the dirt electrode 53 are connected to the same dirt electrode 5.
3 in common, and are three-dimensionally configured to face each other, so the C-
A MOS inverter can be realized. For this reason, a large number of C-
This has effects such as contributing to microstructuring and higher density of MO8 type semiconductor devices formed by integrating MOS inverters.
また、特殊な技術を必要とすることもなく、公知の製造
技術を用いるのみで容易に実現し得る等の利点がある。Further, there is an advantage that no special technology is required and it can be easily realized using only known manufacturing technology.
なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記ｎ型ｓｉ基板の代りにｐ型Ｓｔ基板を
用いてもよいのは勿論のことで１７、さらに８１以外の
半導体基板を用いることも可能である。ま７ｊ、Ｃ−Ｍ
ＯＳインバータに限らず、ダート電極を共通接続する各
種のＣ−ＭＯ８素子に適用できるのも勿論のことである
。その他、本発明の要旨を逸脱しない範囲で、種々変形
して実施することができる。Note that the present invention is not limited to the embodiments described above. For example, it goes without saying that a p-type St substrate may be used instead of the n-type Si substrate, and it is also possible to use semiconductor substrates other than 17 and 81. M7j, C-M
Of course, the present invention is applicable not only to OS inverters but also to various C-MO8 elements in which dart electrodes are commonly connected. In addition, various modifications can be made without departing from the gist of the present invention.
第１図は従来のＣ−ＭＯＳインバータの素子構造を示す
断面図、第２図は上記Ｃ−ＭＯＳインバータの回路構成
図、第３図（ａ）〜（ｄ）は本発明の詳細な説明するた
めの工程断面図、第４図（、）〜優）は本発明の一実施
例に係わるＣ −ＭＯＳインバータ製造工程を示す断面
図、第５図（、） （ｂ）は上記実施例を説明するため
のもので第５図（−）は第４図（ｄ）の工程図に対応す
る平面図、第５図（ｂ）は第４図優）の工程図に対応す
る平面図である。１１．４１・・・８１基板（半導体基板）、Ｚ２゜４２
・・・ｐ型ウェル（第１のウェル）、１３゜４３・・・
ｎ層（第１の高濃度不純物層）、１４゜４４・・・ｐ層
（第２の高濃度不純物層）、１５゜４５・・・ｎ型エピ
タキシャル層、１６．４６・・・ｐ型ウェル（第２のウ
ェル）、１７．４７・・・層層（第３の高濃度不純物層
）、１８．４８・・・Ｉ） Ｉｔｉｌ（第４の高濃度不
純物層）、１９．５０・・・穴部、２０．５１・・・Ｓ
ｉＯ２膜（絶縁膜）、２１．５２・・・ダート絶縁膜、
２２．５３・・・多結晶シリコン膜（ゲート電極）、４
９・・・フィールド酸化膜、５４・・・素子保護膜、５
５．５６．５７・・臼ａ配線膜。出願人代理人 弁理士 鈴 江 武 彦第１図第２図第３図ｉ！４図第４図第５図FIG. 1 is a cross-sectional view showing the element structure of a conventional C-MOS inverter, FIG. 2 is a circuit diagram of the C-MOS inverter, and FIGS. 3(a) to 3(d) are detailed explanations of the present invention. 4(a) to 4(b) are sectional views showing the manufacturing process of a C-MOS inverter according to an embodiment of the present invention, and FIG. 5(a) to (b) illustrate the above embodiment. FIG. 5(-) is a plan view corresponding to the process diagram of FIG. 4(d), and FIG. 5(b) is a plan view corresponding to the process diagram of FIG. 11.41...81 substrate (semiconductor substrate), Z2°42
...p-type well (first well), 13°43...
n layer (first high concentration impurity layer), 14゜44...p layer (second high concentration impurity layer), 15゜45...n type epitaxial layer, 16.46...p type well (second well), 17.47...layer (third high concentration impurity layer), 18.48...I) Itil (fourth high concentration impurity layer), 19.50... Hole part, 20.51...S
iO2 film (insulating film), 21.52... dart insulating film,
22.53...Polycrystalline silicon film (gate electrode), 4
9...Field oxide film, 54...Element protection film, 5
5.56.57...Mole a wiring membrane. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 i! Figure 4Figure 4Figure 5
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57112977AJPS594080A (en) | 1982-06-30 | 1982-06-30 | Mos type semiconductor device and manufacture thereof |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57112977AJPS594080A (en) | 1982-06-30 | 1982-06-30 | Mos type semiconductor device and manufacture thereof |
| Publication Number | Publication Date |
|---|---|
| JPS594080Atrue JPS594080A (en) | 1984-01-10 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57112977APendingJPS594080A (en) | 1982-06-30 | 1982-06-30 | Mos type semiconductor device and manufacture thereof |
| Country | Link |
|---|---|
| JP (1) | JPS594080A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4902637A (en)* | 1986-03-03 | 1990-02-20 | Mitsubishi Denki Kabushiki Kaisha | Method for producing a three-dimensional type semiconductor device |
| JPH05166094A (en)* | 1991-04-30 | 1993-07-02 | Mitsubishi Corp | Local controller for traffic signal on main road |
| US5302542A (en)* | 1992-05-06 | 1994-04-12 | Kabushiki Kaisha Toshiba | Method of making a semiconductor memory device |
| US5391505A (en)* | 1993-11-01 | 1995-02-21 | Lsi Logic Corporation | Active device constructed in opening formed in insulation layer and process for making same |
| KR100396432B1 (en)* | 2001-09-10 | 2003-09-02 | 주식회사 미뉴타텍 | Method for fabricating semiconductor devices by using pattern with three-dimensional |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4902637A (en)* | 1986-03-03 | 1990-02-20 | Mitsubishi Denki Kabushiki Kaisha | Method for producing a three-dimensional type semiconductor device |
| JPH05166094A (en)* | 1991-04-30 | 1993-07-02 | Mitsubishi Corp | Local controller for traffic signal on main road |
| US5302542A (en)* | 1992-05-06 | 1994-04-12 | Kabushiki Kaisha Toshiba | Method of making a semiconductor memory device |
| US5391505A (en)* | 1993-11-01 | 1995-02-21 | Lsi Logic Corporation | Active device constructed in opening formed in insulation layer and process for making same |
| US5523600A (en)* | 1993-11-01 | 1996-06-04 | Lsi Logic Corporation | Active device constructed in opening formed in insulation layer |
| KR100396432B1 (en)* | 2001-09-10 | 2003-09-02 | 주식회사 미뉴타텍 | Method for fabricating semiconductor devices by using pattern with three-dimensional |
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