【発明の詳細な説明】産業上の利用分野この発明は半導体装置の製造方法に関し、特に半導体基
板上に金属等の薄膜パターンを形成するリフトオフ法に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a lift-off method for forming a thin film pattern of metal or the like on a semiconductor substrate.
従来例の構成とその問題点半導体基板全面に付着された金属膜を選択的に除去して
所望の金属パターンを形成するときに、金稿膜形成前に
、所望金属パターン部以外の部分にあらかじめたとえば
フォトレジスト膜をつけておきその上にたとえば金々ど
の金属を付着させた後、前記フォトレジストの除去とと
もに所望金属パターン部以外の金属膜をも除去して金属
パターンを得るリフトオフ法がある。これは、微細パタ
ーン形成のためや化学エツチングの困難な金属パターン
形成のためや多層金属パターン形成のためなどによく用
いられる方法である。この方法では基板上に形成した被
膜による段差を利用している3ベーラ゛ので被膜の厚さが問題となる。Conventional configuration and its problems When forming a desired metal pattern by selectively removing a metal film attached to the entire surface of a semiconductor substrate, before forming the metal film, it is necessary to remove the metal film from the area other than the desired metal pattern in advance. For example, there is a lift-off method in which a photoresist film is formed, a metal such as gold is deposited thereon, and then the photoresist is removed and the metal film other than the desired metal pattern portion is also removed to obtain a metal pattern. This is a method often used for forming fine patterns, metal patterns that are difficult to chemically etch, and multilayer metal patterns. In this method, the thickness of the coating becomes a problem since it is a three-layer method that utilizes the step difference caused by the coating formed on the substrate.
このだめ、第1図に示すように基板1上に絶縁膜2を形
成しくA)、その上にフォトレジスト3で所望のフォト
レジストパターン4を形成しくB)、絶縁膜2をリアク
ティブイオンエツチングした後(C)、全面に金属6を
付着しくD)、フォトレジスト3とともに不要金属6を
除去すれば所望の金属パターン6が得られる(E)。こ
の場合絶縁膜2は段差を太きくするためと金属パターン
形成後の表面平坦化のはたらきをする。しかし、この場
合、フォトレジストパターン4のわずかなテーパーによ
ってリフトオフ後の金属パターンエツジ切れがわるく不
要物7が残る。そこで、金属パターンのエツジ切れを良
好にするだめ、逆テーパ−パターンや絶縁膜のザイドエ
ノチングが考えられた。In this case, as shown in FIG. 1, an insulating film 2 is formed on the substrate 1 (A), a desired photoresist pattern 4 is formed on it with a photoresist 3 (B), and the insulating film 2 is reactive ion etched. After that (C), the metal 6 is attached to the entire surface (D), and the unnecessary metal 6 is removed together with the photoresist 3 to obtain the desired metal pattern 6 (E). In this case, the insulating film 2 functions to increase the thickness of the step and to flatten the surface after the metal pattern is formed. However, in this case, due to the slight taper of the photoresist pattern 4, the edges of the metal pattern are not easily cut after lift-off, and unnecessary materials 7 remain. Therefore, in order to improve the edge cutting of the metal pattern, a reverse taper pattern and zide etching of the insulating film were considered.
第2図にサイドエッチパターンを用いたりフトオフ法を
示す。基板11上に絶縁膜12を形成した後(A)、フ
ォトレジスト13で所望のレジストパターン14を形成
しくB)、絶縁膜を等方性エツチングしくC)、アンダ
ーカット16を形成する■)。次に金属16を全面に付
着しくK)、リフトオフを行い金属パターン17を形成
する(F)。この方法の場合金属パターン17のエツジ
切れは良好であるが、金属パターン1了の幅の広がりが
問題となる。従って、従来はパターンエツジ切れのよい
、パターン幅の正確な金属パターンを得ることが難しか
った。FIG. 2 shows a method using a side etch pattern or a foot-off method. After the insulating film 12 is formed on the substrate 11 (A), a desired resist pattern 14 is formed using a photoresist 13 (B), the insulating film is isotropically etched (C), and an undercut 16 is formed (2). Next, metal 16 is deposited on the entire surface (K), and lift-off is performed to form metal pattern 17 (F). In this method, the edge breakage of the metal pattern 17 is good, but the problem is that the width of the metal pattern 1 widens. Therefore, conventionally it has been difficult to obtain a metal pattern with good pattern edge cutting and accurate pattern width.
発明の目的この発明は、このような欠点を改善したものであり、半
導体基板上に金属等の薄膜パターンを形成する場合、段
差部をもつよつな開孔を形成しこれをリフトオフに利用
することによってエツジ切れの良い、所望の幅のパター
ンを提供する。Purpose of the Invention The present invention improves these drawbacks, and when forming a thin film pattern of metal or the like on a semiconductor substrate, a wide opening with a stepped portion is formed and this is used for lift-off. This provides a pattern with sharp edges and a desired width.
発明の構成この発明は、半導体基板上に金属等の薄膜パターンを形
成する場合、被膜にフォトレジスト等のマスク及び多層
の絶縁膜を用いて段差部をもつような開孔部を形成し、
これを利用してリフトオフを行いエツジ切れの良い、所
望の幅をもつ金属等の薄膜パターンを得るものである。Structure of the Invention This invention provides a method for forming a pattern of a thin film of metal or the like on a semiconductor substrate by forming an opening having a stepped portion in the film using a mask such as a photoresist and a multilayer insulating film.
 This is used to perform lift-off to obtain a thin film pattern of metal, etc., with good edge cutting and a desired width.
実施例の説明6ページ次にこの発明を実施例によって詳細に説明する。Description of examples6 pagesNext, the present invention will be explained in detail by way of examples.
第3図に示すようにたとえば半導体結晶のGaAs基板
21上に酸化シリコンを多量に含んだシリコン窒化膜2
2をプラズマcvnで26oO人形成し、その上に酸化
シリコンをほとんど含1ないシリコン窒化膜23を15
00人形成する(A)。次にフォトレジスト24(例え
ばムZ1400−31)を用いて所望のパターン25を
抜きパターンで形成する申)。As shown in FIG. 3, a silicon nitride film 2 containing a large amount of silicon oxide is formed on a GaAs substrate 21 made of semiconductor crystal, for example.
 A silicon nitride film 23 containing almost no silicon oxide is formed on the silicon nitride film 23 by 1500 nm using plasma CVN.
 Form 00 people (A). Next, a desired pattern 25 is formed as a punch pattern using a photoresist 24 (for example, Mu Z1400-31).
次いでOF4雰囲気中でリアクティブイオンエッチで2
層の窒化膜を異方性エツチングする(C)。その後OF
4雰囲気中で等方性エツチングを行い、酸化シリコンを
多量に含む第1のシリコン窒化膜22と酸化シリコンを
含1ない第2のシリコン窒化膜21とのエツチング速度
の違いによって段差部26が形成される(D)。次に金
属2了としてPt、Ti、ムUをそれぞれ500人、、
500A、  3oooA全面に蒸着する停)。この時
、開孔部では容易に金属エツジ切れが生じている。この
後フォトレジスト25を除去するためにアセトンに浸漬
し、超音波処理6ページすれば容易に7オトレジスト24とその上の不要金属膜
27は除去され所望の金属パターン28が得られる。こ
の時表面はほぼ平坦化している。以上、本発明の一実施
例を示したが、本発明は2層に限らず、多層の絶縁膜に
応用できる。Then, 2
 Anisotropically etching the nitride layer (C). Then OF
 4. Performing isotropic etching in an atmosphere, step portions 26 are formed due to the difference in etching speed between the first silicon nitride film 22 containing a large amount of silicon oxide and the second silicon nitride film 21 containing no silicon oxide. (D) Next, 500 people each of Pt, Ti, and MuU were used as the second metal.
 500A, 3oooA (deposited over the entire surface). At this time, the metal edge easily breaks at the opening. Thereafter, in order to remove the photoresist 25, the photoresist 24 and the unnecessary metal film 27 thereon are easily removed by immersion in acetone and six pages of ultrasonic treatment, and the desired metal pattern 28 is obtained. At this time, the surface is almost flat. Although one embodiment of the present invention has been described above, the present invention is applicable not only to two-layer insulating films but also to multi-layer insulating films.
発明の効果以上のようにこの発明は、金属等の薄膜パターンを形成
する場合、被膜にフォトレジスト等のマスク及び多層の
絶縁膜を用いて段差部をもつような開孔部を形成し、こ
れを利用してリフトオフを行うことによってエツジ切れ
のよい、所望の幅をtつ金属等の薄膜パターンを形成す
ることができる。Effects of the Invention As described above, in the case of forming a thin film pattern of metal or the like, this invention forms an opening having a stepped portion in the film using a mask such as a photoresist and a multilayer insulating film. By performing lift-off using the method, it is possible to form a thin film pattern of metal or the like with good edge cutting and a desired width of t.
第1図(ム)〜(E)、!2図(A)〜(F)は従来の
リフトオフ法より金属パターンを形成する工程を示す断
面図、第3図(ム)〜伊)はこの発明の一実施例の方法
により金属パターンを形成する工程を示す断面図である
。21・・・・・・基板、22.23・・・・・・シリコ
ン窒化膜、Yベージ24・・・・・・フォトレジスト、26・・・・・・段
差部、28・・・・・・@属パターン。代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図第 2(!iQ第3図8Figure 1 (Mu) to (E),! 2 (A) to (F) are cross-sectional views showing the process of forming a metal pattern using the conventional lift-off method, and FIGS. It is a sectional view showing a process. 21...Substrate, 22.23...Silicon nitride film, Y base 24...Photoresist, 26...Step portion, 28...・@genus pattern. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
 Figure 2 (!iQ Figure 3 8
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| JP58014899AJPS59141222A (en) | 1983-01-31 | 1983-01-31 | Manufacture of semiconductor device | 
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| JP58014899AJPS59141222A (en) | 1983-01-31 | 1983-01-31 | Manufacture of semiconductor device | 
| Publication Number | Publication Date | 
|---|---|
| JPS59141222Atrue JPS59141222A (en) | 1984-08-13 | 
| Application Number | Title | Priority Date | Filing Date | 
|---|---|---|---|
| JP58014899APendingJPS59141222A (en) | 1983-01-31 | 1983-01-31 | Manufacture of semiconductor device | 
| Country | Link | 
|---|---|
| JP (1) | JPS59141222A (en) | 
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|---|---|---|---|---|
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| KR100490575B1 (en)* | 2001-08-03 | 2005-05-17 | 야마하 가부시키가이샤 | Method of forming noble metal thin film pattern | 
| EP3530084A4 (en)* | 2016-10-28 | 2020-06-24 | Board of Regents, The University of Texas System | ELECTRICAL DEVICES WITH ELECTRODES ON SOFTENING POLYMERS AND METHODS OF MAKING SAME | 
| Publication number | Priority date | Publication date | Assignee | Title | 
|---|---|---|---|---|
| JPH02275643A (en)* | 1989-01-19 | 1990-11-09 | Sanyo Electric Co Ltd | Manufacture of semiconductor device | 
| US5091342A (en)* | 1989-02-24 | 1992-02-25 | Hewlett-Packard Company | Multilevel resist plated transfer layer process for fine line lithography | 
| US5006478A (en)* | 1989-07-25 | 1991-04-09 | Sony Corporation | Method for manufacture of semiconductor device | 
| US5266516A (en)* | 1992-01-02 | 1993-11-30 | Chartered Semiconductor Manufacturing Pte Ltd | Method for making electrical contact through an opening of one micron or less for CMOS technology | 
| KR100490575B1 (en)* | 2001-08-03 | 2005-05-17 | 야마하 가부시키가이샤 | Method of forming noble metal thin film pattern | 
| EP3530084A4 (en)* | 2016-10-28 | 2020-06-24 | Board of Regents, The University of Texas System | ELECTRICAL DEVICES WITH ELECTRODES ON SOFTENING POLYMERS AND METHODS OF MAKING SAME | 
| US11596072B2 (en) | 2016-10-28 | 2023-02-28 | Board Of Regents, The University Of Texas System | Electrical devices with electrodes on softening polymers and methods of manufacturing thereof | 
| US11991836B2 (en) | 2016-10-28 | 2024-05-21 | Board Of Regents, The University Of Texas System | Electrical devices with electrodes on softening polymers and methods of manufacturing thereof | 
| US12262481B2 (en) | 2016-10-28 | 2025-03-25 | Board Of Regents, The University Of Texas System | Electrical devices with electrodes on softening polymers and methods of manufacturing thereof | 
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| JPS59141222A (en) | Manufacture of semiconductor device | |
| JP2821623B2 (en) | Method for manufacturing semiconductor device | |
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| JPH03200330A (en) | Manufacture of semiconductor device | |
| JPH06120211A (en) | Manufacture of semiconductor device | |
| JPS6254427A (en) | Manufacture of semiconductor device | |
| JPS59165425A (en) | Pattern formation | |
| JPH08306871A (en) | Manufacture of dielectric capacitor | |
| JPH0536846A (en) | Manufacture of semiconductor device | |
| JPS58100434A (en) | Method for forming spacer for lift off | |
| US20050029660A1 (en) | Adhesions of structures formed from materials of poor adhesion | |
| JPH0358433A (en) | Manufacture of field effect transistor | |
| JPH0837233A (en) | Manufacture of semiconductor device | |
| JPS6056237B2 (en) | Base layer structure of plating film | |
| JPH01119028A (en) | Manufacture of semiconductor device | |
| JPH023926A (en) | Forming method of wiring | |
| JPS6193629A (en) | Manufacture of semiconductor device | |
| JPH084108B2 (en) | Method for manufacturing semiconductor device | |
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| JPS6386453A (en) | Manufacturing method of semiconductor device | |
| JPH04129226A (en) | Manufacture of semiconductor device | |
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| JPH0294439A (en) | Manufacture of semiconductor device | |
| JPS62245654A (en) | Semiconductor device and manufacture thereof | |
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