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JPS59111533U - Handbag handle attachment - Google Patents

Handbag handle attachment

Info

Publication number
JPS59111533U
JPS59111533UJP633883UJP633883UJPS59111533UJP S59111533 UJPS59111533 UJP S59111533UJP 633883 UJP633883 UJP 633883UJP 633883 UJP633883 UJP 633883UJP S59111533 UJPS59111533 UJP S59111533U
Authority
JP
Japan
Prior art keywords
fitting
handbag
handle attachment
hole
abutment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP633883U
Other languages
Japanese (ja)
Inventor
敬三 池田
Original Assignee
株式会社池田地球
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社池田地球filedCritical株式会社池田地球
Priority to JP633883UpriorityCriticalpatent/JPS59111533U/en
Publication of JPS59111533UpublicationCriticalpatent/JPS59111533U/en
Pendinglegal-statusCriticalCurrent

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Abstract

Translated fromJapanese

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Translated fromJapanese
【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本考案の使用状態を示す斜視図、第
3図及び第4図は第1図及び第2図の要部拡大横断面図
、第5図は本考案の分解斜面図。1・・・・・・手提鞄の蓋、2・・・・・・当接金具、
3・・・・・・取付部材、4・・・・・・結合手段、5
・・・・・・突起状筒部、6・・・・・・座部、7.9
・・・・・・取付孔、8・・・・・・嵌入孔、10・・
・・・・鋲着。
Figures 1 and 2 are perspective views showing the present invention in use, Figures 3 and 4 are enlarged cross-sectional views of the main parts of Figures 1 and 2, and Figure 5 is an exploded slope view of the present invention. figure. 1... Handbag lid, 2... Contact metal fittings,
3...Mounting member, 4...Coupling means, 5
...Protruding tube part, 6... Seat part, 7.9
...Mounting hole, 8...Fitting hole, 10...
...Racked.

Claims (1)

Translated fromJapanese
【実用新案登録請求の範囲】[Scope of utility model registration request]手提鞄の蓋1に重ねる当接金具2と、この当接金具2の
下面に重ねる一対の取付部材3と、前記型なり状態を結
合する結合手段4とから成る手提鞄の提手取付具におい
て、前記取付部材としては一端の突起状筒部ど他端の重
層状態の座部6とを゛  一体形成し、また座部には取
付孔7を形成し、当接金具2としては前記筒部5を嵌入
する嵌入孔8並びに取付孔9を対設し、前記嵌入孔8に
筒部5を嵌入したる後、当接金具2と取付部材3と蓋1
を鋲着10した手提鞄の提手取付具。
A handle attachment for a handbag, which comprises an abutment fitting 2 that is placed on the lid 1 of the handbag, a pair of attachment members 3 that are placed on the lower surface of the abutment fitting 2, and a connecting means 4 that connects the shaped state. As the mounting member, a protruding cylindrical portion at one end and a seat portion 6 in a multilayered state at the other end are integrally formed, and a mounting hole 7 is formed in the seat portion. A fitting hole 8 into which the fitting 5 is inserted and a mounting hole 9 are provided oppositely, and after fitting the cylindrical portion 5 into the fitting hole 8, the abutment fitting 2, the mounting member 3 and the lid 1 are fitted.
Handbag handle attachment with 10 rivets attached.
JP633883U1983-01-191983-01-19 Handbag handle attachmentPendingJPS59111533U (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP633883UJPS59111533U (en)1983-01-191983-01-19 Handbag handle attachment

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP633883UJPS59111533U (en)1983-01-191983-01-19 Handbag handle attachment

Publications (1)

Publication NumberPublication Date
JPS59111533Utrue JPS59111533U (en)1984-07-27

Family

ID=30137896

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP633883UPendingJPS59111533U (en)1983-01-191983-01-19 Handbag handle attachment

Country Status (1)

CountryLink
JP (1)JPS59111533U (en)

Cited By (33)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US6868476B2 (en)2001-08-272005-03-15Intel CorporationSoftware controlled content addressable memory in a general purpose execution datapath
US6876561B2 (en)1999-12-282005-04-05Intel CorporationScratchpad memory
US6895457B2 (en)1999-12-282005-05-17Intel CorporationBus interface with a first-in-first-out memory
US6934951B2 (en)2002-01-172005-08-23Intel CorporationParallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US6941438B2 (en)2003-01-102005-09-06Intel CorporationMemory interleaving
US6976095B1 (en)1999-12-302005-12-13Intel CorporationPort blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US6983350B1 (en)1999-08-312006-01-03Intel CorporationSDRAM controller for parallel processor architecture
US7020871B2 (en)2000-12-212006-03-28Intel CorporationBreakpoint method for parallel hardware threads in multithreaded processor
US7107413B2 (en)2001-12-172006-09-12Intel CorporationWrite queue descriptor count instruction for high speed queuing
US7126952B2 (en)2001-09-282006-10-24Intel CorporationMultiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7149226B2 (en)2002-02-012006-12-12Intel CorporationProcessing data packets
US7158964B2 (en)2001-12-122007-01-02Intel CorporationQueue management
US7181573B2 (en)2002-01-072007-02-20Intel CorporationQueue array caching in network devices
US7181594B2 (en)2002-01-252007-02-20Intel CorporationContext pipelines
US7191321B2 (en)1999-08-312007-03-13Intel CorporationMicroengine for parallel processor architecture
US7216204B2 (en)2001-08-272007-05-08Intel CorporationMechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en)2001-08-272007-05-29Intel CorporationMultiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7269179B2 (en)2001-12-182007-09-11Intel CorporationControl mechanisms for enqueue and dequeue operations in a pipelined network processor
US7305500B2 (en)1999-08-312007-12-04Intel CorporationSram controller for parallel processor architecture including a read queue and an order queue for handling requests
US7328289B2 (en)1999-12-302008-02-05Intel CorporationCommunication between processors
US7337275B2 (en)2002-08-132008-02-26Intel CorporationFree list and ring data structure management
US7352769B2 (en)2002-09-122008-04-01Intel CorporationMultiple calendar schedule reservation structure and method
US7421572B1 (en)1999-09-012008-09-02Intel CorporationBranch instruction for processor with branching dependent on a specified bit in a register
US7433307B2 (en)2002-11-052008-10-07Intel CorporationFlow control in a network environment
US7434221B2 (en)1999-12-302008-10-07Intel CorporationMulti-threaded sequenced receive for fast network port stream of packets
US7437724B2 (en)2002-04-032008-10-14Intel CorporationRegisters for data transfers
US7443836B2 (en)2003-06-162008-10-28Intel CorporationProcessing a data packet
US7471688B2 (en)2002-06-182008-12-30Intel CorporationScheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7480706B1 (en)1999-12-302009-01-20Intel CorporationMulti-threaded round-robin receive for fast network port
US7487505B2 (en)2001-08-272009-02-03Intel CorporationMultithreaded microprocessor with register allocation based on number of active threads
US7610451B2 (en)2002-01-252009-10-27Intel CorporationData transfer mechanism using unidirectional pull bus and push bus
US7620702B1 (en)1999-12-282009-11-17Intel CorporationProviding real-time control data for a network processor
US9128818B2 (en)1999-12-272015-09-08Intel CorporationMemory mapping in a processor having multiple programmable units

Citations (1)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS5648821B2 (en)*1978-02-081981-11-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS5648821B2 (en)*1978-02-081981-11-18

Cited By (37)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US7305500B2 (en)1999-08-312007-12-04Intel CorporationSram controller for parallel processor architecture including a read queue and an order queue for handling requests
US7191321B2 (en)1999-08-312007-03-13Intel CorporationMicroengine for parallel processor architecture
US7424579B2 (en)1999-08-312008-09-09Intel CorporationMemory controller for processor having multiple multithreaded programmable units
US6983350B1 (en)1999-08-312006-01-03Intel CorporationSDRAM controller for parallel processor architecture
US7421572B1 (en)1999-09-012008-09-02Intel CorporationBranch instruction for processor with branching dependent on a specified bit in a register
US9128818B2 (en)1999-12-272015-09-08Intel CorporationMemory mapping in a processor having multiple programmable units
US7620702B1 (en)1999-12-282009-11-17Intel CorporationProviding real-time control data for a network processor
US6876561B2 (en)1999-12-282005-04-05Intel CorporationScratchpad memory
US6895457B2 (en)1999-12-282005-05-17Intel CorporationBus interface with a first-in-first-out memory
US7480706B1 (en)1999-12-302009-01-20Intel CorporationMulti-threaded round-robin receive for fast network port
US7328289B2 (en)1999-12-302008-02-05Intel CorporationCommunication between processors
US6976095B1 (en)1999-12-302005-12-13Intel CorporationPort blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US7434221B2 (en)1999-12-302008-10-07Intel CorporationMulti-threaded sequenced receive for fast network port stream of packets
US7020871B2 (en)2000-12-212006-03-28Intel CorporationBreakpoint method for parallel hardware threads in multithreaded processor
US7487505B2 (en)2001-08-272009-02-03Intel CorporationMultithreaded microprocessor with register allocation based on number of active threads
US7216204B2 (en)2001-08-272007-05-08Intel CorporationMechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en)2001-08-272007-05-29Intel CorporationMultiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7246197B2 (en)2001-08-272007-07-17Intel CorporationSoftware controlled content addressable memory in a general purpose execution datapath
US6868476B2 (en)2001-08-272005-03-15Intel CorporationSoftware controlled content addressable memory in a general purpose execution datapath
US7126952B2 (en)2001-09-282006-10-24Intel CorporationMultiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7158964B2 (en)2001-12-122007-01-02Intel CorporationQueue management
US7107413B2 (en)2001-12-172006-09-12Intel CorporationWrite queue descriptor count instruction for high speed queuing
US7269179B2 (en)2001-12-182007-09-11Intel CorporationControl mechanisms for enqueue and dequeue operations in a pipelined network processor
US7181573B2 (en)2002-01-072007-02-20Intel CorporationQueue array caching in network devices
US7302549B2 (en)2002-01-172007-11-27Intel CorporationProcessing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access
US6934951B2 (en)2002-01-172005-08-23Intel CorporationParallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7181594B2 (en)2002-01-252007-02-20Intel CorporationContext pipelines
US7610451B2 (en)2002-01-252009-10-27Intel CorporationData transfer mechanism using unidirectional pull bus and push bus
US7149226B2 (en)2002-02-012006-12-12Intel CorporationProcessing data packets
US7437724B2 (en)2002-04-032008-10-14Intel CorporationRegisters for data transfers
US7471688B2 (en)2002-06-182008-12-30Intel CorporationScheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7337275B2 (en)2002-08-132008-02-26Intel CorporationFree list and ring data structure management
US7352769B2 (en)2002-09-122008-04-01Intel CorporationMultiple calendar schedule reservation structure and method
US7433307B2 (en)2002-11-052008-10-07Intel CorporationFlow control in a network environment
US7418571B2 (en)2003-01-102008-08-26Intel CorporationMemory interleaving
US6941438B2 (en)2003-01-102005-09-06Intel CorporationMemory interleaving
US7443836B2 (en)2003-06-162008-10-28Intel CorporationProcessing a data packet

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