【発明の詳細な説明】本発明は、半導体素子等を収容する電子部品パッケージ
に関し、更に詳しく框し電子部品パッケージから導出す
るリード端子に、ロジウムを下地として金めつきを施し
た構造の電子部品パッケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic component package for accommodating a semiconductor element, etc., and more particularly to an electronic component having a structure in which lead terminals led out from a frame electronic component package are gold plated with rhodium as a base. It's about packaging.
セラミックパッケージの場合通常メタライジングパター
ン向上にニッケルめっきが施されているがこの場合、パ
ッケージングの際４５０℃、５分の加熱に耐えるＫは金
めつきとして最低１．５μｍ程度のめっき厚が必要であ
る。In the case of ceramic packages, nickel plating is usually applied to improve the metallizing pattern, but in this case, K, which can withstand heating at 450°C for 5 minutes during packaging, requires a plating thickness of at least 1.5 μm as gold plating. It is.
半導体用のパッケージにおいて金めつきが使用されてい
る場合、この厚みを最少にとどめることがコスト上のｉ
ｗ問題である。この目的から金めつき厚を１９薄くして
同等の特性を得る技術が求められる。本発明に、金めり
き厚を従来の１／３以下にすることができる構造の電子
部品パッケージを提供するものである。When gold plating is used in semiconductor packages, it is important to keep this thickness to a minimum for cost reasons.
This is a w problem. For this purpose, a technique is required to obtain equivalent characteristics by reducing the gold plating thickness by 19 mm. The present invention provides an electronic component package having a structure in which the gold plating thickness can be reduced to one-third or less of the conventional thickness.
この目的を達成するため、本発明では金属面上に金めっ
き′に２１１！ｉシた電子部品パッケージにおいて金め
つきの下地層としてロジウム層が形成されてなることｔ
特徴とする金めっきされた電子部品パッケージとする。To achieve this objective, the present invention provides gold plating on the metal surface with 211! A rhodium layer is formed as a base layer for gold plating in an electronic component package.
It features a gold-plated electronic component package.
金めつきの下地としてロジウムめっきを行なうことにＬ
り、ロジウムが金と金属間化合物を作りにくいこと、ま
た、鉄、ニッケル等の拡散のバリアーとしても有効に働
くことおよびロジウム自体が酸化しにくいこと等の特性
により、金めつき下地として使用すると半導体パッケー
ジの場合、４５０℃、５公租度の加熱試験が行なわれる
が、従来必要とされｆｃｌ、５μｍ稈度の厚さを約０．
５μｍ穆度まで低下させることができる。L decided to perform rhodium plating as a base for gold plating.
Rhodium is difficult to form intermetallic compounds with gold, works effectively as a barrier to diffusion of iron, nickel, etc., and rhodium itself is difficult to oxidize. In the case of semiconductor packages, a heating test of 450° C. and 5 degrees of tolerance is performed, but conventionally required fcl, 5 μm thickness and approximately 0.
It is possible to reduce the degree of slenderness to 5 μm.
金はダイボンディング性、ワイヤーボンディング性、ハ
ンダ付は性、耐食性、耐熱性＠Ｃすぐれているため高価
であるにもかか°わらず各種の電子部品に金めっきとし
て広く使用されている。しかしコストダウンの要請が強
い今日では金から銀への切り換え勢が行なわれているが
、その特性止金を必要する製品も依然として多い、そこ
で金の部分めっき化、薄めつき化が進められたわけであ
るが半導体パッケージ時の加熱条件が過酷であるため薄
めつき化すると下地のニッケル、鉄、銅等が金中に拡散
する結果加熱変色を起こすことになる。Gold has excellent die bonding properties, wire bonding properties, soldering properties, corrosion resistance, and heat resistance @C, so it is widely used as gold plating for various electronic parts, despite being expensive. However, in today's world where there is a strong demand for cost reduction, people are switching from gold to silver, but there are still many products that require this characteristic clasp, which is why partial plating and thinning of gold have been promoted. However, since the heating conditions during semiconductor packaging are harsh, if the metal is thinned, the underlying nickel, iron, copper, etc. will diffuse into the gold, resulting in heat discoloration.
１％にセラミックパッケージのメタライズ面は凹凸がｈ
す緻密質にできないため金めつきのピンホールを通して
の下地の変質が起こりやすく耐熱変色チップ剥離、ボン
ディング不良、金／スズリッド付は不良等の不良が発生
し十丁くなる。The metallized surface of the ceramic package has irregularities at 1%.
Since it cannot be made dense, it is easy to cause deterioration of the base through the pinholes of the gold plating, resulting in defects such as peeling of heat-resistant discoloration chips, poor bonding, and defects with gold/tin lids.
従って、やむｔ得ず前記の通り最低でも１．５μｍ穆度
の金めつき１施しているのが現状である。そこで薄い金
め−）き層でも性能劣化が起きない電子部品パッケージ
について鋭意検討した結果、金めりきの下地として酸化
が起きにり（、金属の拡散バリアーとして優れ、かつ金
と金属間化合物を生成しにくい金属めつきを施せば良い
ことを見出し本発明を完成した。すなわち本発明の要旨
は金属面上和会めっきが施された電子部品において金め
つきの下地としてロジウムめっきを施すことｔ−特徴り
する金めっきされた電子部品パッケージにある。仁の方
法を適用できる電子部品パッケージとしては鉄−ニッケ
ル合金、銅合金等の材料１９なるプラスチック封止用り
−ドフレーム、セラミック基板表面をタングステｙ、モ
リブデン等の材料でメタライニングしたセラミックパッ
ケージ、ハーメチックシールしたキャン・タイプのパッ
ケージ等がある。以下に本発明１−＊膣例に従い説明す
る。Therefore, the current situation is that gold plating with a purity of at least 1.5 μm is applied as described above. As a result of intensive research into electronic component packages that would not cause performance deterioration even with a thin gold plating layer, we found that the base of the gold plating layer is highly oxidized (as a base for the gold plating layer), is excellent as a diffusion barrier for metals, and is highly effective for preventing gold and intermetallic compounds. The present invention was completed by discovering that it is sufficient to apply metal plating that is difficult to form.That is, the gist of the present invention is to apply rhodium plating as a base for gold plating on electronic components that have been plated on metal surfaces. Electronic component packages to which this method can be applied include plastic encapsulation frames made of materials such as iron-nickel alloys and copper alloys, and tungsten plated ceramic substrate surfaces. There are ceramic packages metal-lined with materials such as Y, molybdenum, and hermetically sealed can-type packages.Hereinafter, the present invention will be explained according to the example of the present invention 1-*Vagina.
実施例１焼結後のセラずツクパッケージのメタライズ面にニッケ
ルめりＩ管行１い外鄭導出用リードを猟付けし九後ワッ
ト浴に！Ｊ）２μｍのニッケルめりきｖｍす、これに金
ストライクめっき０．１＃ｍを行い、ｏ、ｓｓｍのロジ
ウムめっきを施し、さら＃ＣＯ，！ＳｊＩｍの金めつき
１行ない′、種々の特性試験を行った。ロジウム及び金
めつき液に市販品（ＥＥＪＡ＃ ローデックスお工び
テンペレックス４０１）を使用した。Example 1 After sintering, a nickel-plated lead for leading out the outside of the I tube is attached to the metallized surface of the ceramic package, and it is then used for a Watt bath! J) 2 μm nickel plated vm, gold strike plating 0.1#m, o, ssm rhodium plating, and #CO,! After one gold plating of SjIm, various characteristic tests were conducted. Commercially available products (EEJA #Rhodex Temperex 401) were used as rhodium and gold plating solutions.
グイ付けに４３０℃で窒素雰囲気中においてダイ【スク
ライプしながら行い、シア〒テスト（接着面を刃物で強
制的Ｋにがし、接着状ｍｔみる試験）を行い金／シリコ
／共晶で９０−以上濡れているものｔ良好とした。For bonding, a die test was performed at 430°C in a nitrogen atmosphere, and a shear test (a test in which the bonded surface was forcibly peeled off with a knife and the bonded state was observed) was performed with gold/silico/eutectic. Items that were more than 100% wet were considered to be good.
ワづヤーポンディングは４５０℃、５分加熱したサンプ
ルにアルミニウム線を用いた超音波ボンディングを行な
い、２００℃、４８時間の加熱エージングを行ないその
良否を判定した−いずれの場合も全く異状はみとめられ
ず充分良好な結果を与えた。For wire bonding, ultrasonic bonding was performed using aluminum wire on a sample heated at 450°C for 5 minutes, and the quality was determined by heat aging at 200°C for 48 hours - no abnormalities were observed in either case. It gave very good results.
ロジウムめりき厚に実用上０．１／Ｊｍ程度でも充分で
あるが、１．０Ａｍ以上にロジウム自体が高価であるた
め、実用面では好ましくない、０．３μｍ以下の７ラク
シ工程度で十分である。ｔｆｔロジウムと組み合わせて
使用する金Ｍはニッケル以外に例えば銀、銅、コバルト
等でも充分機能することはいうまでもない。A rhodium plating thickness of about 0.1/Jm is sufficient for practical purposes, but since rhodium itself is expensive if it is more than 1.0 Am, it is not preferable from a practical point of view. be. It goes without saying that the gold M used in combination with tft rhodium can function satisfactorily with silver, copper, cobalt, etc. in addition to nickel.
以上述べた工うＫごく薄いロジウム層會金めつきの下地
に用いることにＬ９金めりき厚を従来の１／３程度に容
易に低減させることができ、高品質で低価格のパッケー
ジの製造が可能となった。By using the extremely thin rhodium layer described above as the base for gold plating, the thickness of the L9 gold plating can be easily reduced to about 1/3 of the conventional thickness, making it possible to manufacture high-quality, low-cost packages. It has become possible.
以上本発明會セラミックパッケージの実施例にて詳述し
たが、以下の態様でも行なう仁とができる。Although the embodiments of the ceramic package of the present invention have been described in detail above, the present invention can also be carried out in the following embodiments.
（１） 部分金めっきリードフレームの金めつき下地
として、金めつきと同じ位置にジェットめっきＫＬ９０
ジウムめっきを行なう。(1) Jet plating KL90 in the same position as the gold plating as the gold plating base of the selective gold plating lead frame.
Perform dium plating.
（２）（１）と同様にハーメチックシールの部分金めっ
き下地として使用する。(2) Similar to (1), use as a base for partial gold plating of hermetic seals.
（３） バレルめっきＫＬる全体会めうきにも下地め
っきとして使用する。(3) Barrel plating It is also used as a base plating for general meetings.
本発明ＫＬれば、金めりきされた電子部品パッケージに
訃いて金めつき厚を従来の一般的な１．５μｍから約０
．５μｍＫｔで低下させることができ安価な製品管従来
と同等の機能１備えたものとして製造できる。With the KL of the present invention, it is possible to reduce the gold plating thickness from the conventional general 1.5 μm to approximately 0 μm on a gold-plated electronic component package.
．． The Kt can be lowered to 5 μm and can be manufactured as an inexpensive product with the same functions as conventional products.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56102743AJPS584955A (en) | 1981-06-30 | 1981-06-30 | Package of gold-plated electronic parts |
| GB08217956AGB2103420B (en) | 1981-06-30 | 1982-06-21 | Gold-plated package for semiconductor devices |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56102743AJPS584955A (en) | 1981-06-30 | 1981-06-30 | Package of gold-plated electronic parts |
| Publication Number | Publication Date |
|---|---|
| JPS584955Atrue JPS584955A (en) | 1983-01-12 |
| JPS6243343B2 JPS6243343B2 (en) | 1987-09-12 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56102743AGrantedJPS584955A (en) | 1981-06-30 | 1981-06-30 | Package of gold-plated electronic parts |
| Country | Link |
|---|---|
| JP (1) | JPS584955A (en) |
| GB (1) | GB2103420B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961155A (en)* | 1982-09-30 | 1984-04-07 | Fujitsu Ltd | semiconductor equipment |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4783722A (en)* | 1985-07-16 | 1988-11-08 | Nippon Telegraph And Telephone Corporation | Interboard connection terminal and method of manufacturing the same |
| US4701573A (en)* | 1985-09-26 | 1987-10-20 | Itt Gallium Arsenide Technology Center | Semiconductor chip housing |
| FR2610451B1 (en)* | 1987-01-30 | 1989-04-21 | Radiotechnique Compelec | OPTO-ELECTRONIC DEVICE COMPRISING AT LEAST ONE COMPONENT MOUNTED ON A SUPPORT |
| DE3704200A1 (en)* | 1987-02-11 | 1988-08-25 | Bbc Brown Boveri & Cie | METHOD FOR PRODUCING A CONNECTION BETWEEN A BONDED WIRE AND A CONTACT AREA IN HYBRID THICK-LAYER CIRCUITS |
| CA2092165C (en)* | 1992-03-23 | 2001-05-15 | Tuyosi Nagano | Chip carrier for optical device |
| JPH0799368A (en)* | 1993-09-29 | 1995-04-11 | Mitsubishi Electric Corp | Optical semiconductor device |
| FR2713401B1 (en)* | 1993-09-29 | 1997-01-17 | Mitsubishi Electric Corp | Optical semiconductor device. |
| JP2606115B2 (en)* | 1993-12-27 | 1997-04-30 | 日本電気株式会社 | Element bonding pad for semiconductor mounting board |
| DE102008021435A1 (en)* | 2008-04-29 | 2009-11-19 | Schott Ag | Housing for LEDs with high performance |
| CN119297161A (en)* | 2024-11-18 | 2025-01-10 | 中国振华集团永光电子有限公司（国营第八七三厂） | A SMD power hybrid integrated circuit module packaging method and packaging structure thereof |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3609472A (en)* | 1969-05-21 | 1971-09-28 | Trw Semiconductors Inc | High-temperature semiconductor and method of fabrication |
| JPS4829186A (en)* | 1971-08-18 | 1973-04-18 |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3609472A (en)* | 1969-05-21 | 1971-09-28 | Trw Semiconductors Inc | High-temperature semiconductor and method of fabrication |
| JPS4829186A (en)* | 1971-08-18 | 1973-04-18 |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961155A (en)* | 1982-09-30 | 1984-04-07 | Fujitsu Ltd | semiconductor equipment |
| Publication number | Publication date |
|---|---|
| GB2103420A (en) | 1983-02-16 |
| JPS6243343B2 (en) | 1987-09-12 |
| GB2103420B (en) | 1986-01-29 |
| Publication | Publication Date | Title |
|---|---|---|
| US4675243A (en) | Ceramic package for semiconductor devices | |
| US6664136B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6013078B2 (en) | Gold-plated electronic components and their manufacturing method | |
| JPH04115558A (en) | Lead frame for semiconductor device | |
| JPH09275182A (en) | Lead frame for semiconductor device | |
| JPS584955A (en) | Package of gold-plated electronic parts | |
| JPS5948546B2 (en) | Metal strip for lead frame and its manufacturing method | |
| US6853056B2 (en) | Semiconductor device having a base metal lead frame | |
| US3982908A (en) | Nickel-gold-cobalt contact for silicon devices | |
| US4065588A (en) | Method of making gold-cobalt contact for silicon devices | |
| JPH01257356A (en) | Lead frame for semiconductor | |
| EP0264128A2 (en) | Jumper chip for semiconductor devices | |
| US4765528A (en) | Plating process for an electronic part | |
| JPS5933851A (en) | Airtightly sealed semiconductor container | |
| JP2000068396A (en) | Hermetic seal cover | |
| JP3444981B2 (en) | Lead frame and lead frame material | |
| JPS628532A (en) | Gold-plated electronic component package | |
| JPS6353287A (en) | Ag coated conductor | |
| JPS6142941A (en) | Lead frame for semiconductor | |
| JP2721259B2 (en) | Wire bonding method and copper-based lead frame used therefor | |
| JPS639957A (en) | Semiconductor lead frame | |
| JPS628533A (en) | Gold-plated electronic component package | |
| JPS588586B2 (en) | Sealing method for semiconductor devices | |
| JPS61195991A (en) | Manufacturing method of electronic components | |
| JPH02174253A (en) | Electronic parts package with rhenium layer at metal part |