【発明の詳細な説明】本発明は、条件処理を含む判断処理を高速に実用できる
、データ処理回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing circuit that can perform judgment processing including conditional processing at high speed.
データ処理装置においては、入力データに対して内部に
蓄えられている条件によって判断を行なって、判断結果
を出力として得るというような、条件処理を含む判断処
理が必要な場合がある。従来、このような条件処理を含
む判断処理を実行するデータ処理方式の実現手法として
杜、計数回路の内容に処理内容をそれぞれ対応させ、計
数回路の出力によって処理回路における処理内容を指定
するようにしそ、計数回路が計数するごとに処理内容を
変化させて順次データを処理し、またはデータにより判
断した内容を出力していた。In a data processing device, there are cases where judgment processing including conditional processing is necessary, such as making a judgment on input data based on internally stored conditions and obtaining the judgment result as an output. Conventionally, as a method for realizing a data processing method that executes judgment processing including such conditional processing, the processing contents are made to correspond to the contents of the counting circuit, and the processing contents in the processing circuit are specified by the output of the counting circuit. However, each time the counting circuit counts, the processing content is changed to sequentially process the data, or the content determined based on the data is output.
第１１祉従来の条件処理を含む判断処理を実行するデー
タ処理回路の一例を示している。同−図において１は計
数回路、２は入力選択回路、３は処理回路である。計数
回路１は、計数回路出力０１によって、処理回路３に対
して処理内容を指定する。同時に入力選択回路２は、計
数回路出力０１によって、入力データ０４〜０６ から
処理回路３における処理内容に対応した入力データを選
択して、選択回路出力０２を生じ、処理回路３に入力す
る。11. An example of a data processing circuit that executes judgment processing including conventional conditional processing is shown. In the figure, 1 is a counting circuit, 2 is an input selection circuit, and 3 is a processing circuit. The counting circuit 1 specifies processing content to the processing circuit 3 using the counting circuit output 01. At the same time, the input selection circuit 2 selects the input data corresponding to the processing content in the processing circuit 3 from among the input data 04 to 06 using the counting circuit output 01, generates the selection circuit output 02, and inputs it to the processing circuit 3.
処理回路３における処理結果により、処理回路出力０３
を生じる。計数回路１は１回の処理が終了するごとに計
数内容を変更し、これによって計数回路出力０１が変化
して、処理内容の変更が行われる。According to the processing result in the processing circuit 3, the processing circuit output 03
occurs. The counting circuit 1 changes the counting content each time one process is completed, and thereby the counting circuit output 01 changes, and the processing content is changed.
従来の条件処理を含む判断処理を実行するデータ処理回
路においては、このような方法で処理を行なっていたた
め、ある定められた順序でしか処理が行われず、処理内
容を最適な順序で行うような複雑な処理は不可能である
ため、必要な処理内容のみを高速に行うような手法をと
ることはできなかった。Conventional data processing circuits that perform judgment processing, including conditional processing, perform processing in this way, so processing is performed only in a certain order, and it is difficult to perform processing in the optimal order. Since complex processing is not possible, it has not been possible to use a method that performs only the necessary processing at high speed.
本発明は、このような従来技術の欠点を除去しようとす
るものであって、その目的は最適な順序で処理内容を実
行することによシ、条件処理を含む判断処理を高速に行
うことができるデータ処理回路を提供することにある。The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to execute processing contents in an optimal order so that judgment processing including conditional processing can be performed at high speed. The objective is to provide a data processing circuit that can.
本発明のデータ処理回路は、読出し用メモリ（以下ＲＯ
Ｍという）とラッチ回路とによって順序°回路を構成し
、処理回路における処理結果をＲＯＭのアドレス入力に
加えることによって、最適な順序で処理を行えるように
したものである。The data processing circuit of the present invention has a read memory (hereinafter referred to as RO).
A sequential circuit is formed by a latch circuit (referred to as M) and a latch circuit, and by adding the processing results in the processing circuit to the address input of the ROM, processing can be performed in the optimal order.
以下、実施例について本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to Examples.
第２１紘本発明のデータ処理回路の一実施例の構成を示
している。同図において、第１図におけると同じ部分は
同じ番号で示されており、４はＲＯＭ、５はラッチ回路
である。21 shows the configuration of an embodiment of the data processing circuit of the present invention. In the same figure, the same parts as in FIG. 1 are indicated by the same numbers, 4 is a ROM, and 5 is a latch circuit.
第２図において、ラッチ回路５はラッチ回路出力０８を
発生して処理回路３に入力する。これによって処理回路
５における処理内容が指定される。In FIG. 2, the latch circuit 5 generates a latch circuit output 08 and inputs it to the processing circuit 3. This specifies the processing content in the processing circuit 5.
ラッチ回路出力０８は同時に入力選択回路２にも入力さ
れ、これによって入力選択回路２は、入力データ０４〜
０６ から、処理回路５における処理内容に対応した
データを選択して、選択回路出力０２を生じる０選択回
路出力０２は処理回路３に入力され、これによって処理
回路５において処理が行われて、処理回路出力ｏ３を生
じる。処理回路出力０３は、ラッチ回路出力０８ととも
にＲＯＭ４ヘアドレス入力として加えられ、これによっ
てＲＯＭ４からＲＯＭ出力０７を生じる。’ＲＯＭ出力
ｏ７はラッチ回路５に入力され、・ラッチ回路５はこれ
を一時記憶してラッチ回路出力０８を生じる。ラッチ回
路出力０８は、前述のように入力選択回路２における入
力データの選択と処理回路３における処理内容とを指定
する。The latch circuit output 08 is also input to the input selection circuit 2 at the same time, so that the input selection circuit 2 selects the input data 04 to
06, the data corresponding to the processing content in the processing circuit 5 is selected to produce the selection circuit output 02. The 0 selection circuit output 02 is input to the processing circuit 3, and is processed in the processing circuit 5. produces a circuit output o3. Processing circuit output 03 is applied as an address input to ROM4 along with latch circuit output 08, thereby producing ROM output 07 from ROM4. 'The ROM output o7 is input to the latch circuit 5, and the latch circuit 5 temporarily stores it and produces the latch circuit output 08. The latch circuit output 08 specifies the selection of input data in the input selection circuit 2 and the processing content in the processing circuit 3, as described above.
このように本発明のデータ処理回路によれば、現在の処
理内容とその処理結果とをＲＯＭのアドレス入力とし【
加えることによって、次に処理すべき内容がＲＯＭ出力
として決定される。従って、処理順序ｌｌＲＯＭのプロ
グラミングによって容易に決定される０本発明のデータ
処理回路において杜、このような手法によって、所要の
処理内容を最適な順序で行うことができるので、処理を
高速化することが可能となる。As described above, according to the data processing circuit of the present invention, the current processing contents and the processing results are input to the address of the ROM.
By adding this, the content to be processed next is determined as the ROM output. Therefore, in the data processing circuit of the present invention, the processing order can be easily determined by programming the ROM, and by using such a method, the required processing contents can be performed in the optimal order, so that the processing speed can be increased. becomes possible.
以上説明したように本発明のデータ処理回路によれば、
次に処理すべき内容が現在の処理内容とその処理結果と
によって決定されるため、最適な順序で必要な処理を行
うことができ、従って高速な処理が可能になって、極め
て効果的である。As explained above, according to the data processing circuit of the present invention,
Since the content to be processed next is determined by the current processing content and its processing results, the necessary processing can be performed in the optimal order, making high-speed processing possible and extremely effective. .
第１図は従来のデータ処理回路の構成を示すブロック図
、第２図は本発明のデータ処理回路の一実施例の構成を
示すブロック図である。１・・・計数回路、２・・・入力選択回路、５・・・処
理回路、４・・・読出し用メモリ（ＲＯＭ）、５・・・
ラッチ回路、ロー ・・・計数回路出力、０２・・・選
択回路出力、０３・・・処理回路出力、０４〜０６
・・・入力データ、０７・・・絖出し用メモリ（ＲＯＭ
）出力、０８・・・ラッチ回路出力特許出願人富士通株式会社FIG. 1 is a block diagram showing the configuration of a conventional data processing circuit, and FIG. 2 is a block diagram showing the configuration of an embodiment of the data processing circuit of the present invention. DESCRIPTION OF SYMBOLS 1... Counting circuit, 2... Input selection circuit, 5... Processing circuit, 4... Reading memory (ROM), 5...
Latch circuit, low... Counting circuit output, 02... Selection circuit output, 03... Processing circuit output, 04-06
...Input data, 07...Memory for threading (ROM)
) output, 08...Latch circuit output Patent applicant Fujitsu Limited
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10258281AJPS584448A (en) | 1981-06-30 | 1981-06-30 | Data processing circuit |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10258281AJPS584448A (en) | 1981-06-30 | 1981-06-30 | Data processing circuit |
| Publication Number | Publication Date |
|---|---|
| JPS584448Atrue JPS584448A (en) | 1983-01-11 |
| JPS6229817B2 JPS6229817B2 (en) | 1987-06-29 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10258281AGrantedJPS584448A (en) | 1981-06-30 | 1981-06-30 | Data processing circuit |
| Country | Link |
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| JP (1) | JPS584448A (en) |
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