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JPS5821347A - Flat type semiconductor device - Google Patents

Flat type semiconductor device

Info

Publication number
JPS5821347A
JPS5821347AJP56118744AJP11874481AJPS5821347AJP S5821347 AJPS5821347 AJP S5821347AJP 56118744 AJP56118744 AJP 56118744AJP 11874481 AJP11874481 AJP 11874481AJP S5821347 AJPS5821347 AJP S5821347A
Authority
JP
Japan
Prior art keywords
pellet
contact
electrode
flat
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56118744A
Other languages
Japanese (ja)
Inventor
Yukio Igarashi
五十嵐 行雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co LtdfiledCriticalToshiba Corp
Priority to JP56118744ApriorityCriticalpatent/JPS5821347A/en
Publication of JPS5821347ApublicationCriticalpatent/JPS5821347A/en
Pendinglegal-statusCriticalCurrent

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Classifications

Landscapes

Abstract

PURPOSE:To contrive the reduction of pressure impressed on a pellet and prevent surface damages, by forming the entire area of one surface of an electrode post of a flat package contacted on a semiconductor pellet larger than the contact area on a cooling fin. CONSTITUTION:The part wherein electrode posts 13, 14 contact the cooling fin is reduced more than the flat surface contacted on the pellet 11 and mechanically and firmly installed by less total weighting. Further, the stepwise difference h 40mu is provided, and a good thermal conductive grease is applied resulting in the prevention-of the decrease in cooling effect. In this constitution, the fine patterns on the surface of a pellet are not damaged.

Description

Translated fromJapanese

【発明の詳細な説明】この発明は半導体ペレットに加わる圧力を緩和すること
ができる平置半導体装置に関する・第1図は従来の平温
半導体装置の断面図である・図において11は半導体ペ
レy)、JJは平置容器である・ま九、11及び14は
それぞれ電極ポストであシ通常上記平屋容器12に固着
されている。15及び16社それぞれ半導体素子を冷却
する為の冷却フィンである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flat semiconductor device capable of relieving pressure applied to a semiconductor pellet. FIG. 1 is a sectional view of a conventional normal temperature semiconductor device. In the figure, 11 is a semiconductor pellet ), JJ is a flat container, and 9, 11 and 14 are electrode posts, respectively, which are usually fixed to the one-story container 12. These are cooling fins for cooling semiconductor devices manufactured by companies No. 15 and No. 16, respectively.

次に、第2図は他の従来の平綴半導体装置の断面図であ
る。第2図と第111に示される平盤半導体装置との相
違は電極−ス)J4Iiの冷却シ゛イン(図では省略)
側が−大きい事である。これは電極ポスト14と冷却フ
ィンとの電気的、熱的接触を向上させる為O第1図の改
善である。
Next, FIG. 2 is a sectional view of another conventional flat-bound semiconductor device. The difference between the flat semiconductor device shown in Fig. 2 and Fig. 111 is the electrodes).
The side is big. This is an improvement over FIG. 1 to improve electrical and thermal contact between the electrode posts 14 and the cooling fins.

一般的に従来は半導体ペレ、)1111面が平坦であル
、電極4スト14@の半導体ペレット11側及び冷却フ
(ン15,1−側のそれぞれ加圧接触す葛部分の接触面
積は#!埋同じであるか異なる場合でも許容され得る程
度の圧力(通常100〜300 #/J ) Kて加8
E接触されている。しかし、半導体素子性能の向上及び
多様化にともない第3図に示すような半導体ペレ。
Generally, in the past, the surface of the semiconductor pellet (1111) was flat, and the contact area of the part of the semiconductor pellet (11 side) of the electrode 4st 14 @ and the part of the cooling fan (15, 1- side) that was in pressure contact with each other was # !Allowable pressure (usually 100 to 300 #/J) even if the pressure is the same or different.
E is in contact. However, with the improvement and diversification of semiconductor device performance, the semiconductor chip as shown in FIG.

トのように表面が微細パターン化されるケースが増えて
いる。このため、半導体ペレット11と電極4スト11
間の加圧力が400〜800に9/d’ K tでなる
場合もあ)、半導体ペレ、トxxo@傷、電極lスト1
1面OIR形等0不具合を生じるという欠点がある。を
九、全体の加圧力を低くする事で半導体ペレット11と
電極ボス)17間の加圧力は弱くなるが、それとともに
電極Iスト13.ノ4と冷却フィン15゜1#間の単位
面積尚シの加圧力も弱(なシ、電気的抵抗の上昇及び機
械的固定力が弱くなシ素子取付けが不安定になるという
欠点がありた。
Increasingly, there are cases where surfaces are patterned into fine patterns. For this reason, the semiconductor pellet 11 and the electrode 4 stroke 11
In some cases, the pressing force between 400 and 800 is 9/d'Kt), semiconductor pellet, toxxo@wound, electrode l strike 1
One side OIR type has the disadvantage of causing zero defects. (9) By lowering the overall pressing force, the pressing force between the semiconductor pellet 11 and the electrode boss 17 becomes weaker, but at the same time, the electrode I strike 13. The unit area between No. 4 and the cooling fin 15°1 # also has a weak pressing force (there was a drawback that the electrical resistance increased and the mechanical fixing force was weak, making the element installation unstable). .

この発明は上記の点に鑑みてなされたもので、その目的
は半導体ペレットに加わる圧力を緩和することかでil
為千蓋半導体装置を提供するととKある。
This invention was made in view of the above points, and its purpose is to alleviate the pressure applied to semiconductor pellets.
K is said to provide Tamechiba semiconductor devices.

以下、図面を参照してこの発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第3図に示すように電極ポスト11゜14の冷却フィン
(図示せず)に接する部分を電極ポストJJ、J4と半
導体ペレットとが接する平面よシ小さくする。すなわち
、電極ボス)71.74と冷却フィンとの接触面を小さ
くし、単位面積当ルの加圧力を増やす事で、全加重を低
くしても機械的に強固に取付は返事が可能となる。tた
、電気的抵抗も半導体ペレット1jと電極Iスト14間
の接触面に比べて小さいので影譬度少なく性能低下には
ならない。さらに、段差(綽を40J11!度にしてお
き、その間fiK良伝熱性グリース等を塗布する事で、
冷却効果の低減を防止jることかで龜る。上記間隙は使
用するグリース類の種類によって異なるが、例として電
極ポスト13,14のペレット接触部を27−−、冷却
フィン接触部を雪O■φ(h−30*)の場合にはダ蟹
−ス無しで熱抵抗の上昇が約40−であるが、東芝シリ
コーン■製シリフーンダリスYG@111使用で5%0
上昇、信越化学工業KW製シリーーン!リスに8609
使用で8−O上昇(いずれも接触面のみの熱抵抗値)程
度であ)その効果は確認されている・次に、この発明の他O実施例を1lE5図を用いて説明
する0図に示したように、冷却フィンx5.1gと接す
るWO電極−スト13,14の径を縮小するかわルに冷
却フィンXi、1i側を小さくする事でも同じ効果が得
られる・次に1関lIhとグリース(YG6111)使
用時の熱抵抗の上昇率を第5図に示しておく。
As shown in FIG. 3, the portions of the electrode posts 11 and 14 that contact the cooling fins (not shown) are made smaller than the planes where the electrode posts JJ, J4 and the semiconductor pellet contact. In other words, by reducing the contact surface between the electrode boss (71.74) and the cooling fin and increasing the pressing force per unit area, it is possible to maintain a mechanically strong installation even when the total load is low. . In addition, since the electrical resistance is also smaller than the contact surface between the semiconductor pellet 1j and the electrode I striker 14, there is less chance of a problem and the performance will not deteriorate. In addition, by keeping the level difference (wall) at 40J11! degrees and applying fiK good heat conductive grease etc.,
It is difficult to prevent the cooling effect from decreasing. The above-mentioned gap varies depending on the type of grease used, but for example, if the pellet contact part of the electrode posts 13 and 14 is 27--, and the cooling fin contact part is snow O■φ (h-30*), -The increase in thermal resistance is about 40- without the heat resistance, but when using Toshiba Silicone's silicone dalis YG@111, it is 5% zero.
Rise, Shin-Etsu Chemical KW made Shireen! 8609 to squirrel
Its effect has been confirmed (the thermal resistance value increases only at the contact surface) by use. As shown, the same effect can be obtained by making the cooling fins Xi and 1i smaller instead of reducing the diameters of the WO electrodes 13 and 14 that are in contact with the cooling fin x5.1g. Figure 5 shows the rate of increase in thermal resistance when using grease (YG6111).

ζζで、接合部(ペレット)と冷却フィン15゜1σ間
の総合熱抵抗との関係で、この上昇率そのものが総合熱
抵抗上昇率とはならないが、許容出来得る接触面熱抵抗
上昇率を10−とすれば30〜40sの関atで許容す
ることができる。
In relation to the overall thermal resistance between the joint (pellet) and the cooling fin 15° 1σ, this rate of increase itself is not the overall thermal resistance increase rate, but the allowable contact surface thermal resistance increase rate is 10 -, a relationship of 30 to 40 seconds can be tolerated.

以上詳述しえようにこの発明によれば、半導体ペレット
に加゛わる圧力を緩和することができるので、半導体ペ
レットの表面が微細パターン化されている場合でもその
表面の損、傷を防止することがで!ゐ。
As detailed above, according to the present invention, the pressure applied to the semiconductor pellet can be alleviated, so even if the surface of the semiconductor pellet is finely patterned, damage and scratches on the surface can be prevented. It's possible! Wow.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ従来の平蓋半導体素子の断
面図、第3図はこの発明の一実施例を示す千型牛導体装
置の断面図、第4図はこの発明の他の実施例を示す平盤
半導体装置の断面図、第5図は間隙りと熱抵抗上昇率と
の関係葡示す図である。ィ、、Fj−・・半導体ペレッ)、JJ−・・平蓋容器
、111.14・・・電極4スト、15 a J #−
冷却フイ  ン ・出願人代理人  弁理士 鈴 江 武 彦第1図jI3r!!J第4図
FIGS. 1 and 2 are sectional views of a conventional flat-lid semiconductor device, FIG. 3 is a sectional view of a 100-mold conductor device showing one embodiment of the present invention, and FIG. 4 is a sectional view of another embodiment of the present invention. FIG. 5 is a sectional view of a flat semiconductor device showing an example, and is a diagram showing the relationship between the gap and the rate of increase in thermal resistance. ,,Fj-...Semiconductor pellet), JJ-...Flat lid container, 111.14...Electrode 4 stroke, 15 a J #-
Cooling fin / Applicant's representative Patent attorney Takehiko Suzue Figure 1 jI3r! ! J Figure 4

Claims (1)

Translated fromJapanese
【特許請求の範囲】[Claims](1)半導体ペレットな封入する平型容器の電極Iスト
面において、半導体ペレットと接する一表面の全面積が
冷却フィンと接する部分の面積よル大きいことを特徴と
する平型半導体装置・(2)上記電極−ス)JIfと上
記冷却フィンとの接触する部分の一部に間隙を設け、そ
の間隙に良熱伝導性物質を塗布し九ことを特徴とする特
許請求の範囲第1項記載の平置半導体装置。
(1) A flat semiconductor device characterized in that, on the electrode I strike surface of a flat container in which semiconductor pellets are enclosed, the total area of one surface in contact with the semiconductor pellet is larger than the area of the portion in contact with cooling fins. ) A gap is provided in a part of the contact portion between the electrode () JIf and the cooling fin, and a material with good thermal conductivity is applied to the gap. Flat-standing semiconductor device.
JP56118744A1981-07-291981-07-29Flat type semiconductor devicePendingJPS5821347A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP56118744AJPS5821347A (en)1981-07-291981-07-29Flat type semiconductor device

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP56118744AJPS5821347A (en)1981-07-291981-07-29Flat type semiconductor device

Publications (1)

Publication NumberPublication Date
JPS5821347Atrue JPS5821347A (en)1983-02-08

Family

ID=14743979

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP56118744APendingJPS5821347A (en)1981-07-291981-07-29Flat type semiconductor device

Country Status (1)

CountryLink
JP (1)JPS5821347A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5189509A (en)*1989-12-151993-02-23Mitsubishi Denki Kabushiki KaishaSemiconductor device and electrode block for the same
US6225695B1 (en)*1997-06-052001-05-01Lsi Logic CorporationGrooved semiconductor die for flip-chip heat sink attachment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5189509A (en)*1989-12-151993-02-23Mitsubishi Denki Kabushiki KaishaSemiconductor device and electrode block for the same
US6225695B1 (en)*1997-06-052001-05-01Lsi Logic CorporationGrooved semiconductor die for flip-chip heat sink attachment

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