【発明の詳細な説明】〔発明の技術分野〕本発明は、浮遊ｆｆ−）と制御デートを有する、電気的
に書き換え可能な不揮発性半導体メモリ装置に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to electrically rewritable non-volatile semiconductor memory devices having floating ff-) and control dates.
匠米、浮遊ｆ−）を有する不揮発性メモリは４１図に示
す如く、例えばＰ型シリコン基板１にドレイン２、ソー
ス３を設け、チャネル領域上に第１ダート絶蘇膜４１を
介して浮遊ケ゛−ト５を設け、更にその上に第２））′
−）絶縁膜４２を介して制御ゲート６を設けて構成され
る。電気的に書き換えを可能とするため、浮遊ｙ−ト５
は薄いｒ−）絶縁膜４１＋４１を介して基板１および制
御ゲート６と対向する様構成され、絶縁膜のトンネル電
流を用いて電荷の授受を行うことにより、情報の省き換
えが行なわれる。As shown in FIG. 41, a nonvolatile memory having a floating f-) is, for example, provided with a drain 2 and a source 3 on a P-type silicon substrate 1, and a floating cell is placed on a channel region via a first dirt-reducing film 41. - 5), and a second))'
-) The control gate 6 is provided with an insulating film 42 in between. To enable electrical rewriting, the floating Y-T5
is configured to face the substrate 1 and the control gate 6 via a thin r-) insulating film 41+41, and information is replaced by transferring charges using a tunnel current of the insulating film.
ＩＪＬＩち、第２図に示す如く、浮遊ｒ−）、５に負の
電荷が蓄積されている状態（以下書込み状態と呼ぶ）で
は、♂ｄ憶素子を選択的νＣ枕み出−丈際制御ケ゛−ト
ロに印加されるｒ〜ト電位ｖＧ２よりもしきい値が動く
、仔遊ｒ−ト５に畦竹の蓄積さｔｒ、でいない、あるい
は止の電荷の蓄積されている状態（以下消去状態と叶ぶ
）では、記憶素子が絖み出し時に非速択のとき制御ｒ−
トロに印加される電圧Ｖ。１とＶ。、の間にしきい値が
変化するように設計される。夾＃ＡＫは、”０１と■。As shown in FIG. 2, in a state in which negative charges are accumulated in the floating r-) and 5 (hereinafter referred to as the write state), the ♂d storage element is selectively controlled by νC. A state in which the threshold voltage moves more than the r~t potential vG2 applied to the keitor, and there is no or no charge accumulated in the child r~t 5 (hereinafter referred to as an erased state) ), the control r-
Voltage V applied to Toro. 1 and V. , the threshold value is designed to change between . #AK is “01” and ■.
。の間にしきい値が入るよう書き換え時に制御するのＦｉ
技術的に困難なので、第１図に示した如く浮遊ｒ−ト５
はチャネル領域を部分的におおい、制御ｒ−）６の一部
をチャネル領域の残りの部分に延在させ、この部分のし
きい値をｖａｔとｖＧ！の間に設定する事により、上記
の目的を達成している。ところで、書き換えの観点から
は消去状態から誉込み状態への変化、あるいは逆の変化
を起こすプログラム電圧、及び時間は等しい事が望まし
いので、浮遊ｅ−） ５に電荷の蓄積されていない時の
しきい値はほぼ■。、に等しい事が望ましい。従って、
Ｍ１図において、浮ａデート５によって制御さＪするチ
ャネル部のしきいＭＬは■。、にほぼ等しく、市ｉ鉤？
−） ｂの延在部によって制（財）されるチャネル部の
しきい値はＶ。１〜 ■ｏ、の間ＶＣあることが４まし
い。. Fi is controlled during rewriting so that the threshold value falls between
Since it is technically difficult, a floating r-tower 5 is used as shown in Figure 1.
partially covers the channel region and extends a portion of the control r−)6 into the remaining portion of the channel region, setting the thresholds of this portion to vat and vG! The above purpose is achieved by setting between By the way, from the point of view of rewriting, it is desirable that the program voltage and time that cause the change from the erased state to the written state, or vice versa, be the same. The threshold is approximately ■. It is desirable that it be equal to . Therefore,
In diagram M1, the threshold ML of the channel section controlled by float a date 5 is ■. , approximately equal to the city i hook?
-) The threshold value of the channel part controlled by the extension part of b is V. It is desirable that there be a VC between 1 and 1 o.
本発明は上記の如き要求を満たし、電気的消去および書
込みを＃１は同′昨圧の同時１ｉＪ１印加で行い潜るよ
うにした不揮発性半導体メモリ装置を提供する事を目的
としている。It is an object of the present invention to provide a non-volatile semiconductor memory device which satisfies the above requirements and performs electrical erasing and writing by simultaneously applying 1iJ1 of the same voltage to #1.
本発明に係るメモリ素子は、第３図にｌドす如く、浮遊
ｒ−ト５の一端に自己幣合して形成されるドレイン２（
またはソース）に接して、基孕と同電導型の尚濃度不純
物頭載７を設ける。As shown in FIG. 3, the memory device according to the present invention has a drain 2 (
An impurity head 7 of the same conductivity type as the substrate is provided in contact with the source (or the source).
それ以外は第１図と変らない。これにより、Ｉｌ−遊ダ
ート５下のチャネル部のしきい値を制御ｒ−トロ延在部
下のチャネル部のしきい値よりも大をなる様にしている
。Other than that, it is the same as Figure 1. As a result, the threshold value of the channel portion below the Il-free dirt 5 is made larger than the threshold value of the channel portion below the control r-toro extension.
本発明によれば、電気的書き換えが同電圧、同時間で行
えるイ・併発性半導体メモリ装置が実ｊＪａ−Ｃきる。According to the present invention, a concurrent semiconductor memory device in which electrical rewriting can be performed at the same voltage and in the same time can be realized.
しかも１％；、一度不純物領域７ｔよドレイン２の拡散
窓を−ｆｖ＞まま用いて拡散形成することができ、製造
−丁稲は（ｔｙ’−米に比べて１μＪら複雑ｔｒｃなる
ととｔまない。Moreover, once the impurity region 7t is 1%, the diffusion window of the drain 2 can be used as -fv> to form a diffusion. do not have.
以ト、本発明と−実り例を用いて詳しく♂発明−４る。Hereinafter, the present invention and the male invention-4 will be explained in detail using practical examples.
ｊｇ４図（ａ）〜（ｄ）は一実施例の散部の製造上、１
イを示し、ている。まずＰ型Ｓ％ノん也４１上に第１り
゛−ト酸化ＢＩＡ’４２１ を介して＃遊ケ”−ト４
３をル成しくａ）、次にこのＦに第２ケ゛−ト嘔化胛４
２２を介して劃−ブート４４４形成する（ｂ）、−飼り
′−ト４４はその一部１を浮遊デート４３の一端と（１
７首を合せ、他ψ１１１１枳１１ ｔｕ、 ＃遊ダート
４３のない羨城上に延在させて基板４１に直接対向させ
る。jg4 Figures (a) to (d) are 1
It shows and is true. First, the #free gate 4 is passed through the first oxidized BIA'421 onto the P-type S% non-ya 41.
3 to form a), then add the second number to this F.
22 to form a boot 444 (b), the boot 44 connects its part 1 to one end of the floating date 43 (1
7 necks are put together, and the other ψ1111 11 tu are made to extend over the top where there is no free dart 43 and directly face the substrate 41.
こｉｔらの）ｆ−ト４：ｉ、４４は例えは４０ （１０
人）６厚をもつ多結晶シリコンを用いて公知の方法によ
って形成される。For example, 44 is 40 (10
It is formed by a known method using polycrystalline silicon having a thickness of 6.6 mm.
次に、浮遊り°−ト４３と制−ｆ−ト４４が位置合せさ
れた端部下μ域のみ繕出する様に、例えはレノスト４５
によって不必要な部分をマスクし、Ｓｔ基板中へ高濃度
のＢ（ゲロン）を添加してＰ禰域４６を形成する（Ｃ）
。次にレジスト４５を除去し制＠）ｆ−）４４をマスク
として例えばＰ（リン）を添加してドレイン４７および
ソース４８を形成する（ｄ）。Next, repair only the region below the end where the floating float 43 and the restraint gate 44 are aligned, using a lennost 45, for example.
Unnecessary portions are masked by masking, and a high concentration of B (geron) is added into the St substrate to form a P area 46 (C).
. Next, the resist 45 is removed, and using the resist 44 as a mask, for example, P (phosphorus) is added to form a drain 47 and a source 48 (d).
第５図はこのメモリ素子の平面図であり、そのＡ −Ａ
’断面が第４図に対応する。FIG. 5 is a plan view of this memory element, and its A-A
'The cross section corresponds to FIG.
第５図に示すように、チャネル領域に近接してソース４
８と連続的に形成され九Ｍ４領域４９が設けられ、この
上に薄い（〜２０（ｌ Ｘ ）酸化膜を介して浮遊ゲー
ト４３の一部を延在させており、このＭ−１域４９でト
ンネル電流による書き換えが行われるようになっている
。As shown in FIG.
A nine M4 region 49 is formed continuously with the M-1 region 49, on which a part of the floating gate 43 is extended via a thin (~20(lx)) oxide film. Rewriting is performed using tunnel current.
このように構成されたメモリ素子は、浮遊ｒ−ト４３に
電荷の蓄積されていない時のしきい値が例えば５ｖ１ソ
ース４８．ドレイン４７を接地して制御ゲート４４に２
０Ｖのプログラム電圧パルスをｌ０ｍ５印加した時のし
きい値が例えばＩＯＶ、逆に制御ゲート４４を接地し、
ソ−ス４８に同じ・ぞルスを印加した時のしきい値は、
浮遊ｆ−ト４３の下がＯｖ以下になったとしてもそれ以
外の制御ゲート４４がおおう領域のしきい値１ｖで決ま
る。従って本メモリ素子では、情報の誓き換えは同じプ
ログラム電圧とプログラム時間で行える。The memory element configured in this manner has a threshold value of, for example, 5v1 source 48. The drain 47 is grounded and the control gate 44 is connected to the
For example, when the threshold value when applying a 0V program voltage pulse 10m5 is IOV, conversely, the control gate 44 is grounded,
The threshold value when the same voltage is applied to source 48 is
Even if the temperature below the floating gate 43 is below Ov, it is determined by the threshold value 1v of the area covered by the other control gates 44. Therefore, in this memory device, information can be exchanged using the same programming voltage and programming time.
他の実施例と１〜で、同じく電気的に書き換え可能な不
揮発性メモリで、かつ選択的な書き換えを可能とした記
憶素子に本発明を適用した場合について述べる。In other embodiments 1 to 1, a case will be described in which the present invention is applied to a memory element which is also an electrically rewritable nonvolatile memory and which allows selective rewritability.
第６図は平面図であり、第７図（ａ） 、 （ｂ）はそ
れぞれ第６図のＢ−Ｂ’、Ｃ−Ｃ’断面である。先の実
施例と異なる点は、ソース４８と共に行方向に連続的に
形成される制御ゲート４４を第２の制御ｆ−）とし、こ
れと浮遊ｆｆ−ト４３との間に、ドレイン４７と共に列
方向に連続的に形成される第１の制御ｆ−）５０を設け
ていること・）である。Ｃ−Ｃ’断面である第７図（ｂ）を見ると、先
の実施例でも説明したように薄い酸化膜によるトンネル
領域がｎ Ｓｍ域４９上に形成されている。FIG. 6 is a plan view, and FIGS. 7(a) and 7(b) are BB' and CC' cross sections in FIG. 6, respectively. The difference from the previous embodiment is that the control gate 44 which is formed continuously in the row direction together with the source 48 is used as a second control gate f-), and between this and the floating gate 43, the control gate 44 which is formed continuously in the row direction along with the drain 47 is The first control f-) 50 is provided continuously in the direction. Looking at FIG. 7(b), which is a cross section taken along the line C-C', a tunnel region made of a thin oxide film is formed on the n Sm region 49, as described in the previous embodiment.
本記憶素子は、浮遊ダート４３に電荷の？Ｅ人されてい
ない時のしきい値が５■で、ソース４８が接地され２つ
の制御’ｙ”−ト４４．ｓｏに同時に高電圧２０Ｖが印
加された時のみ誉込み状態に変化し、逆にソース４８が
ＳＩ′ｔｌＬ位となり、２つの制御ダート４４．５０が
接地された」助合に消去状態に変化する。この実施例で
も、浮遊ゲート４３下にこれら自己整合されたＰ ｆＡ
域４６を設けることにより、同じ電圧で同じ・９ルス幅
で書き換えを行うことができる。In this memory element, there is no charge on the floating dart 43? When the threshold value when no one is connected is 5■, the source 48 is grounded and a high voltage of 20V is simultaneously applied to the two control 'y'-to's 44.so. When the source 48 goes to SI'tlL and the two control darts 44 and 50 are grounded, the state changes to the erased state. In this embodiment as well, these self-aligned P fA under the floating gate 43
By providing the area 46, rewriting can be performed with the same voltage and the same 9 pulse width.
以上述べた如く、本発明によれば、電気的に誉き換え可
能でしかも省き換えの特性のバランスした不揮発性記憶
装置を得る事ができる。尚、上記の説明でＵＮチャネル
の場合についてのみ述べたが、本発明けＰチャネルでも
もちろん適用できる。 ”、、、、ＳAs described above, according to the present invention, it is possible to obtain a nonvolatile memory device that is electrically replaceable and has balanced replacement characteristics. In the above explanation, only the case of UN channel was described, but the present invention can of course be applied to P channel as well. ”,,,,S
第１図は従来の曹き換え可能な不揮発性メモリ素子の一
例を示す図、第２図はその転移特性を示す図、＠３図は
本発明に係るメモリ素子の基本構成を第１図に対応させ
て示す図、第４図（、）〜（ｄ）は本発明の一実施例の
メモリ素子の製造工程を説明するための図、第５図は同
メモリ素子の平面図、第６図に他の実施例のメモリ素子
の平面図、第７図（ａ） 、 （ｂ）はそれぞれ第６図
のＢ−Ｂ’、 Ｃ−Ｃ’断面図である。１・・・Ｐ型シリコン基板、２・・・ドレイン、３・・
・ソース、５・・・浮遊ダート、６・・・制御ｒ−）、
７・・・面濃度不純物領域（Ｐ＋）、４１・・・Ｐ型シ
リコン基板、 ４３ ・・ 浮遊 ケ０− ト 、
４４ ・・・制御ｒ−） 、４６・・・Ｐ１領域、
４７・・・ドレイン、４８・・・ソース、４９・・・ｎ
＋ｉ８頁域（書き換え領域）、５０・・・制御ｒ−ト
。出願人代理人 升理士 鈴 江 武 彦第１図第２図ｉ３Ｎ４図第５図第６図塩７図ムムFig. 1 is a diagram showing an example of a conventional non-volatile memory element that can be replaced, Fig. 2 is a diagram showing its transfer characteristics, and Fig. 3 is a diagram showing the basic configuration of a memory element according to the present invention. 4(a) to 4(d) are diagrams for explaining the manufacturing process of a memory element according to an embodiment of the present invention, FIG. 5 is a plan view of the same memory element, and FIG. 7(a) and 7(b) are sectional views taken along line BB' and line CC' in FIG. 6, respectively. 1... P-type silicon substrate, 2... drain, 3...
・Source, 5... Floating dirt, 6... Control r-),
7... Planar concentration impurity region (P+), 41... P-type silicon substrate, 43... floating ketone,
44...control r-), 46...P1 area,
47...Drain, 48...Source, 49...n
+i8 page area (rewriting area), 50...control r-t. Applicant's agent Suzue Takehiko Figure 1 Figure 2 i3N4 Figure 5 Figure 6 Salt Figure 7 Mumu
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57089162AJPS58206165A (en) | 1982-05-26 | 1982-05-26 | Non volatile semiconductor memory unit |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57089162AJPS58206165A (en) | 1982-05-26 | 1982-05-26 | Non volatile semiconductor memory unit |
| Publication Number | Publication Date |
|---|---|
| JPS58206165Atrue JPS58206165A (en) | 1983-12-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57089162APendingJPS58206165A (en) | 1982-05-26 | 1982-05-26 | Non volatile semiconductor memory unit |
| Country | Link |
|---|---|
| JP (1) | JPS58206165A (en) |
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|---|---|---|---|---|
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| US4861730A (en)* | 1988-01-25 | 1989-08-29 | Catalyst Semiconductor, Inc. | Process for making a high density split gate nonvolatile memory cell |
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| US5053842A (en)* | 1990-05-30 | 1991-10-01 | Seiko Instruments Inc. | Semiconductor nonvolatile memory |
| US5424567A (en)* | 1991-05-15 | 1995-06-13 | North American Philips Corporation | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
| US5486480A (en)* | 1991-05-15 | 1996-01-23 | North American Philips Corporation | Method of fabrication of protected programmable transistor with reduced parasitic capacitances |
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