JPS57170571A - Manufacture of mos type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the disconnection of a wire on a polysilicon and to reduce the superposition capacity between a gate, source and a drain by etching the side surface of the polysilicon after an ion implantation with two-layer mask of a mask material and a polysilicon layer. CONSTITUTION:A gate oxidized film 12 and a doped polysilicon 13 are laminated on a P type Si substrate 11, a resist mask 14 is covered, and a sputter etching is performed. Subsequently, with the resist 14 and the polysilicon 13 as masks P ions are implanted to form a source 15 and a drain 16. When an activation and depression are performed, the gate 13 extends downwardly in the amount corresponding to approx. (0.6-0.64)xj with respect to the depth xj. Then, when the vertical side surface of the polysilicon 13 is etched, a taper is produced due to the presence of the impurity density difference. When the etching amount at the lowermost end of the gate 13 is selected to (0.55-0.6)xj, the superposition of the gate 13 and the source 15, the drain 16 becomes approx. zero, the capacity becomes ultrafine, thereby accelerating the operation, and the disconnection can be prevented by the taper.