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JPS5713977A - Controlling for pwm inverter - Google Patents

Controlling for pwm inverter

Info

Publication number
JPS5713977A
JPS5713977AJP8777480AJP8777480AJPS5713977AJP S5713977 AJPS5713977 AJP S5713977AJP 8777480 AJP8777480 AJP 8777480AJP 8777480 AJP8777480 AJP 8777480AJP S5713977 AJPS5713977 AJP S5713977A
Authority
JP
Japan
Prior art keywords
circuit
pulses
received
transmits
different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8777480A
Other languages
Japanese (ja)
Inventor
Masahiro Koike
Mitsuaki Yonekawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Electric Industry Co Ltd
Original Assignee
Nippon Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Industry Co LtdfiledCriticalNippon Electric Industry Co Ltd
Priority to JP8777480ApriorityCriticalpatent/JPS5713977A/en
Publication of JPS5713977ApublicationCriticalpatent/JPS5713977A/en
Pendinglegal-statusCriticalCurrent

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Abstract

PURPOSE:To maintain the content of higher harmonic components at low value in a PWM inverter output wave by a methd wherein the pulse width ratio is kept constant at each of the multiple rectangular pulses generated during a half wave period. CONSTITUTION:A basic pulse generating circuit 2 receives clock pulses from a clock pulse generating circuit 1 and transmits rectangular pulses (c) whose width is different from the received clock pulses to an integration circuit 3. The integration circuit 3 changes the received rectangular pulses (c) into triangular pulses (d) of different height and transmits them to an amplitude variable circuit 4. The amplitude variable circuit 4 converts the received triangular pulses into ones of the same height and different bases and transmits them to a composite circuit 6. Output of the composite circuit 6 is subjected to sequential switching by timing signal forming circuit 5 timing signals and is received by a comparing circuit 7 in which a comparison is made to a reference voltage EO. During the period of a level higher than EO, gate signals are supplied to a singal forming circit 9, causing switching signals X, -X, and Y to be outputted. This method results in a decrease of higher harmonics in an inverter output.
JP8777480A1980-06-301980-06-30Controlling for pwm inverterPendingJPS5713977A (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
JP8777480AJPS5713977A (en)1980-06-301980-06-30Controlling for pwm inverter

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
JP8777480AJPS5713977A (en)1980-06-301980-06-30Controlling for pwm inverter

Publications (1)

Publication NumberPublication Date
JPS5713977Atrue JPS5713977A (en)1982-01-25

Family

ID=13924320

Family Applications (1)

Application NumberTitlePriority DateFiling Date
JP8777480APendingJPS5713977A (en)1980-06-301980-06-30Controlling for pwm inverter

Country Status (1)

CountryLink
JP (1)JPS5713977A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS59226671A (en)*1983-06-061984-12-19Kyosan Electric Mfg Co LtdSingle phase bridge inverter device
JPS6013477A (en)*1983-07-041985-01-23Kyosan Electric Mfg Co LtdMultiplex inverter device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS59226671A (en)*1983-06-061984-12-19Kyosan Electric Mfg Co LtdSingle phase bridge inverter device
JPS6013477A (en)*1983-07-041985-01-23Kyosan Electric Mfg Co LtdMultiplex inverter device

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