JPS5679472A - Preparing method of mos-type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an FET having a high integrated degree by embeding a gate electrode into an insulating layer and setting a poly-silicon or amorphous silicon channel thereon and a source drain at both sides thereof. CONSTITUTION:A poly-silicon 3 is laid on a SiO2 2 on a Si substrate 1. It is oxidized to change to SiO2 32 performing a mask 4. After demasking, it is covered with an oxide film 5 and a N<+> layer 5 is prepared injecting P-ion. Then, the poly- silicon 6 is selectively formed and the P-ion is injected to set the N<+> layer 8, 9 performing a resist mask 7. After removing the mask 7, the LASER is irradiated to activate it. Then, it is covered with SiO2 10 and Al electrodes 111, 112 are made by opening selectively. By this constitution, a smooth construction can be realized with poly-silicon film, thereby being capable of miniaturization and high integration of element without decreasing the reliability. Further, the combination with the conventional construction makes possible to obtain various kinds of devices.