JPS56169359A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To effectively prevent a latch-up of a semiconductor integrated circuit device due to a parasitic element by performing the steps of isolating elements and forming of a well with one mask in one step when providing a bipolar transistor and a complementary FET on the same substrate and reducing the number of steps. CONSTITUTION:When N<+> type layers 102, 103 are buried in a P type Si substrate 100, an N type epitaxial layer 104 is superposed thereon and N type wells 105, 106 are respectively formed via SiO2 mask 71 on the buried layers, they are isolated with the layer 104, the steps can be remarkably simplified as compared with the conventional process inexpensively and readily. Then, a mask 81 is formed, and P<+> type base 107, source 108, drain 109, and channels 111, 112 are formed. Then, a mask 91 is formed, N<+> type emitter 113, source 114, drain 115, and connecting layer 116 are formed, a gate oxidized film 119 and a gate electrode 120 are eventually formed, and prescribed electrodes 120-126 are then formed to complete the integrated circuit. According to this configuration, since the base width of the parasitic element with the layers 114-104-103 is large, its hfe is small and its latch- up can be effectively prevented.