JPS56150858A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To highly integrate and accelerate the operation of a vertical ROM by serially connecting an FET having a gate electrode of the first layer and an FET having a gate electrode of the second layer so disposed that the gate electrodes of the two layers are alternately contacted with one another. CONSTITUTION:A p<+> type diffused layer 2 is formed on an n type substrate 1, and a windowlike channel region 1a is formed on the substrate. The first layer gate electrodes 5 (polysilicon) are disposed at a predetermined interval through a gate film 3 on the region 1a. The second layer gate electrode 7 is so formed as to partly superpose with the first layer gate electrode 5 covered with an insulating layer 6. The respective gate electrodes of the two layers extend to be connected to the input unit. A p<+> type diffused layer 2 is connected to a power source, an output and an earth via aluminum electrode wires 8. Since the FETs are connected serially without providing a p<+> type diffused layer between the respective gates in this manner, it can reduce the predetermined area and the floating capacity of the vertical ROM. The modes of the respective FETs can be formed in any of E type or D type by selectively introducing impurity to the substrate at the lower parts of the respective gate regions.